blob: e1f574f9056945ac9b367a6fe0882d3ec0dd3e90 [file] [log] [blame]
Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Hans de Goedef07872b2015-04-06 20:33:34 +02003# Note only one of these may be selected at a time! But hidden choices are
4# not supported by Kconfig
5config SUNXI_GEN_SUN4I
6 bool
7 ---help---
8 Select this for sunxi SoCs which have resets and clocks set up
9 as the original A10 (mach-sun4i).
10
11config SUNXI_GEN_SUN6I
12 bool
13 ---help---
14 Select this for sunxi SoCs which have sun6i like periphery, like
15 separate ahb reset control registers, custom pmic bus, new style
16 watchdog, etc.
17
18
Ian Campbelld8e69e02014-10-24 21:20:44 +010019choice
20 prompt "Sunxi SoC Variant"
Joe Hershbergerf0699602015-05-12 14:46:23 -050021 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010022
Ian Campbell4a24a1c2014-10-24 21:20:45 +010023config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010024 bool "sun4i (Allwinner A10)"
25 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020026 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010027 select SUPPORT_SPL
28
Ian Campbell4a24a1c2014-10-24 21:20:45 +010029config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010030 bool "sun5i (Allwinner A13)"
31 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020032 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010033 select SUPPORT_SPL
34
Ian Campbell4a24a1c2014-10-24 21:20:45 +010035config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010036 bool "sun6i (Allwinner A31)"
37 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080038 select CPU_V7_HAS_NONSEC
39 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020040 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020041 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080042 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010043
Ian Campbell4a24a1c2014-10-24 21:20:45 +010044config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010045 bool "sun7i (Allwinner A20)"
46 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010047 select CPU_V7_HAS_NONSEC
48 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020049 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010050 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020051 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010052
Hans de Goedef055ed62015-04-06 20:55:39 +020053config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 bool "sun8i (Allwinner A23)"
55 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080056 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
Hans de Goedef07872b2015-04-06 20:33:34 +020058 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010059 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080060 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010061
Vishnu Patekar3702f142015-03-01 23:47:48 +053062config MACH_SUN8I_A33
63 bool "sun8i (Allwinner A33)"
64 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Vishnu Patekar3702f142015-03-01 23:47:48 +053067 select SUNXI_GEN_SUN6I
68 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080069 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +053070
Jens Kuskef9770722015-11-17 15:12:58 +010071config MACH_SUN8I_H3
72 bool "sun8i (Allwinner H3)"
73 select CPU_V7
74 select SUNXI_GEN_SUN6I
75
Hans de Goede7bfe2bb2015-01-13 19:25:06 +010076config MACH_SUN9I
77 bool "sun9i (Allwinner A80)"
78 select CPU_V7
79 select SUNXI_GEN_SUN6I
80
Ian Campbelld8e69e02014-10-24 21:20:44 +010081endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +080082
Hans de Goedef055ed62015-04-06 20:55:39 +020083# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
84config MACH_SUN8I
85 bool
Jens Kuskef9770722015-11-17 15:12:58 +010086 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3
Hans de Goedef055ed62015-04-06 20:55:39 +020087
88
Hans de Goede3aeaa282014-11-15 19:46:39 +010089config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +010090 int "sunxi dram clock speed"
91 default 312 if MACH_SUN6I || MACH_SUN8I
92 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +010093 ---help---
94 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goede06ddc452015-01-25 11:29:27 +010095 of 24.
Hans de Goede3aeaa282014-11-15 19:46:39 +010096
Siarhei Siamashka47359bb2015-02-01 00:27:06 +020097if MACH_SUN5I || MACH_SUN7I
98config DRAM_MBUS_CLK
99 int "sunxi mbus clock speed"
100 default 300
101 ---help---
102 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
103
104endif
105
Hans de Goede3aeaa282014-11-15 19:46:39 +0100106config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100107 int "sunxi dram zq value"
108 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
109 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100110 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100111 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100112
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200113config DRAM_ODT_EN
114 bool "sunxi dram odt enable"
115 default n if !MACH_SUN8I_A23
116 default y if MACH_SUN8I_A23
117 ---help---
118 Select this to enable dram odt (on die termination).
119
Hans de Goede59d9fc72015-01-17 14:24:55 +0100120if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
121config DRAM_EMR1
122 int "sunxi dram emr1 value"
123 default 0 if MACH_SUN4I
124 default 4 if MACH_SUN5I || MACH_SUN7I
125 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100126 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200127
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200128config DRAM_TPR3
129 hex "sunxi dram tpr3 value"
130 default 0
131 ---help---
132 Set the dram controller tpr3 parameter. This parameter configures
133 the delay on the command lane and also phase shifts, which are
134 applied for sampling incoming read data. The default value 0
135 means that no phase/delay adjustments are necessary. Properly
136 configuring this parameter increases reliability at high DRAM
137 clock speeds.
138
139config DRAM_DQS_GATING_DELAY
140 hex "sunxi dram dqs_gating_delay value"
141 default 0
142 ---help---
143 Set the dram controller dqs_gating_delay parmeter. Each byte
144 encodes the DQS gating delay for each byte lane. The delay
145 granularity is 1/4 cycle. For example, the value 0x05060606
146 means that the delay is 5 quarter-cycles for one lane (1.25
147 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
148 The default value 0 means autodetection. The results of hardware
149 autodetection are not very reliable and depend on the chip
150 temperature (sometimes producing different results on cold start
151 and warm reboot). But the accuracy of hardware autodetection
152 is usually good enough, unless running at really high DRAM
153 clocks speeds (up to 600MHz). If unsure, keep as 0.
154
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200155choice
156 prompt "sunxi dram timings"
157 default DRAM_TIMINGS_VENDOR_MAGIC
158 ---help---
159 Select the timings of the DDR3 chips.
160
161config DRAM_TIMINGS_VENDOR_MAGIC
162 bool "Magic vendor timings from Android"
163 ---help---
164 The same DRAM timings as in the Allwinner boot0 bootloader.
165
166config DRAM_TIMINGS_DDR3_1066F_1333H
167 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
168 ---help---
169 Use the timings of the standard JEDEC DDR3-1066F speed bin for
170 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
171 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
172 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
173 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
174 that down binning to DDR3-1066F is supported (because DDR3-1066F
175 uses a bit faster timings than DDR3-1333H).
176
177config DRAM_TIMINGS_DDR3_800E_1066G_1333J
178 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
179 ---help---
180 Use the timings of the slowest possible JEDEC speed bin for the
181 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
182 DDR3-800E, DDR3-1066G or DDR3-1333J.
183
184endchoice
185
Hans de Goede3aeaa282014-11-15 19:46:39 +0100186endif
187
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200188if MACH_SUN8I_A23
189config DRAM_ODT_CORRECTION
190 int "sunxi dram odt correction value"
191 default 0
192 ---help---
193 Set the dram odt correction value (range -255 - 255). In allwinner
194 fex files, this option is found in bits 8-15 of the u32 odt_en variable
195 in the [dram] section. When bit 31 of the odt_en variable is set
196 then the correction is negative. Usually the value for this is 0.
197endif
198
Iain Paton630df142015-03-28 10:26:38 +0000199config SYS_CLK_FREQ
200 default 912000000 if MACH_SUN7I
201 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
202
Maxime Ripard2c519412014-10-03 20:16:29 +0800203config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100204 default "sun4i" if MACH_SUN4I
205 default "sun5i" if MACH_SUN5I
206 default "sun6i" if MACH_SUN6I
207 default "sun7i" if MACH_SUN7I
208 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100209 default "sun9i" if MACH_SUN9I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900210
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900211config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900212 default "sunxi"
213
214config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900215 default "sunxi"
216
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200217config UART0_PORT_F
218 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200219 default n
220 ---help---
221 Repurpose the SD card slot for getting access to the UART0 serial
222 console. Primarily useful only for low level u-boot debugging on
223 tablets, where normal UART0 is difficult to access and requires
224 device disassembly and/or soldering. As the SD card can't be used
225 at the same time, the system can be only booted in the FEL mode.
226 Only enable this if you really know what you are doing.
227
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200228config OLD_SUNXI_KERNEL_COMPAT
229 boolean "Enable workarounds for booting old kernels"
230 default n
231 ---help---
232 Set this to enable various workarounds for old kernels, this results in
233 sub-optimal settings for newer kernels, only enable if needed.
234
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200235config MMC
236 depends on !UART0_PORT_F
237 default y if ARCH_SUNXI
238
Hans de Goede7412ef82014-10-02 20:29:26 +0200239config MMC0_CD_PIN
240 string "Card detect pin for mmc0"
241 default ""
242 ---help---
243 Set the card detect pin for mmc0, leave empty to not use cd. This
244 takes a string in the format understood by sunxi_name_to_gpio, e.g.
245 PH1 for pin 1 of port H.
246
247config MMC1_CD_PIN
248 string "Card detect pin for mmc1"
249 default ""
250 ---help---
251 See MMC0_CD_PIN help text.
252
253config MMC2_CD_PIN
254 string "Card detect pin for mmc2"
255 default ""
256 ---help---
257 See MMC0_CD_PIN help text.
258
259config MMC3_CD_PIN
260 string "Card detect pin for mmc3"
261 default ""
262 ---help---
263 See MMC0_CD_PIN help text.
264
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100265config MMC1_PINS
266 string "Pins for mmc1"
267 default ""
268 ---help---
269 Set the pins used for mmc1, when applicable. This takes a string in the
270 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
271
272config MMC2_PINS
273 string "Pins for mmc2"
274 default ""
275 ---help---
276 See MMC1_PINS help text.
277
278config MMC3_PINS
279 string "Pins for mmc3"
280 default ""
281 ---help---
282 See MMC1_PINS help text.
283
Hans de Goedeaf593e42014-10-02 20:43:50 +0200284config MMC_SUNXI_SLOT_EXTRA
285 int "mmc extra slot number"
286 default -1
287 ---help---
288 sunxi builds always enable mmc0, some boards also have a second sdcard
289 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
290 support for this.
291
Hans de Goedee7b852a2015-01-07 15:26:06 +0100292config USB0_VBUS_PIN
293 string "Vbus enable pin for usb0 (otg)"
294 default ""
295 ---help---
296 Set the Vbus enable pin for usb0 (otg). This takes a string in the
297 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
298
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100299config USB0_VBUS_DET
300 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100301 default ""
302 ---help---
303 Set the Vbus detect pin for usb0 (otg). This takes a string in the
304 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
305
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200306config USB0_ID_DET
307 string "ID detect pin for usb0 (otg)"
308 default ""
309 ---help---
310 Set the ID detect pin for usb0 (otg). This takes a string in the
311 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
312
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100313config USB1_VBUS_PIN
314 string "Vbus enable pin for usb1 (ehci0)"
315 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100316 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100317 ---help---
318 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
319 a string in the format understood by sunxi_name_to_gpio, e.g.
320 PH1 for pin 1 of port H.
321
322config USB2_VBUS_PIN
323 string "Vbus enable pin for usb2 (ehci1)"
324 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100325 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100326 ---help---
327 See USB1_VBUS_PIN help text.
328
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200329config I2C0_ENABLE
330 bool "Enable I2C/TWI controller 0"
331 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
332 default n if MACH_SUN6I || MACH_SUN8I
333 ---help---
334 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
335 its clock and setting up the bus. This is especially useful on devices
336 with slaves connected to the bus or with pins exposed through e.g. an
337 expansion port/header.
338
339config I2C1_ENABLE
340 bool "Enable I2C/TWI controller 1"
341 default n
342 ---help---
343 See I2C0_ENABLE help text.
344
345config I2C2_ENABLE
346 bool "Enable I2C/TWI controller 2"
347 default n
348 ---help---
349 See I2C0_ENABLE help text.
350
351if MACH_SUN6I || MACH_SUN7I
352config I2C3_ENABLE
353 bool "Enable I2C/TWI controller 3"
354 default n
355 ---help---
356 See I2C0_ENABLE help text.
357endif
358
359if MACH_SUN7I
360config I2C4_ENABLE
361 bool "Enable I2C/TWI controller 4"
362 default n
363 ---help---
364 See I2C0_ENABLE help text.
365endif
366
Hans de Goede3ae1d132015-04-25 17:25:14 +0200367config AXP_GPIO
368 boolean "Enable support for gpio-s on axp PMICs"
369 default n
370 ---help---
371 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
372
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200373config VIDEO
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100374 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200375 default y
376 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100377 Say Y here to add support for using a cfb console on the HDMI, LCD
378 or VGA output found on most sunxi devices. See doc/README.video for
379 info on how to select the video output and mode.
380
Hans de Goedee9544592014-12-23 23:04:35 +0100381config VIDEO_HDMI
382 boolean "HDMI output support"
383 depends on VIDEO && !MACH_SUN8I
384 default y
385 ---help---
386 Say Y here to add support for outputting video over HDMI.
387
Hans de Goede260f5202014-12-25 13:58:06 +0100388config VIDEO_VGA
389 boolean "VGA output support"
390 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
391 default n
392 ---help---
393 Say Y here to add support for outputting video over VGA.
394
Hans de Goedeac1633c2014-12-24 12:17:07 +0100395config VIDEO_VGA_VIA_LCD
396 boolean "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800397 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100398 default n
399 ---help---
400 Say Y here to add support for external DACs connected to the parallel
401 LCD interface driving a VGA connector, such as found on the
402 Olimex A13 boards.
403
Hans de Goede18366f72015-01-25 15:33:07 +0100404config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
405 boolean "Force sync active high for VGA via LCD controller support"
406 depends on VIDEO_VGA_VIA_LCD
407 default n
408 ---help---
409 Say Y here if you've a board which uses opendrain drivers for the vga
410 hsync and vsync signals. Opendrain drivers cannot generate steep enough
411 positive edges for a stable video output, so on boards with opendrain
412 drivers the sync signals must always be active high.
413
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800414config VIDEO_VGA_EXTERNAL_DAC_EN
415 string "LCD panel power enable pin"
416 depends on VIDEO_VGA_VIA_LCD
417 default ""
418 ---help---
419 Set the enable pin for the external VGA DAC. This takes a string in the
420 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
421
Hans de Goedec06e00e2015-08-03 19:20:26 +0200422config VIDEO_COMPOSITE
423 boolean "Composite video output support"
424 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
425 default n
426 ---help---
427 Say Y here to add support for outputting composite video.
428
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100429config VIDEO_LCD_MODE
430 string "LCD panel timing details"
431 depends on VIDEO
432 default ""
433 ---help---
434 LCD panel timing details string, leave empty if there is no LCD panel.
435 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
436 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200437 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100438
Hans de Goede481b6642015-01-13 13:21:46 +0100439config VIDEO_LCD_DCLK_PHASE
440 int "LCD panel display clock phase"
441 depends on VIDEO
442 default 1
443 ---help---
444 Select LCD panel display clock phase shift, range 0-3.
445
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100446config VIDEO_LCD_POWER
447 string "LCD panel power enable pin"
448 depends on VIDEO
449 default ""
450 ---help---
451 Set the power enable pin for the LCD panel. This takes a string in the
452 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
453
Hans de Goedece9e3322015-02-16 17:26:41 +0100454config VIDEO_LCD_RESET
455 string "LCD panel reset pin"
456 depends on VIDEO
457 default ""
458 ---help---
459 Set the reset pin for the LCD panel. This takes a string in the format
460 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
461
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100462config VIDEO_LCD_BL_EN
463 string "LCD panel backlight enable pin"
464 depends on VIDEO
465 default ""
466 ---help---
467 Set the backlight enable pin for the LCD panel. This takes a string in the
468 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
469 port H.
470
471config VIDEO_LCD_BL_PWM
472 string "LCD panel backlight pwm pin"
473 depends on VIDEO
474 default ""
475 ---help---
476 Set the backlight pwm pin for the LCD panel. This takes a string in the
477 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200478
Hans de Goede2d5d3022015-01-22 21:02:42 +0100479config VIDEO_LCD_BL_PWM_ACTIVE_LOW
480 bool "LCD panel backlight pwm is inverted"
481 depends on VIDEO
482 default y
483 ---help---
484 Set this if the backlight pwm output is active low.
485
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100486config VIDEO_LCD_PANEL_I2C
487 bool "LCD panel needs to be configured via i2c"
488 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100489 default n
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100490 ---help---
491 Say y here if the LCD panel needs to be configured via i2c. This
492 will add a bitbang i2c controller using gpios to talk to the LCD.
493
494config VIDEO_LCD_PANEL_I2C_SDA
495 string "LCD panel i2c interface SDA pin"
496 depends on VIDEO_LCD_PANEL_I2C
497 default "PG12"
498 ---help---
499 Set the SDA pin for the LCD i2c interface. This takes a string in the
500 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
501
502config VIDEO_LCD_PANEL_I2C_SCL
503 string "LCD panel i2c interface SCL pin"
504 depends on VIDEO_LCD_PANEL_I2C
505 default "PG10"
506 ---help---
507 Set the SCL pin for the LCD i2c interface. This takes a string in the
508 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
509
Hans de Goede797a0f52015-01-01 22:04:34 +0100510
511# Note only one of these may be selected at a time! But hidden choices are
512# not supported by Kconfig
513config VIDEO_LCD_IF_PARALLEL
514 bool
515
516config VIDEO_LCD_IF_LVDS
517 bool
518
519
520choice
521 prompt "LCD panel support"
522 depends on VIDEO
523 ---help---
524 Select which type of LCD panel to support.
525
526config VIDEO_LCD_PANEL_PARALLEL
527 bool "Generic parallel interface LCD panel"
528 select VIDEO_LCD_IF_PARALLEL
529
530config VIDEO_LCD_PANEL_LVDS
531 bool "Generic lvds interface LCD panel"
532 select VIDEO_LCD_IF_LVDS
533
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200534config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
535 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
536 select VIDEO_LCD_SSD2828
537 select VIDEO_LCD_IF_PARALLEL
538 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200539 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
540
541config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
542 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
543 select VIDEO_LCD_ANX9804
544 select VIDEO_LCD_IF_PARALLEL
545 select VIDEO_LCD_PANEL_I2C
546 ---help---
547 Select this for eDP LCD panels with 4 lanes running at 1.62G,
548 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200549
Hans de Goede743fb9552015-01-20 09:23:36 +0100550config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
551 bool "Hitachi tx18d42vm LCD panel"
552 select VIDEO_LCD_HITACHI_TX18D42VM
553 select VIDEO_LCD_IF_LVDS
554 ---help---
555 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
556
Hans de Goede613dade2015-02-16 17:49:47 +0100557config VIDEO_LCD_TL059WV5C0
558 bool "tl059wv5c0 LCD panel"
559 select VIDEO_LCD_PANEL_I2C
560 select VIDEO_LCD_IF_PARALLEL
561 ---help---
562 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
563 Aigo M60/M608/M606 tablets.
564
Hans de Goede797a0f52015-01-01 22:04:34 +0100565endchoice
566
567
Hans de Goedebf880fe2015-01-25 12:10:48 +0100568config GMAC_TX_DELAY
569 int "GMAC Transmit Clock Delay Chain"
570 default 0
571 ---help---
572 Set the GMAC Transmit Clock Delay Chain value.
573
Hans de Goede66ab79d2015-09-13 13:02:48 +0200574config SPL_STACK_R_ADDR
575 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
576 default 0x2fe00000 if MACH_SUN9I
577
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900578endif