blob: 00011331b9810661f52562a248657ac9c1fe86b1 [file] [log] [blame]
Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Siva Durga Prasad Paladugu809438d2016-07-29 15:31:47 +05303config IDENT_STRING
4 default " Allwinner Technology"
5
Simon Glasse304a5e2016-10-17 20:12:36 -06006config PRE_CONSOLE_BUFFER
7 default y
8
Simon Glass0bdfc3e2016-09-12 23:18:39 -06009config SPL_GPIO_SUPPORT
10 default y
11
Simon Glassf2a89462016-09-12 23:18:41 -060012config SPL_LIBCOMMON_SUPPORT
13 default y
14
Simon Glassf6de2572016-09-12 23:18:42 -060015config SPL_LIBDISK_SUPPORT
16 default y
17
Simon Glassb16c92c2016-09-12 23:18:43 -060018config SPL_LIBGENERIC_SUPPORT
19 default y
20
Simon Glassbd58f1d2016-09-12 23:18:44 -060021config SPL_MMC_SUPPORT
22 default y
23
Simon Glass0d7c7e02016-09-12 23:18:54 -060024config SPL_POWER_SUPPORT
25 default y
26
Simon Glasse076d6f2016-09-12 23:18:56 -060027config SPL_SERIAL_SUPPORT
28 default y
29
Hans de Goedef07872b2015-04-06 20:33:34 +020030# Note only one of these may be selected at a time! But hidden choices are
31# not supported by Kconfig
32config SUNXI_GEN_SUN4I
33 bool
34 ---help---
35 Select this for sunxi SoCs which have resets and clocks set up
36 as the original A10 (mach-sun4i).
37
38config SUNXI_GEN_SUN6I
39 bool
40 ---help---
41 Select this for sunxi SoCs which have sun6i like periphery, like
42 separate ahb reset control registers, custom pmic bus, new style
43 watchdog, etc.
44
45
Ian Campbelld8e69e02014-10-24 21:20:44 +010046choice
47 prompt "Sunxi SoC Variant"
Hans de Goedeb05a6482016-06-12 11:57:07 +020048 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010049
Ian Campbell4a24a1c2014-10-24 21:20:45 +010050config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010051 bool "sun4i (Allwinner A10)"
52 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 select SUPPORT_SPL
55
Ian Campbell4a24a1c2014-10-24 21:20:45 +010056config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010057 bool "sun5i (Allwinner A13)"
58 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020059 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010060 select SUPPORT_SPL
61
Ian Campbell4a24a1c2014-10-24 21:20:45 +010062config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010063 bool "sun6i (Allwinner A31)"
64 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090067 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020068 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020069 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080070 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010071
Ian Campbell4a24a1c2014-10-24 21:20:45 +010072config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010073 bool "sun7i (Allwinner A20)"
74 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010075 select CPU_V7_HAS_NONSEC
76 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090077 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020078 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010079 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020080 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010081
Hans de Goedef055ed62015-04-06 20:55:39 +020082config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010083 bool "sun8i (Allwinner A23)"
84 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080085 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090087 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020088 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010089 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080090 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010091
Vishnu Patekar3702f142015-03-01 23:47:48 +053092config MACH_SUN8I_A33
93 bool "sun8i (Allwinner A33)"
94 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080095 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090097 select ARCH_SUPPORT_PSCI
Vishnu Patekar3702f142015-03-01 23:47:48 +053098 select SUNXI_GEN_SUN6I
99 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +0800100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +0530101
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800102config MACH_SUN8I_A83T
103 bool "sun8i (Allwinner A83T)"
104 select CPU_V7
105 select SUNXI_GEN_SUN6I
106 select SUPPORT_SPL
107
Jens Kuskef9770722015-11-17 15:12:58 +0100108config MACH_SUN8I_H3
109 bool "sun8i (Allwinner H3)"
110 select CPU_V7
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800111 select CPU_V7_HAS_NONSEC
112 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900113 select ARCH_SUPPORT_PSCI
Jens Kuskef9770722015-11-17 15:12:58 +0100114 select SUNXI_GEN_SUN6I
Jens Kuske53f018e2015-11-17 15:12:59 +0100115 select SUPPORT_SPL
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800116 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +0100117
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100118config MACH_SUN9I
119 bool "sun9i (Allwinner A80)"
120 select CPU_V7
121 select SUNXI_GEN_SUN6I
Philipp Tomsich470626e2016-10-28 18:21:32 +0800122 select SUPPORT_SPL
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100123
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800124config MACH_SUN50I
125 bool "sun50i (Allwinner A64)"
126 select ARM64
127 select SUNXI_GEN_SUN6I
Andre Przywaraa563adc2017-01-02 11:48:45 +0000128 select SUPPORT_SPL
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800129
Ian Campbelld8e69e02014-10-24 21:20:44 +0100130endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +0800131
Hans de Goedef055ed62015-04-06 20:55:39 +0200132# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
133config MACH_SUN8I
134 bool
vishnupatekarcdf1e482015-11-29 01:07:19 +0800135 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goedef055ed62015-04-06 20:55:39 +0200136
Andre Przywara06893b62017-01-02 11:48:35 +0000137config RESERVE_ALLWINNER_BOOT0_HEADER
138 bool "reserve space for Allwinner boot0 header"
139 select ENABLE_ARM_SOC_BOOT0_HOOK
140 ---help---
141 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
142 filled with magic values post build. The Allwinner provided boot0
143 blob relies on this information to load and execute U-Boot.
144 Only needed on 64-bit Allwinner boards so far when using boot0.
145
Andre Przywara46c3d992017-01-02 11:48:36 +0000146config ARM_BOOT_HOOK_RMR
147 bool
148 depends on ARM64
149 default y
150 select ENABLE_ARM_SOC_BOOT0_HOOK
151 ---help---
152 Insert some ARM32 code at the very beginning of the U-Boot binary
153 which uses an RMR register write to bring the core into AArch64 mode.
154 The very first instruction acts as a switch, since it's carefully
155 chosen to be a NOP in one mode and a branch in the other, so the
156 code would only be executed if not already in AArch64.
157 This allows both the SPL and the U-Boot proper to be entered in
158 either mode and switch to AArch64 if needed.
159
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800160config DRAM_TYPE
161 int "sunxi dram type"
162 depends on MACH_SUN8I_A83T
163 default 3
164 ---help---
165 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200166
Hans de Goede3aeaa282014-11-15 19:46:39 +0100167config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100168 int "sunxi dram clock speed"
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800169 default 792 if MACH_SUN9I
Hans de Goede59d9fc72015-01-17 14:24:55 +0100170 default 312 if MACH_SUN6I || MACH_SUN8I
171 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Andre Przywaraafd68702017-01-02 11:48:37 +0000172 default 672 if MACH_SUN50I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100173 ---help---
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800174 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
175 must be a multiple of 24. For the sun9i (A80), the tested values
176 (for DDR3-1600) are 312 to 792.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100177
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200178if MACH_SUN5I || MACH_SUN7I
179config DRAM_MBUS_CLK
180 int "sunxi mbus clock speed"
181 default 300
182 ---help---
183 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
184
185endif
186
Hans de Goede3aeaa282014-11-15 19:46:39 +0100187config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100188 int "sunxi dram zq value"
189 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
190 default 127 if MACH_SUN7I
Chen-Yu Tsai47bb3062016-10-28 18:21:36 +0800191 default 4145117 if MACH_SUN9I
Andre Przywaraafd68702017-01-02 11:48:37 +0000192 default 3881915 if MACH_SUN50I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100193 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100194 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100195
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200196config DRAM_ODT_EN
197 bool "sunxi dram odt enable"
198 default n if !MACH_SUN8I_A23
199 default y if MACH_SUN8I_A23
Andre Przywaraa563adc2017-01-02 11:48:45 +0000200 default y if MACH_SUN50I
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200201 ---help---
202 Select this to enable dram odt (on die termination).
203
Hans de Goede59d9fc72015-01-17 14:24:55 +0100204if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
205config DRAM_EMR1
206 int "sunxi dram emr1 value"
207 default 0 if MACH_SUN4I
208 default 4 if MACH_SUN5I || MACH_SUN7I
209 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100210 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200211
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200212config DRAM_TPR3
213 hex "sunxi dram tpr3 value"
214 default 0
215 ---help---
216 Set the dram controller tpr3 parameter. This parameter configures
217 the delay on the command lane and also phase shifts, which are
218 applied for sampling incoming read data. The default value 0
219 means that no phase/delay adjustments are necessary. Properly
220 configuring this parameter increases reliability at high DRAM
221 clock speeds.
222
223config DRAM_DQS_GATING_DELAY
224 hex "sunxi dram dqs_gating_delay value"
225 default 0
226 ---help---
227 Set the dram controller dqs_gating_delay parmeter. Each byte
228 encodes the DQS gating delay for each byte lane. The delay
229 granularity is 1/4 cycle. For example, the value 0x05060606
230 means that the delay is 5 quarter-cycles for one lane (1.25
231 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
232 The default value 0 means autodetection. The results of hardware
233 autodetection are not very reliable and depend on the chip
234 temperature (sometimes producing different results on cold start
235 and warm reboot). But the accuracy of hardware autodetection
236 is usually good enough, unless running at really high DRAM
237 clocks speeds (up to 600MHz). If unsure, keep as 0.
238
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200239choice
240 prompt "sunxi dram timings"
241 default DRAM_TIMINGS_VENDOR_MAGIC
242 ---help---
243 Select the timings of the DDR3 chips.
244
245config DRAM_TIMINGS_VENDOR_MAGIC
246 bool "Magic vendor timings from Android"
247 ---help---
248 The same DRAM timings as in the Allwinner boot0 bootloader.
249
250config DRAM_TIMINGS_DDR3_1066F_1333H
251 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
252 ---help---
253 Use the timings of the standard JEDEC DDR3-1066F speed bin for
254 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
255 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
256 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
257 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
258 that down binning to DDR3-1066F is supported (because DDR3-1066F
259 uses a bit faster timings than DDR3-1333H).
260
261config DRAM_TIMINGS_DDR3_800E_1066G_1333J
262 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
263 ---help---
264 Use the timings of the slowest possible JEDEC speed bin for the
265 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
266 DDR3-800E, DDR3-1066G or DDR3-1333J.
267
268endchoice
269
Hans de Goede3aeaa282014-11-15 19:46:39 +0100270endif
271
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200272if MACH_SUN8I_A23
273config DRAM_ODT_CORRECTION
274 int "sunxi dram odt correction value"
275 default 0
276 ---help---
277 Set the dram odt correction value (range -255 - 255). In allwinner
278 fex files, this option is found in bits 8-15 of the u32 odt_en variable
279 in the [dram] section. When bit 31 of the odt_en variable is set
280 then the correction is negative. Usually the value for this is 0.
281endif
282
Iain Paton630df142015-03-28 10:26:38 +0000283config SYS_CLK_FREQ
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200284 default 816000000 if MACH_SUN50I
Iain Paton630df142015-03-28 10:26:38 +0000285 default 912000000 if MACH_SUN7I
Chen-Yu Tsai40884e62016-10-28 18:21:34 +0800286 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
Iain Paton630df142015-03-28 10:26:38 +0000287
Maxime Ripard2c519412014-10-03 20:16:29 +0800288config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100289 default "sun4i" if MACH_SUN4I
290 default "sun5i" if MACH_SUN5I
291 default "sun6i" if MACH_SUN6I
292 default "sun7i" if MACH_SUN7I
293 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100294 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200295 default "sun50i" if MACH_SUN50I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900296
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900297config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900298 default "sunxi"
299
300config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900301 default "sunxi"
302
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200303config UART0_PORT_F
304 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200305 default n
306 ---help---
307 Repurpose the SD card slot for getting access to the UART0 serial
308 console. Primarily useful only for low level u-boot debugging on
309 tablets, where normal UART0 is difficult to access and requires
310 device disassembly and/or soldering. As the SD card can't be used
311 at the same time, the system can be only booted in the FEL mode.
312 Only enable this if you really know what you are doing.
313
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200314config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900315 bool "Enable workarounds for booting old kernels"
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200316 default n
317 ---help---
318 Set this to enable various workarounds for old kernels, this results in
319 sub-optimal settings for newer kernels, only enable if needed.
320
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200321config MMC
322 depends on !UART0_PORT_F
323 default y if ARCH_SUNXI
324
Hans de Goede7412ef82014-10-02 20:29:26 +0200325config MMC0_CD_PIN
326 string "Card detect pin for mmc0"
Chen-Yu Tsai36741482016-05-02 10:28:08 +0800327 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goede7412ef82014-10-02 20:29:26 +0200328 default ""
329 ---help---
330 Set the card detect pin for mmc0, leave empty to not use cd. This
331 takes a string in the format understood by sunxi_name_to_gpio, e.g.
332 PH1 for pin 1 of port H.
333
334config MMC1_CD_PIN
335 string "Card detect pin for mmc1"
336 default ""
337 ---help---
338 See MMC0_CD_PIN help text.
339
340config MMC2_CD_PIN
341 string "Card detect pin for mmc2"
342 default ""
343 ---help---
344 See MMC0_CD_PIN help text.
345
346config MMC3_CD_PIN
347 string "Card detect pin for mmc3"
348 default ""
349 ---help---
350 See MMC0_CD_PIN help text.
351
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100352config MMC1_PINS
353 string "Pins for mmc1"
354 default ""
355 ---help---
356 Set the pins used for mmc1, when applicable. This takes a string in the
357 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
358
359config MMC2_PINS
360 string "Pins for mmc2"
361 default ""
362 ---help---
363 See MMC1_PINS help text.
364
365config MMC3_PINS
366 string "Pins for mmc3"
367 default ""
368 ---help---
369 See MMC1_PINS help text.
370
Hans de Goedeaf593e42014-10-02 20:43:50 +0200371config MMC_SUNXI_SLOT_EXTRA
372 int "mmc extra slot number"
373 default -1
374 ---help---
375 sunxi builds always enable mmc0, some boards also have a second sdcard
376 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
377 support for this.
378
Hans de Goede99c9fb02016-04-01 22:39:26 +0200379config INITIAL_USB_SCAN_DELAY
380 int "delay initial usb scan by x ms to allow builtin devices to init"
381 default 0
382 ---help---
383 Some boards have on board usb devices which need longer than the
384 USB spec's 1 second to connect from board powerup. Set this config
385 option to a non 0 value to add an extra delay before the first usb
386 bus scan.
387
Hans de Goedee7b852a2015-01-07 15:26:06 +0100388config USB0_VBUS_PIN
389 string "Vbus enable pin for usb0 (otg)"
390 default ""
391 ---help---
392 Set the Vbus enable pin for usb0 (otg). This takes a string in the
393 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
394
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100395config USB0_VBUS_DET
396 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100397 default ""
398 ---help---
399 Set the Vbus detect pin for usb0 (otg). This takes a string in the
400 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
401
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200402config USB0_ID_DET
403 string "ID detect pin for usb0 (otg)"
404 default ""
405 ---help---
406 Set the ID detect pin for usb0 (otg). This takes a string in the
407 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
408
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100409config USB1_VBUS_PIN
410 string "Vbus enable pin for usb1 (ehci0)"
411 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100412 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100413 ---help---
414 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
415 a string in the format understood by sunxi_name_to_gpio, e.g.
416 PH1 for pin 1 of port H.
417
418config USB2_VBUS_PIN
419 string "Vbus enable pin for usb2 (ehci1)"
420 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100421 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100422 ---help---
423 See USB1_VBUS_PIN help text.
424
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100425config USB3_VBUS_PIN
426 string "Vbus enable pin for usb3 (ehci2)"
427 default ""
428 ---help---
429 See USB1_VBUS_PIN help text.
430
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200431config I2C0_ENABLE
432 bool "Enable I2C/TWI controller 0"
433 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
434 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede2c526402016-05-15 13:51:58 +0200435 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200436 ---help---
437 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
438 its clock and setting up the bus. This is especially useful on devices
439 with slaves connected to the bus or with pins exposed through e.g. an
440 expansion port/header.
441
442config I2C1_ENABLE
443 bool "Enable I2C/TWI controller 1"
444 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200445 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200446 ---help---
447 See I2C0_ENABLE help text.
448
449config I2C2_ENABLE
450 bool "Enable I2C/TWI controller 2"
451 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200452 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200453 ---help---
454 See I2C0_ENABLE help text.
455
456if MACH_SUN6I || MACH_SUN7I
457config I2C3_ENABLE
458 bool "Enable I2C/TWI controller 3"
459 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200460 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200461 ---help---
462 See I2C0_ENABLE help text.
463endif
464
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100465if SUNXI_GEN_SUN6I
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100466config R_I2C_ENABLE
467 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100468 # This is used for the pmic on H3
469 default y if SY8106A_POWER
Hans de Goede2c526402016-05-15 13:51:58 +0200470 select CMD_I2C
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100471 ---help---
472 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100473endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100474
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200475if MACH_SUN7I
476config I2C4_ENABLE
477 bool "Enable I2C/TWI controller 4"
478 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200479 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200480 ---help---
481 See I2C0_ENABLE help text.
482endif
483
Hans de Goede3ae1d132015-04-25 17:25:14 +0200484config AXP_GPIO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900485 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede3ae1d132015-04-25 17:25:14 +0200486 default n
487 ---help---
488 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
489
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200490config VIDEO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900491 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywara8f977272016-09-05 01:32:40 +0100492 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200493 default y
494 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100495 Say Y here to add support for using a cfb console on the HDMI, LCD
496 or VGA output found on most sunxi devices. See doc/README.video for
497 info on how to select the video output and mode.
498
Hans de Goedee9544592014-12-23 23:04:35 +0100499config VIDEO_HDMI
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900500 bool "HDMI output support"
Hans de Goedee9544592014-12-23 23:04:35 +0100501 depends on VIDEO && !MACH_SUN8I
502 default y
503 ---help---
504 Say Y here to add support for outputting video over HDMI.
505
Hans de Goede260f5202014-12-25 13:58:06 +0100506config VIDEO_VGA
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900507 bool "VGA output support"
Hans de Goede260f5202014-12-25 13:58:06 +0100508 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
509 default n
510 ---help---
511 Say Y here to add support for outputting video over VGA.
512
Hans de Goedeac1633c2014-12-24 12:17:07 +0100513config VIDEO_VGA_VIA_LCD
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900514 bool "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800515 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100516 default n
517 ---help---
518 Say Y here to add support for external DACs connected to the parallel
519 LCD interface driving a VGA connector, such as found on the
520 Olimex A13 boards.
521
Hans de Goede18366f72015-01-25 15:33:07 +0100522config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900523 bool "Force sync active high for VGA via LCD controller support"
Hans de Goede18366f72015-01-25 15:33:07 +0100524 depends on VIDEO_VGA_VIA_LCD
525 default n
526 ---help---
527 Say Y here if you've a board which uses opendrain drivers for the vga
528 hsync and vsync signals. Opendrain drivers cannot generate steep enough
529 positive edges for a stable video output, so on boards with opendrain
530 drivers the sync signals must always be active high.
531
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800532config VIDEO_VGA_EXTERNAL_DAC_EN
533 string "LCD panel power enable pin"
534 depends on VIDEO_VGA_VIA_LCD
535 default ""
536 ---help---
537 Set the enable pin for the external VGA DAC. This takes a string in the
538 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
539
Hans de Goedec06e00e2015-08-03 19:20:26 +0200540config VIDEO_COMPOSITE
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900541 bool "Composite video output support"
Hans de Goedec06e00e2015-08-03 19:20:26 +0200542 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
543 default n
544 ---help---
545 Say Y here to add support for outputting composite video.
546
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100547config VIDEO_LCD_MODE
548 string "LCD panel timing details"
549 depends on VIDEO
550 default ""
551 ---help---
552 LCD panel timing details string, leave empty if there is no LCD panel.
553 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
554 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200555 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100556
Hans de Goede481b6642015-01-13 13:21:46 +0100557config VIDEO_LCD_DCLK_PHASE
558 int "LCD panel display clock phase"
559 depends on VIDEO
560 default 1
561 ---help---
562 Select LCD panel display clock phase shift, range 0-3.
563
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100564config VIDEO_LCD_POWER
565 string "LCD panel power enable pin"
566 depends on VIDEO
567 default ""
568 ---help---
569 Set the power enable pin for the LCD panel. This takes a string in the
570 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
571
Hans de Goedece9e3322015-02-16 17:26:41 +0100572config VIDEO_LCD_RESET
573 string "LCD panel reset pin"
574 depends on VIDEO
575 default ""
576 ---help---
577 Set the reset pin for the LCD panel. This takes a string in the format
578 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
579
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100580config VIDEO_LCD_BL_EN
581 string "LCD panel backlight enable pin"
582 depends on VIDEO
583 default ""
584 ---help---
585 Set the backlight enable pin for the LCD panel. This takes a string in the
586 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
587 port H.
588
589config VIDEO_LCD_BL_PWM
590 string "LCD panel backlight pwm pin"
591 depends on VIDEO
592 default ""
593 ---help---
594 Set the backlight pwm pin for the LCD panel. This takes a string in the
595 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200596
Hans de Goede2d5d3022015-01-22 21:02:42 +0100597config VIDEO_LCD_BL_PWM_ACTIVE_LOW
598 bool "LCD panel backlight pwm is inverted"
599 depends on VIDEO
600 default y
601 ---help---
602 Set this if the backlight pwm output is active low.
603
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100604config VIDEO_LCD_PANEL_I2C
605 bool "LCD panel needs to be configured via i2c"
606 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100607 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200608 select CMD_I2C
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100609 ---help---
610 Say y here if the LCD panel needs to be configured via i2c. This
611 will add a bitbang i2c controller using gpios to talk to the LCD.
612
613config VIDEO_LCD_PANEL_I2C_SDA
614 string "LCD panel i2c interface SDA pin"
615 depends on VIDEO_LCD_PANEL_I2C
616 default "PG12"
617 ---help---
618 Set the SDA pin for the LCD i2c interface. This takes a string in the
619 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
620
621config VIDEO_LCD_PANEL_I2C_SCL
622 string "LCD panel i2c interface SCL pin"
623 depends on VIDEO_LCD_PANEL_I2C
624 default "PG10"
625 ---help---
626 Set the SCL pin for the LCD i2c interface. This takes a string in the
627 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
628
Hans de Goede797a0f52015-01-01 22:04:34 +0100629
630# Note only one of these may be selected at a time! But hidden choices are
631# not supported by Kconfig
632config VIDEO_LCD_IF_PARALLEL
633 bool
634
635config VIDEO_LCD_IF_LVDS
636 bool
637
638
639choice
640 prompt "LCD panel support"
641 depends on VIDEO
642 ---help---
643 Select which type of LCD panel to support.
644
645config VIDEO_LCD_PANEL_PARALLEL
646 bool "Generic parallel interface LCD panel"
647 select VIDEO_LCD_IF_PARALLEL
648
649config VIDEO_LCD_PANEL_LVDS
650 bool "Generic lvds interface LCD panel"
651 select VIDEO_LCD_IF_LVDS
652
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200653config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
654 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
655 select VIDEO_LCD_SSD2828
656 select VIDEO_LCD_IF_PARALLEL
657 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200658 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
659
660config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
661 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
662 select VIDEO_LCD_ANX9804
663 select VIDEO_LCD_IF_PARALLEL
664 select VIDEO_LCD_PANEL_I2C
665 ---help---
666 Select this for eDP LCD panels with 4 lanes running at 1.62G,
667 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200668
Hans de Goede743fb9552015-01-20 09:23:36 +0100669config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
670 bool "Hitachi tx18d42vm LCD panel"
671 select VIDEO_LCD_HITACHI_TX18D42VM
672 select VIDEO_LCD_IF_LVDS
673 ---help---
674 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
675
Hans de Goede613dade2015-02-16 17:49:47 +0100676config VIDEO_LCD_TL059WV5C0
677 bool "tl059wv5c0 LCD panel"
678 select VIDEO_LCD_PANEL_I2C
679 select VIDEO_LCD_IF_PARALLEL
680 ---help---
681 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
682 Aigo M60/M608/M606 tablets.
683
Hans de Goede797a0f52015-01-01 22:04:34 +0100684endchoice
685
686
Hans de Goedebf880fe2015-01-25 12:10:48 +0100687config GMAC_TX_DELAY
688 int "GMAC Transmit Clock Delay Chain"
689 default 0
690 ---help---
691 Set the GMAC Transmit Clock Delay Chain value.
692
Hans de Goede66ab79d2015-09-13 13:02:48 +0200693config SPL_STACK_R_ADDR
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200694 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goede66ab79d2015-09-13 13:02:48 +0200695 default 0x2fe00000 if MACH_SUN9I
696
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900697endif