blob: 5cca1eae73b3b2f63c40ad87d7278e460152691b [file] [log] [blame]
Ian Campbelld8e69e02014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Siva Durga Prasad Paladugu809438d2016-07-29 15:31:47 +05303config IDENT_STRING
4 default " Allwinner Technology"
5
Simon Glasse304a5e2016-10-17 20:12:36 -06006config PRE_CONSOLE_BUFFER
7 default y
8
Simon Glass0bdfc3e2016-09-12 23:18:39 -06009config SPL_GPIO_SUPPORT
10 default y
11
Simon Glassf2a89462016-09-12 23:18:41 -060012config SPL_LIBCOMMON_SUPPORT
13 default y
14
Simon Glassf6de2572016-09-12 23:18:42 -060015config SPL_LIBDISK_SUPPORT
16 default y
17
Simon Glassb16c92c2016-09-12 23:18:43 -060018config SPL_LIBGENERIC_SUPPORT
19 default y
20
Simon Glassbd58f1d2016-09-12 23:18:44 -060021config SPL_MMC_SUPPORT
22 default y
23
Simon Glass0d7c7e02016-09-12 23:18:54 -060024config SPL_POWER_SUPPORT
25 default y
26
Simon Glasse076d6f2016-09-12 23:18:56 -060027config SPL_SERIAL_SUPPORT
28 default y
29
Hans de Goedef07872b2015-04-06 20:33:34 +020030# Note only one of these may be selected at a time! But hidden choices are
31# not supported by Kconfig
32config SUNXI_GEN_SUN4I
33 bool
34 ---help---
35 Select this for sunxi SoCs which have resets and clocks set up
36 as the original A10 (mach-sun4i).
37
38config SUNXI_GEN_SUN6I
39 bool
40 ---help---
41 Select this for sunxi SoCs which have sun6i like periphery, like
42 separate ahb reset control registers, custom pmic bus, new style
43 watchdog, etc.
44
45
Ian Campbelld8e69e02014-10-24 21:20:44 +010046choice
47 prompt "Sunxi SoC Variant"
Hans de Goedeb05a6482016-06-12 11:57:07 +020048 optional
Ian Campbelld8e69e02014-10-24 21:20:44 +010049
Ian Campbell4a24a1c2014-10-24 21:20:45 +010050config MACH_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010051 bool "sun4i (Allwinner A10)"
52 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010054 select SUPPORT_SPL
55
Ian Campbell4a24a1c2014-10-24 21:20:45 +010056config MACH_SUN5I
Ian Campbelld8e69e02014-10-24 21:20:44 +010057 bool "sun5i (Allwinner A13)"
58 select CPU_V7
Hans de Goedef07872b2015-04-06 20:33:34 +020059 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010060 select SUPPORT_SPL
61
Ian Campbell4a24a1c2014-10-24 21:20:45 +010062config MACH_SUN6I
Ian Campbelld8e69e02014-10-24 21:20:44 +010063 bool "sun6i (Allwinner A31)"
64 select CPU_V7
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090067 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020068 select SUNXI_GEN_SUN6I
Hans de Goedea5403b92014-10-25 20:18:10 +020069 select SUPPORT_SPL
Chen-Yu Tsaif31017c2015-05-28 21:25:32 +080070 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010071
Ian Campbell4a24a1c2014-10-24 21:20:45 +010072config MACH_SUN7I
Ian Campbelld8e69e02014-10-24 21:20:44 +010073 bool "sun7i (Allwinner A20)"
74 select CPU_V7
Hans de Goede85437352014-11-14 09:34:30 +010075 select CPU_V7_HAS_NONSEC
76 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090077 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020078 select SUNXI_GEN_SUN4I
Ian Campbelld8e69e02014-10-24 21:20:44 +010079 select SUPPORT_SPL
Hans de Goedea5636382014-10-24 20:12:04 +020080 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010081
Hans de Goedef055ed62015-04-06 20:55:39 +020082config MACH_SUN8I_A23
Ian Campbelld8e69e02014-10-24 21:20:44 +010083 bool "sun8i (Allwinner A23)"
84 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080085 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090087 select ARCH_SUPPORT_PSCI
Hans de Goedef07872b2015-04-06 20:33:34 +020088 select SUNXI_GEN_SUN6I
Hans de Goede966d2392014-12-07 14:34:27 +010089 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080090 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbelld8e69e02014-10-24 21:20:44 +010091
Vishnu Patekar3702f142015-03-01 23:47:48 +053092config MACH_SUN8I_A33
93 bool "sun8i (Allwinner A33)"
94 select CPU_V7
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +080095 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +090097 select ARCH_SUPPORT_PSCI
Vishnu Patekar3702f142015-03-01 23:47:48 +053098 select SUNXI_GEN_SUN6I
99 select SUPPORT_SPL
Chen-Yu Tsai5acec7c2015-05-28 21:25:34 +0800100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar3702f142015-03-01 23:47:48 +0530101
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800102config MACH_SUN8I_A83T
103 bool "sun8i (Allwinner A83T)"
104 select CPU_V7
105 select SUNXI_GEN_SUN6I
106 select SUPPORT_SPL
107
Jens Kuskef9770722015-11-17 15:12:58 +0100108config MACH_SUN8I_H3
109 bool "sun8i (Allwinner H3)"
110 select CPU_V7
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800111 select CPU_V7_HAS_NONSEC
112 select CPU_V7_HAS_VIRT
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900113 select ARCH_SUPPORT_PSCI
Jens Kuskef9770722015-11-17 15:12:58 +0100114 select SUNXI_GEN_SUN6I
Jens Kuske53f018e2015-11-17 15:12:59 +0100115 select SUPPORT_SPL
Chen-Yu Tsaiaa9ab0e2016-01-06 15:13:09 +0800116 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuskef9770722015-11-17 15:12:58 +0100117
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100118config MACH_SUN9I
119 bool "sun9i (Allwinner A80)"
120 select CPU_V7
121 select SUNXI_GEN_SUN6I
Philipp Tomsich470626e2016-10-28 18:21:32 +0800122 select SUPPORT_SPL
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100123
Chen-Yu Tsai1fcaea02016-05-02 10:28:07 +0800124config MACH_SUN50I
125 bool "sun50i (Allwinner A64)"
126 select ARM64
127 select SUNXI_GEN_SUN6I
128
Ian Campbelld8e69e02014-10-24 21:20:44 +0100129endchoice
Maxime Ripard2c519412014-10-03 20:16:29 +0800130
Hans de Goedef055ed62015-04-06 20:55:39 +0200131# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
132config MACH_SUN8I
133 bool
vishnupatekarcdf1e482015-11-29 01:07:19 +0800134 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goedef055ed62015-04-06 20:55:39 +0200135
Vishnu Patekarc49936f2016-01-12 01:20:58 +0800136config DRAM_TYPE
137 int "sunxi dram type"
138 depends on MACH_SUN8I_A83T
139 default 3
140 ---help---
141 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goedef055ed62015-04-06 20:55:39 +0200142
Hans de Goede3aeaa282014-11-15 19:46:39 +0100143config DRAM_CLK
Hans de Goede59d9fc72015-01-17 14:24:55 +0100144 int "sunxi dram clock speed"
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800145 default 792 if MACH_SUN9I
Hans de Goede59d9fc72015-01-17 14:24:55 +0100146 default 312 if MACH_SUN6I || MACH_SUN8I
147 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100148 ---help---
Philipp Tomsichd36af1c2016-10-28 18:21:28 +0800149 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
150 must be a multiple of 24. For the sun9i (A80), the tested values
151 (for DDR3-1600) are 312 to 792.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100152
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200153if MACH_SUN5I || MACH_SUN7I
154config DRAM_MBUS_CLK
155 int "sunxi mbus clock speed"
156 default 300
157 ---help---
158 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
159
160endif
161
Hans de Goede3aeaa282014-11-15 19:46:39 +0100162config DRAM_ZQ
Hans de Goede59d9fc72015-01-17 14:24:55 +0100163 int "sunxi dram zq value"
164 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
165 default 127 if MACH_SUN7I
Hans de Goede3aeaa282014-11-15 19:46:39 +0100166 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100167 Set the dram zq value.
Hans de Goede3aeaa282014-11-15 19:46:39 +0100168
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200169config DRAM_ODT_EN
170 bool "sunxi dram odt enable"
171 default n if !MACH_SUN8I_A23
172 default y if MACH_SUN8I_A23
173 ---help---
174 Select this to enable dram odt (on die termination).
175
Hans de Goede59d9fc72015-01-17 14:24:55 +0100176if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
177config DRAM_EMR1
178 int "sunxi dram emr1 value"
179 default 0 if MACH_SUN4I
180 default 4 if MACH_SUN5I || MACH_SUN7I
181 ---help---
Hans de Goede06ddc452015-01-25 11:29:27 +0100182 Set the dram controller emr1 value.
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200183
Siarhei Siamashka47359bb2015-02-01 00:27:06 +0200184config DRAM_TPR3
185 hex "sunxi dram tpr3 value"
186 default 0
187 ---help---
188 Set the dram controller tpr3 parameter. This parameter configures
189 the delay on the command lane and also phase shifts, which are
190 applied for sampling incoming read data. The default value 0
191 means that no phase/delay adjustments are necessary. Properly
192 configuring this parameter increases reliability at high DRAM
193 clock speeds.
194
195config DRAM_DQS_GATING_DELAY
196 hex "sunxi dram dqs_gating_delay value"
197 default 0
198 ---help---
199 Set the dram controller dqs_gating_delay parmeter. Each byte
200 encodes the DQS gating delay for each byte lane. The delay
201 granularity is 1/4 cycle. For example, the value 0x05060606
202 means that the delay is 5 quarter-cycles for one lane (1.25
203 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
204 The default value 0 means autodetection. The results of hardware
205 autodetection are not very reliable and depend on the chip
206 temperature (sometimes producing different results on cold start
207 and warm reboot). But the accuracy of hardware autodetection
208 is usually good enough, unless running at really high DRAM
209 clocks speeds (up to 600MHz). If unsure, keep as 0.
210
Siarhei Siamashka9900db12015-02-01 00:27:05 +0200211choice
212 prompt "sunxi dram timings"
213 default DRAM_TIMINGS_VENDOR_MAGIC
214 ---help---
215 Select the timings of the DDR3 chips.
216
217config DRAM_TIMINGS_VENDOR_MAGIC
218 bool "Magic vendor timings from Android"
219 ---help---
220 The same DRAM timings as in the Allwinner boot0 bootloader.
221
222config DRAM_TIMINGS_DDR3_1066F_1333H
223 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
224 ---help---
225 Use the timings of the standard JEDEC DDR3-1066F speed bin for
226 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
227 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
228 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
229 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
230 that down binning to DDR3-1066F is supported (because DDR3-1066F
231 uses a bit faster timings than DDR3-1333H).
232
233config DRAM_TIMINGS_DDR3_800E_1066G_1333J
234 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
235 ---help---
236 Use the timings of the slowest possible JEDEC speed bin for the
237 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
238 DDR3-800E, DDR3-1066G or DDR3-1333J.
239
240endchoice
241
Hans de Goede3aeaa282014-11-15 19:46:39 +0100242endif
243
Hans de Goedeffdc05c2015-05-13 15:00:46 +0200244if MACH_SUN8I_A23
245config DRAM_ODT_CORRECTION
246 int "sunxi dram odt correction value"
247 default 0
248 ---help---
249 Set the dram odt correction value (range -255 - 255). In allwinner
250 fex files, this option is found in bits 8-15 of the u32 odt_en variable
251 in the [dram] section. When bit 31 of the odt_en variable is set
252 then the correction is negative. Usually the value for this is 0.
253endif
254
Iain Paton630df142015-03-28 10:26:38 +0000255config SYS_CLK_FREQ
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200256 default 816000000 if MACH_SUN50I
Iain Paton630df142015-03-28 10:26:38 +0000257 default 912000000 if MACH_SUN7I
Chen-Yu Tsai40884e62016-10-28 18:21:34 +0800258 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
Iain Paton630df142015-03-28 10:26:38 +0000259
Maxime Ripard2c519412014-10-03 20:16:29 +0800260config SYS_CONFIG_NAME
Ian Campbell4a24a1c2014-10-24 21:20:45 +0100261 default "sun4i" if MACH_SUN4I
262 default "sun5i" if MACH_SUN5I
263 default "sun6i" if MACH_SUN6I
264 default "sun7i" if MACH_SUN7I
265 default "sun8i" if MACH_SUN8I
Hans de Goede7bfe2bb2015-01-13 19:25:06 +0100266 default "sun9i" if MACH_SUN9I
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200267 default "sun50i" if MACH_SUN50I
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900268
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900269config SYS_BOARD
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900270 default "sunxi"
271
272config SYS_SOC
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900273 default "sunxi"
274
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200275config UART0_PORT_F
276 bool "UART0 on MicroSD breakout board"
Siarhei Siamashka121161f2014-12-25 02:34:47 +0200277 default n
278 ---help---
279 Repurpose the SD card slot for getting access to the UART0 serial
280 console. Primarily useful only for low level u-boot debugging on
281 tablets, where normal UART0 is difficult to access and requires
282 device disassembly and/or soldering. As the SD card can't be used
283 at the same time, the system can be only booted in the FEL mode.
284 Only enable this if you really know what you are doing.
285
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200286config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900287 bool "Enable workarounds for booting old kernels"
Hans de Goede05e5bcb2014-10-22 14:56:36 +0200288 default n
289 ---help---
290 Set this to enable various workarounds for old kernels, this results in
291 sub-optimal settings for newer kernels, only enable if needed.
292
Maxime Riparde0c7aa42015-10-15 22:04:07 +0200293config MMC
294 depends on !UART0_PORT_F
295 default y if ARCH_SUNXI
296
Hans de Goede7412ef82014-10-02 20:29:26 +0200297config MMC0_CD_PIN
298 string "Card detect pin for mmc0"
Chen-Yu Tsai36741482016-05-02 10:28:08 +0800299 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goede7412ef82014-10-02 20:29:26 +0200300 default ""
301 ---help---
302 Set the card detect pin for mmc0, leave empty to not use cd. This
303 takes a string in the format understood by sunxi_name_to_gpio, e.g.
304 PH1 for pin 1 of port H.
305
306config MMC1_CD_PIN
307 string "Card detect pin for mmc1"
308 default ""
309 ---help---
310 See MMC0_CD_PIN help text.
311
312config MMC2_CD_PIN
313 string "Card detect pin for mmc2"
314 default ""
315 ---help---
316 See MMC0_CD_PIN help text.
317
318config MMC3_CD_PIN
319 string "Card detect pin for mmc3"
320 default ""
321 ---help---
322 See MMC0_CD_PIN help text.
323
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100324config MMC1_PINS
325 string "Pins for mmc1"
326 default ""
327 ---help---
328 Set the pins used for mmc1, when applicable. This takes a string in the
329 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
330
331config MMC2_PINS
332 string "Pins for mmc2"
333 default ""
334 ---help---
335 See MMC1_PINS help text.
336
337config MMC3_PINS
338 string "Pins for mmc3"
339 default ""
340 ---help---
341 See MMC1_PINS help text.
342
Hans de Goedeaf593e42014-10-02 20:43:50 +0200343config MMC_SUNXI_SLOT_EXTRA
344 int "mmc extra slot number"
345 default -1
346 ---help---
347 sunxi builds always enable mmc0, some boards also have a second sdcard
348 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
349 support for this.
350
Hans de Goede99c9fb02016-04-01 22:39:26 +0200351config INITIAL_USB_SCAN_DELAY
352 int "delay initial usb scan by x ms to allow builtin devices to init"
353 default 0
354 ---help---
355 Some boards have on board usb devices which need longer than the
356 USB spec's 1 second to connect from board powerup. Set this config
357 option to a non 0 value to add an extra delay before the first usb
358 bus scan.
359
Hans de Goedee7b852a2015-01-07 15:26:06 +0100360config USB0_VBUS_PIN
361 string "Vbus enable pin for usb0 (otg)"
362 default ""
363 ---help---
364 Set the Vbus enable pin for usb0 (otg). This takes a string in the
365 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
366
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100367config USB0_VBUS_DET
368 string "Vbus detect pin for usb0 (otg)"
Hans de Goedeeaa0d702015-02-16 22:13:43 +0100369 default ""
370 ---help---
371 Set the Vbus detect pin for usb0 (otg). This takes a string in the
372 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
373
Hans de Goedeaadd97f2015-06-14 17:29:53 +0200374config USB0_ID_DET
375 string "ID detect pin for usb0 (otg)"
376 default ""
377 ---help---
378 Set the ID detect pin for usb0 (otg). This takes a string in the
379 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
380
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100381config USB1_VBUS_PIN
382 string "Vbus enable pin for usb1 (ehci0)"
383 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100384 default "PH27" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100385 ---help---
386 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
387 a string in the format understood by sunxi_name_to_gpio, e.g.
388 PH1 for pin 1 of port H.
389
390config USB2_VBUS_PIN
391 string "Vbus enable pin for usb2 (ehci1)"
392 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goedeb5ab8ce2014-11-07 14:51:12 +0100393 default "PH24" if MACH_SUN6I
Hans de Goedeaf4273b2014-11-07 16:09:00 +0100394 ---help---
395 See USB1_VBUS_PIN help text.
396
Hans de Goedea60c3fc2016-03-18 08:42:01 +0100397config USB3_VBUS_PIN
398 string "Vbus enable pin for usb3 (ehci2)"
399 default ""
400 ---help---
401 See USB1_VBUS_PIN help text.
402
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200403config I2C0_ENABLE
404 bool "Enable I2C/TWI controller 0"
405 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
406 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede2c526402016-05-15 13:51:58 +0200407 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200408 ---help---
409 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
410 its clock and setting up the bus. This is especially useful on devices
411 with slaves connected to the bus or with pins exposed through e.g. an
412 expansion port/header.
413
414config I2C1_ENABLE
415 bool "Enable I2C/TWI controller 1"
416 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200417 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200418 ---help---
419 See I2C0_ENABLE help text.
420
421config I2C2_ENABLE
422 bool "Enable I2C/TWI controller 2"
423 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200424 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200425 ---help---
426 See I2C0_ENABLE help text.
427
428if MACH_SUN6I || MACH_SUN7I
429config I2C3_ENABLE
430 bool "Enable I2C/TWI controller 3"
431 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200432 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200433 ---help---
434 See I2C0_ENABLE help text.
435endif
436
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100437if SUNXI_GEN_SUN6I
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100438config R_I2C_ENABLE
439 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100440 # This is used for the pmic on H3
441 default y if SY8106A_POWER
Hans de Goede2c526402016-05-15 13:51:58 +0200442 select CMD_I2C
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100443 ---help---
444 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100445endif
Jelle van der Waa8d3d7c12016-01-14 14:06:26 +0100446
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200447if MACH_SUN7I
448config I2C4_ENABLE
449 bool "Enable I2C/TWI controller 4"
450 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200451 select CMD_I2C
Paul Kocialkowski0a3ec0a2015-04-10 23:09:52 +0200452 ---help---
453 See I2C0_ENABLE help text.
454endif
455
Hans de Goede3ae1d132015-04-25 17:25:14 +0200456config AXP_GPIO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900457 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede3ae1d132015-04-25 17:25:14 +0200458 default n
459 ---help---
460 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
461
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200462config VIDEO
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900463 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywara8f977272016-09-05 01:32:40 +0100464 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200465 default y
466 ---help---
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100467 Say Y here to add support for using a cfb console on the HDMI, LCD
468 or VGA output found on most sunxi devices. See doc/README.video for
469 info on how to select the video output and mode.
470
Hans de Goedee9544592014-12-23 23:04:35 +0100471config VIDEO_HDMI
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900472 bool "HDMI output support"
Hans de Goedee9544592014-12-23 23:04:35 +0100473 depends on VIDEO && !MACH_SUN8I
474 default y
475 ---help---
476 Say Y here to add support for outputting video over HDMI.
477
Hans de Goede260f5202014-12-25 13:58:06 +0100478config VIDEO_VGA
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900479 bool "VGA output support"
Hans de Goede260f5202014-12-25 13:58:06 +0100480 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
481 default n
482 ---help---
483 Say Y here to add support for outputting video over VGA.
484
Hans de Goedeac1633c2014-12-24 12:17:07 +0100485config VIDEO_VGA_VIA_LCD
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900486 bool "VGA via LCD controller support"
Chen-Yu Tsai39ca4c12015-01-12 18:02:10 +0800487 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedeac1633c2014-12-24 12:17:07 +0100488 default n
489 ---help---
490 Say Y here to add support for external DACs connected to the parallel
491 LCD interface driving a VGA connector, such as found on the
492 Olimex A13 boards.
493
Hans de Goede18366f72015-01-25 15:33:07 +0100494config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900495 bool "Force sync active high for VGA via LCD controller support"
Hans de Goede18366f72015-01-25 15:33:07 +0100496 depends on VIDEO_VGA_VIA_LCD
497 default n
498 ---help---
499 Say Y here if you've a board which uses opendrain drivers for the vga
500 hsync and vsync signals. Opendrain drivers cannot generate steep enough
501 positive edges for a stable video output, so on boards with opendrain
502 drivers the sync signals must always be active high.
503
Chen-Yu Tsai9ed19522015-01-12 18:02:11 +0800504config VIDEO_VGA_EXTERNAL_DAC_EN
505 string "LCD panel power enable pin"
506 depends on VIDEO_VGA_VIA_LCD
507 default ""
508 ---help---
509 Set the enable pin for the external VGA DAC. This takes a string in the
510 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
511
Hans de Goedec06e00e2015-08-03 19:20:26 +0200512config VIDEO_COMPOSITE
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900513 bool "Composite video output support"
Hans de Goedec06e00e2015-08-03 19:20:26 +0200514 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
515 default n
516 ---help---
517 Say Y here to add support for outputting composite video.
518
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100519config VIDEO_LCD_MODE
520 string "LCD panel timing details"
521 depends on VIDEO
522 default ""
523 ---help---
524 LCD panel timing details string, leave empty if there is no LCD panel.
525 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
526 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede924c8932015-08-16 11:23:42 +0200527 Also see: http://linux-sunxi.org/LCD
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100528
Hans de Goede481b6642015-01-13 13:21:46 +0100529config VIDEO_LCD_DCLK_PHASE
530 int "LCD panel display clock phase"
531 depends on VIDEO
532 default 1
533 ---help---
534 Select LCD panel display clock phase shift, range 0-3.
535
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100536config VIDEO_LCD_POWER
537 string "LCD panel power enable pin"
538 depends on VIDEO
539 default ""
540 ---help---
541 Set the power enable pin for the LCD panel. This takes a string in the
542 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
543
Hans de Goedece9e3322015-02-16 17:26:41 +0100544config VIDEO_LCD_RESET
545 string "LCD panel reset pin"
546 depends on VIDEO
547 default ""
548 ---help---
549 Set the reset pin for the LCD panel. This takes a string in the format
550 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
551
Hans de Goede7e68a1b2014-12-21 16:28:32 +0100552config VIDEO_LCD_BL_EN
553 string "LCD panel backlight enable pin"
554 depends on VIDEO
555 default ""
556 ---help---
557 Set the backlight enable pin for the LCD panel. This takes a string in the
558 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
559 port H.
560
561config VIDEO_LCD_BL_PWM
562 string "LCD panel backlight pwm pin"
563 depends on VIDEO
564 default ""
565 ---help---
566 Set the backlight pwm pin for the LCD panel. This takes a string in the
567 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegenb01df1e2014-08-13 07:55:06 +0200568
Hans de Goede2d5d3022015-01-22 21:02:42 +0100569config VIDEO_LCD_BL_PWM_ACTIVE_LOW
570 bool "LCD panel backlight pwm is inverted"
571 depends on VIDEO
572 default y
573 ---help---
574 Set this if the backlight pwm output is active low.
575
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100576config VIDEO_LCD_PANEL_I2C
577 bool "LCD panel needs to be configured via i2c"
578 depends on VIDEO
Hans de Goede6de9f762015-03-07 12:00:02 +0100579 default n
Hans de Goede2c526402016-05-15 13:51:58 +0200580 select CMD_I2C
Hans de Goedea5b4cfe2015-02-16 17:23:25 +0100581 ---help---
582 Say y here if the LCD panel needs to be configured via i2c. This
583 will add a bitbang i2c controller using gpios to talk to the LCD.
584
585config VIDEO_LCD_PANEL_I2C_SDA
586 string "LCD panel i2c interface SDA pin"
587 depends on VIDEO_LCD_PANEL_I2C
588 default "PG12"
589 ---help---
590 Set the SDA pin for the LCD i2c interface. This takes a string in the
591 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
592
593config VIDEO_LCD_PANEL_I2C_SCL
594 string "LCD panel i2c interface SCL pin"
595 depends on VIDEO_LCD_PANEL_I2C
596 default "PG10"
597 ---help---
598 Set the SCL pin for the LCD i2c interface. This takes a string in the
599 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
600
Hans de Goede797a0f52015-01-01 22:04:34 +0100601
602# Note only one of these may be selected at a time! But hidden choices are
603# not supported by Kconfig
604config VIDEO_LCD_IF_PARALLEL
605 bool
606
607config VIDEO_LCD_IF_LVDS
608 bool
609
610
611choice
612 prompt "LCD panel support"
613 depends on VIDEO
614 ---help---
615 Select which type of LCD panel to support.
616
617config VIDEO_LCD_PANEL_PARALLEL
618 bool "Generic parallel interface LCD panel"
619 select VIDEO_LCD_IF_PARALLEL
620
621config VIDEO_LCD_PANEL_LVDS
622 bool "Generic lvds interface LCD panel"
623 select VIDEO_LCD_IF_LVDS
624
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200625config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
626 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
627 select VIDEO_LCD_SSD2828
628 select VIDEO_LCD_IF_PARALLEL
629 ---help---
Hans de Goede91f1b822015-08-08 16:13:53 +0200630 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
631
632config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
633 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
634 select VIDEO_LCD_ANX9804
635 select VIDEO_LCD_IF_PARALLEL
636 select VIDEO_LCD_PANEL_I2C
637 ---help---
638 Select this for eDP LCD panels with 4 lanes running at 1.62G,
639 connected via an ANX9804 bridge chip.
Siarhei Siamashkac02f0522015-01-19 05:23:33 +0200640
Hans de Goede743fb9552015-01-20 09:23:36 +0100641config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
642 bool "Hitachi tx18d42vm LCD panel"
643 select VIDEO_LCD_HITACHI_TX18D42VM
644 select VIDEO_LCD_IF_LVDS
645 ---help---
646 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
647
Hans de Goede613dade2015-02-16 17:49:47 +0100648config VIDEO_LCD_TL059WV5C0
649 bool "tl059wv5c0 LCD panel"
650 select VIDEO_LCD_PANEL_I2C
651 select VIDEO_LCD_IF_PARALLEL
652 ---help---
653 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
654 Aigo M60/M608/M606 tablets.
655
Hans de Goede797a0f52015-01-01 22:04:34 +0100656endchoice
657
658
Hans de Goedebf880fe2015-01-25 12:10:48 +0100659config GMAC_TX_DELAY
660 int "GMAC Transmit Clock Delay Chain"
661 default 0
662 ---help---
663 Set the GMAC Transmit Clock Delay Chain value.
664
Hans de Goede66ab79d2015-09-13 13:02:48 +0200665config SPL_STACK_R_ADDR
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200666 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goede66ab79d2015-09-13 13:02:48 +0200667 default 0x2fe00000 if MACH_SUN9I
668
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900669endif