Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 1 | if ARCH_SUNXI |
| 2 | |
Philipp Tomsich | 2d6a0cc | 2017-08-03 23:23:55 +0200 | [diff] [blame] | 3 | config SPL_LDSCRIPT |
Icenowy Zheng | 8f2d1c0 | 2022-01-29 10:23:07 -0500 | [diff] [blame] | 4 | default "arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds" if MACH_SUNIV |
Philipp Tomsich | 2d6a0cc | 2017-08-03 23:23:55 +0200 | [diff] [blame] | 5 | default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 |
| 6 | |
Siva Durga Prasad Paladugu | 809438d | 2016-07-29 15:31:47 +0530 | [diff] [blame] | 7 | config IDENT_STRING |
| 8 | default " Allwinner Technology" |
| 9 | |
Jagan Teki | 3994b1e | 2018-01-10 16:03:34 +0530 | [diff] [blame] | 10 | config DRAM_SUN4I |
| 11 | bool |
| 12 | help |
| 13 | Select this dram controller driver for Sun4/5/7i platforms, |
| 14 | like A10/A13/A20. |
| 15 | |
Jagan Teki | 68d0f5f | 2018-03-17 00:16:36 +0530 | [diff] [blame] | 16 | config DRAM_SUN6I |
| 17 | bool |
| 18 | help |
| 19 | Select this dram controller driver for Sun6i platforms, |
| 20 | like A31/A31s. |
| 21 | |
Jagan Teki | 318e4e5 | 2018-01-10 16:15:14 +0530 | [diff] [blame] | 22 | config DRAM_SUN8I_A23 |
| 23 | bool |
| 24 | help |
| 25 | Select this dram controller driver for Sun8i platforms, |
| 26 | for A23 SOC. |
| 27 | |
Jagan Teki | e624d4c | 2018-01-10 16:17:39 +0530 | [diff] [blame] | 28 | config DRAM_SUN8I_A33 |
| 29 | bool |
| 30 | help |
| 31 | Select this dram controller driver for Sun8i platforms, |
| 32 | for A33 SOC. |
| 33 | |
Jagan Teki | 270a6f6 | 2018-01-10 16:20:26 +0530 | [diff] [blame] | 34 | config DRAM_SUN8I_A83T |
| 35 | bool |
| 36 | help |
| 37 | Select this dram controller driver for Sun8i platforms, |
| 38 | for A83T SOC. |
| 39 | |
Jagan Teki | 6aa7f71 | 2018-03-17 00:18:01 +0530 | [diff] [blame] | 40 | config DRAM_SUN9I |
| 41 | bool |
| 42 | help |
| 43 | Select this dram controller driver for Sun9i platforms, |
| 44 | like A80. |
| 45 | |
Icenowy Zheng | 4e287f6 | 2018-07-23 06:13:34 +0800 | [diff] [blame] | 46 | config DRAM_SUN50I_H6 |
| 47 | bool |
| 48 | help |
| 49 | Select this dram controller driver for some sun50i platforms, |
| 50 | like H6. |
| 51 | |
Jernej Skrabec | e4aa24b | 2021-01-11 21:11:43 +0100 | [diff] [blame] | 52 | config DRAM_SUN50I_H616 |
| 53 | bool |
| 54 | help |
| 55 | Select this dram controller driver for some sun50i platforms, |
| 56 | like H616. |
| 57 | |
| 58 | if DRAM_SUN50I_H616 |
| 59 | config DRAM_SUN50I_H616_WRITE_LEVELING |
| 60 | bool "H616 DRAM write leveling" |
| 61 | ---help--- |
| 62 | Select this when DRAM on your H616 board needs write leveling. |
| 63 | |
| 64 | config DRAM_SUN50I_H616_READ_CALIBRATION |
| 65 | bool "H616 DRAM read calibration" |
| 66 | ---help--- |
| 67 | Select this when DRAM on your H616 board needs read calibration. |
| 68 | |
| 69 | config DRAM_SUN50I_H616_READ_TRAINING |
| 70 | bool "H616 DRAM read training" |
| 71 | ---help--- |
| 72 | Select this when DRAM on your H616 board needs read training. |
| 73 | |
| 74 | config DRAM_SUN50I_H616_WRITE_TRAINING |
| 75 | bool "H616 DRAM write training" |
| 76 | ---help--- |
| 77 | Select this when DRAM on your H616 board needs write training. |
| 78 | |
| 79 | config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION |
| 80 | bool "H616 DRAM bit delay compensation" |
| 81 | ---help--- |
| 82 | Select this when DRAM on your H616 board needs bit delay |
| 83 | compensation. |
| 84 | |
| 85 | config DRAM_SUN50I_H616_UNKNOWN_FEATURE |
| 86 | bool "H616 DRAM unknown feature" |
| 87 | ---help--- |
| 88 | Select this when DRAM on your H616 board needs this unknown |
| 89 | feature. |
| 90 | endif |
| 91 | |
Jagan Teki | 932f5e0 | 2018-01-11 13:21:15 +0530 | [diff] [blame] | 92 | config SUN6I_PRCM |
| 93 | bool |
| 94 | help |
| 95 | Support for the PRCM (Power/Reset/Clock Management) unit available |
| 96 | in A31 SoC. |
| 97 | |
Jagan Teki | feb2927 | 2018-02-14 22:28:30 +0530 | [diff] [blame] | 98 | config AXP_PMIC_BUS |
Samuel Holland | 623b804 | 2021-10-08 00:17:19 -0500 | [diff] [blame] | 99 | bool |
Samuel Holland | 388fe64 | 2021-10-08 00:17:23 -0500 | [diff] [blame] | 100 | select DM_PMIC if DM_I2C |
| 101 | select PMIC_AXP if DM_I2C |
Jagan Teki | feb2927 | 2018-02-14 22:28:30 +0530 | [diff] [blame] | 102 | help |
| 103 | Select this PMIC bus access helpers for Sunxi platform PRCM or other |
| 104 | AXP family PMIC devices. |
| 105 | |
Icenowy Zheng | 5e6dd27 | 2018-07-21 16:20:20 +0800 | [diff] [blame] | 106 | config SUNXI_SRAM_ADDRESS |
| 107 | hex |
| 108 | default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 |
Jernej Skrabec | da8ae61 | 2021-01-11 21:11:34 +0100 | [diff] [blame] | 109 | default 0x20000 if SUN50I_GEN_H6 |
Icenowy Zheng | 5e6dd27 | 2018-07-21 16:20:20 +0800 | [diff] [blame] | 110 | default 0x0 |
Andre Przywara | de454ec | 2017-02-16 01:20:23 +0000 | [diff] [blame] | 111 | ---help--- |
| 112 | Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, |
| 113 | with the first SRAM region being located at address 0. |
| 114 | Some newer SoCs map the boot ROM at address 0 instead and move the |
Icenowy Zheng | 5e6dd27 | 2018-07-21 16:20:20 +0800 | [diff] [blame] | 115 | SRAM to a different address. |
Andre Przywara | de454ec | 2017-02-16 01:20:23 +0000 | [diff] [blame] | 116 | |
Andre Przywara | d1de0bb | 2018-06-27 01:42:53 +0100 | [diff] [blame] | 117 | config SUNXI_A64_TIMER_ERRATUM |
| 118 | bool |
| 119 | |
Hans de Goede | f07872b | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 120 | # Note only one of these may be selected at a time! But hidden choices are |
| 121 | # not supported by Kconfig |
| 122 | config SUNXI_GEN_SUN4I |
| 123 | bool |
| 124 | ---help--- |
| 125 | Select this for sunxi SoCs which have resets and clocks set up |
| 126 | as the original A10 (mach-sun4i). |
| 127 | |
| 128 | config SUNXI_GEN_SUN6I |
| 129 | bool |
| 130 | ---help--- |
| 131 | Select this for sunxi SoCs which have sun6i like periphery, like |
| 132 | separate ahb reset control registers, custom pmic bus, new style |
| 133 | watchdog, etc. |
| 134 | |
Jernej Skrabec | da8ae61 | 2021-01-11 21:11:34 +0100 | [diff] [blame] | 135 | config SUN50I_GEN_H6 |
| 136 | bool |
| 137 | select FIT |
| 138 | select SPL_LOAD_FIT |
Andre Przywara | b8816f0 | 2021-05-05 10:04:41 +0100 | [diff] [blame] | 139 | select MMC_SUNXI_HAS_NEW_MODE |
Jernej Skrabec | da8ae61 | 2021-01-11 21:11:34 +0100 | [diff] [blame] | 140 | select SUPPORT_SPL |
| 141 | ---help--- |
| 142 | Select this for sunxi SoCs which have H6 like peripherals, clocks |
| 143 | and memory map. |
| 144 | |
Icenowy Zheng | ca0bc02 | 2017-06-03 17:10:14 +0800 | [diff] [blame] | 145 | config SUNXI_DRAM_DW |
| 146 | bool |
| 147 | ---help--- |
| 148 | Select this for sunxi SoCs which uses a DRAM controller like the |
| 149 | DesignWare controller used in H3, mainly SoCs after H3, which do |
| 150 | not have official open-source DRAM initialization code, but can |
| 151 | use modified H3 DRAM initialization code. |
Hans de Goede | f07872b | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 152 | |
Icenowy Zheng | b260751 | 2017-06-03 17:10:16 +0800 | [diff] [blame] | 153 | if SUNXI_DRAM_DW |
| 154 | config SUNXI_DRAM_DW_16BIT |
| 155 | bool |
| 156 | ---help--- |
| 157 | Select this for sunxi SoCs with DesignWare DRAM controller and |
| 158 | have only 16-bit memory buswidth. |
| 159 | |
| 160 | config SUNXI_DRAM_DW_32BIT |
| 161 | bool |
| 162 | ---help--- |
| 163 | Select this for sunxi SoCs with DesignWare DRAM controller with |
| 164 | 32-bit memory buswidth. |
| 165 | endif |
| 166 | |
Andre Przywara | 5fb9743 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 167 | config MACH_SUNXI_H3_H5 |
| 168 | bool |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 169 | select PHY_SUN4I_USB |
Jernej Skrabec | 9b4ca92 | 2017-03-27 19:22:31 +0200 | [diff] [blame] | 170 | select SUNXI_DE2 |
Icenowy Zheng | ca0bc02 | 2017-06-03 17:10:14 +0800 | [diff] [blame] | 171 | select SUNXI_DRAM_DW |
Icenowy Zheng | b260751 | 2017-06-03 17:10:16 +0800 | [diff] [blame] | 172 | select SUNXI_DRAM_DW_32BIT |
Andre Przywara | 5fb9743 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 173 | select SUNXI_GEN_SUN6I |
| 174 | select SUPPORT_SPL |
| 175 | |
Icenowy Zheng | 14170a4 | 2018-10-25 17:23:06 +0800 | [diff] [blame] | 176 | # TODO: try out A80's 8GiB DRAM space |
| 177 | config SUNXI_DRAM_MAX_SIZE |
| 178 | hex |
Andre Przywara | c0387f1 | 2021-04-28 21:29:55 +0100 | [diff] [blame] | 179 | default 0x100000000 if MACH_SUN50I_H616 |
| 180 | default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 |
Icenowy Zheng | 14170a4 | 2018-10-25 17:23:06 +0800 | [diff] [blame] | 181 | default 0x80000000 |
| 182 | |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 183 | choice |
| 184 | prompt "Sunxi SoC Variant" |
Hans de Goede | b05a648 | 2016-06-12 11:57:07 +0200 | [diff] [blame] | 185 | optional |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 186 | |
Icenowy Zheng | 8f2d1c0 | 2022-01-29 10:23:07 -0500 | [diff] [blame] | 187 | config MACH_SUNIV |
| 188 | bool "suniv (Allwinner F1C100s/F1C200s/F1C600/R6)" |
| 189 | select CPU_ARM926EJS |
| 190 | select SUNXI_GEN_SUN6I |
| 191 | select SUPPORT_SPL |
| 192 | |
Ian Campbell | 4a24a1c | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 193 | config MACH_SUN4I |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 194 | bool "sun4i (Allwinner A10)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 195 | select CPU_V7A |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 196 | select PHY_SUN4I_USB |
Jagan Teki | 3994b1e | 2018-01-10 16:03:34 +0530 | [diff] [blame] | 197 | select DRAM_SUN4I |
Hans de Goede | f07872b | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 198 | select SUNXI_GEN_SUN4I |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 199 | select SUPPORT_SPL |
Tom Rini | 52b2e26 | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 200 | imply SPL_SYS_I2C_LEGACY |
| 201 | imply SYS_I2C_LEGACY |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 202 | |
Ian Campbell | 4a24a1c | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 203 | config MACH_SUN5I |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 204 | bool "sun5i (Allwinner A13)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 205 | select CPU_V7A |
Jagan Teki | 3994b1e | 2018-01-10 16:03:34 +0530 | [diff] [blame] | 206 | select DRAM_SUN4I |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 207 | select PHY_SUN4I_USB |
Hans de Goede | f07872b | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 208 | select SUNXI_GEN_SUN4I |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 209 | select SUPPORT_SPL |
Tom Rini | e69ba98 | 2018-03-06 19:02:27 -0500 | [diff] [blame] | 210 | imply CONS_INDEX_2 if !DM_SERIAL |
Tom Rini | 52b2e26 | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 211 | imply SPL_SYS_I2C_LEGACY |
| 212 | imply SYS_I2C_LEGACY |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 213 | |
Ian Campbell | 4a24a1c | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 214 | config MACH_SUN6I |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 215 | bool "sun6i (Allwinner A31)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 216 | select CPU_V7A |
Chen-Yu Tsai | f31017c | 2015-05-28 21:25:32 +0800 | [diff] [blame] | 217 | select CPU_V7_HAS_NONSEC |
| 218 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | d5415b2 | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 219 | select ARCH_SUPPORT_PSCI |
Andre Przywara | 5fc2556 | 2022-01-23 00:27:19 +0000 | [diff] [blame] | 220 | select SPL_ARMV7_SET_CORTEX_SMPEN |
Jagan Teki | 68d0f5f | 2018-03-17 00:16:36 +0530 | [diff] [blame] | 221 | select DRAM_SUN6I |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 222 | select PHY_SUN4I_USB |
Samuel Holland | 60d4928 | 2021-10-08 00:17:20 -0500 | [diff] [blame] | 223 | select SPL_I2C |
Jagan Teki | 932f5e0 | 2018-01-11 13:21:15 +0530 | [diff] [blame] | 224 | select SUN6I_PRCM |
Hans de Goede | f07872b | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 225 | select SUNXI_GEN_SUN6I |
Hans de Goede | a5403b9 | 2014-10-25 20:18:10 +0200 | [diff] [blame] | 226 | select SUPPORT_SPL |
Samuel Holland | 60d4928 | 2021-10-08 00:17:20 -0500 | [diff] [blame] | 227 | select SYS_I2C_SUN6I_P2WI |
Chen-Yu Tsai | f31017c | 2015-05-28 21:25:32 +0800 | [diff] [blame] | 228 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 229 | |
Ian Campbell | 4a24a1c | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 230 | config MACH_SUN7I |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 231 | bool "sun7i (Allwinner A20)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 232 | select CPU_V7A |
Hans de Goede | 8543735 | 2014-11-14 09:34:30 +0100 | [diff] [blame] | 233 | select CPU_V7_HAS_NONSEC |
| 234 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | d5415b2 | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 235 | select ARCH_SUPPORT_PSCI |
Andre Przywara | 5fc2556 | 2022-01-23 00:27:19 +0000 | [diff] [blame] | 236 | select SPL_ARMV7_SET_CORTEX_SMPEN |
Jagan Teki | 3994b1e | 2018-01-10 16:03:34 +0530 | [diff] [blame] | 237 | select DRAM_SUN4I |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 238 | select PHY_SUN4I_USB |
Hans de Goede | f07872b | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 239 | select SUNXI_GEN_SUN4I |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 240 | select SUPPORT_SPL |
Hans de Goede | a563638 | 2014-10-24 20:12:04 +0200 | [diff] [blame] | 241 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Tom Rini | 52b2e26 | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 242 | imply SPL_SYS_I2C_LEGACY |
| 243 | imply SYS_I2C_LEGACY |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 244 | |
Hans de Goede | f055ed6 | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 245 | config MACH_SUN8I_A23 |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 246 | bool "sun8i (Allwinner A23)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 247 | select CPU_V7A |
Chen-Yu Tsai | 5acec7c | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 248 | select CPU_V7_HAS_NONSEC |
| 249 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | d5415b2 | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 250 | select ARCH_SUPPORT_PSCI |
Jagan Teki | 318e4e5 | 2018-01-10 16:15:14 +0530 | [diff] [blame] | 251 | select DRAM_SUN8I_A23 |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 252 | select PHY_SUN4I_USB |
Samuel Holland | b348efb | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 253 | select SPL_I2C |
Hans de Goede | f07872b | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 254 | select SUNXI_GEN_SUN6I |
Hans de Goede | 966d239 | 2014-12-07 14:34:27 +0100 | [diff] [blame] | 255 | select SUPPORT_SPL |
Samuel Holland | b348efb | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 256 | select SYS_I2C_SUN8I_RSB |
Chen-Yu Tsai | 5acec7c | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 257 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Tom Rini | e69ba98 | 2018-03-06 19:02:27 -0500 | [diff] [blame] | 258 | imply CONS_INDEX_5 if !DM_SERIAL |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 259 | |
Vishnu Patekar | 3702f14 | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 260 | config MACH_SUN8I_A33 |
| 261 | bool "sun8i (Allwinner A33)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 262 | select CPU_V7A |
Chen-Yu Tsai | 5acec7c | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 263 | select CPU_V7_HAS_NONSEC |
| 264 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | d5415b2 | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 265 | select ARCH_SUPPORT_PSCI |
Jagan Teki | e624d4c | 2018-01-10 16:17:39 +0530 | [diff] [blame] | 266 | select DRAM_SUN8I_A33 |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 267 | select PHY_SUN4I_USB |
Samuel Holland | b348efb | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 268 | select SPL_I2C |
Vishnu Patekar | 3702f14 | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 269 | select SUNXI_GEN_SUN6I |
| 270 | select SUPPORT_SPL |
Samuel Holland | b348efb | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 271 | select SYS_I2C_SUN8I_RSB |
Chen-Yu Tsai | 5acec7c | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 272 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Tom Rini | e69ba98 | 2018-03-06 19:02:27 -0500 | [diff] [blame] | 273 | imply CONS_INDEX_5 if !DM_SERIAL |
Vishnu Patekar | 3702f14 | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 274 | |
Chen-Yu Tsai | 1fcaea0 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 275 | config MACH_SUN8I_A83T |
| 276 | bool "sun8i (Allwinner A83T)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 277 | select CPU_V7A |
Jagan Teki | 270a6f6 | 2018-01-10 16:20:26 +0530 | [diff] [blame] | 278 | select DRAM_SUN8I_A83T |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 279 | select PHY_SUN4I_USB |
Samuel Holland | b348efb | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 280 | select SPL_I2C |
Chen-Yu Tsai | 1fcaea0 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 281 | select SUNXI_GEN_SUN6I |
Maxime Ripard | 4799a1a | 2017-08-23 12:03:42 +0200 | [diff] [blame] | 282 | select MMC_SUNXI_HAS_NEW_MODE |
Vasily Khoruzhick | b198e2c | 2018-11-09 20:41:44 -0800 | [diff] [blame] | 283 | select MMC_SUNXI_HAS_MODE_SWITCH |
Chen-Yu Tsai | 1fcaea0 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 284 | select SUPPORT_SPL |
Samuel Holland | b348efb | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 285 | select SYS_I2C_SUN8I_RSB |
Chen-Yu Tsai | 1fcaea0 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 286 | |
Jens Kuske | f977072 | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 287 | config MACH_SUN8I_H3 |
| 288 | bool "sun8i (Allwinner H3)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 289 | select CPU_V7A |
Chen-Yu Tsai | aa9ab0e | 2016-01-06 15:13:09 +0800 | [diff] [blame] | 290 | select CPU_V7_HAS_NONSEC |
| 291 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | d5415b2 | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 292 | select ARCH_SUPPORT_PSCI |
Andre Przywara | 5fb9743 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 293 | select MACH_SUNXI_H3_H5 |
Chen-Yu Tsai | aa9ab0e | 2016-01-06 15:13:09 +0800 | [diff] [blame] | 294 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Jens Kuske | f977072 | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 295 | |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 296 | config MACH_SUN8I_R40 |
| 297 | bool "sun8i (Allwinner R40)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 298 | select CPU_V7A |
Chen-Yu Tsai | b1a1fda | 2017-03-01 11:03:15 +0800 | [diff] [blame] | 299 | select CPU_V7_HAS_NONSEC |
| 300 | select CPU_V7_HAS_VIRT |
| 301 | select ARCH_SUPPORT_PSCI |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 302 | select SUNXI_GEN_SUN6I |
Andre Przywara | b8816f0 | 2021-05-05 10:04:41 +0100 | [diff] [blame] | 303 | select MMC_SUNXI_HAS_NEW_MODE |
Chen-Yu Tsai | 2d5826c | 2016-12-02 16:09:49 +0800 | [diff] [blame] | 304 | select SUPPORT_SPL |
Icenowy Zheng | ca0bc02 | 2017-06-03 17:10:14 +0800 | [diff] [blame] | 305 | select SUNXI_DRAM_DW |
Icenowy Zheng | b260751 | 2017-06-03 17:10:16 +0800 | [diff] [blame] | 306 | select SUNXI_DRAM_DW_32BIT |
Andre Przywara | 47d4997 | 2020-01-01 23:44:48 +0000 | [diff] [blame] | 307 | select PHY_SUN4I_USB |
Tom Rini | 52b2e26 | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 308 | imply SPL_SYS_I2C_LEGACY |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 309 | |
Icenowy Zheng | 52e6188 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 310 | config MACH_SUN8I_V3S |
Icenowy Zheng | 7df9910 | 2020-10-26 22:15:59 +0800 | [diff] [blame] | 311 | bool "sun8i (Allwinner V3/V3s/S3/S3L)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 312 | select CPU_V7A |
Icenowy Zheng | 52e6188 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 313 | select CPU_V7_HAS_NONSEC |
| 314 | select CPU_V7_HAS_VIRT |
| 315 | select ARCH_SUPPORT_PSCI |
| 316 | select SUNXI_GEN_SUN6I |
Icenowy Zheng | b54209f | 2017-06-03 17:10:22 +0800 | [diff] [blame] | 317 | select SUNXI_DRAM_DW |
| 318 | select SUNXI_DRAM_DW_16BIT |
| 319 | select SUPPORT_SPL |
Icenowy Zheng | 52e6188 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 320 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
| 321 | |
Hans de Goede | 7bfe2bb | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 322 | config MACH_SUN9I |
| 323 | bool "sun9i (Allwinner A80)" |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 324 | select CPU_V7A |
Andre Przywara | 5fc2556 | 2022-01-23 00:27:19 +0000 | [diff] [blame] | 325 | select SPL_ARMV7_SET_CORTEX_SMPEN |
Jagan Teki | 6aa7f71 | 2018-03-17 00:18:01 +0530 | [diff] [blame] | 326 | select DRAM_SUN9I |
Samuel Holland | b348efb | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 327 | select SPL_I2C |
Jagan Teki | 11f33e1 | 2018-01-11 13:23:02 +0530 | [diff] [blame] | 328 | select SUN6I_PRCM |
Hans de Goede | 7bfe2bb | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 329 | select SUNXI_GEN_SUN6I |
Philipp Tomsich | 470626e | 2016-10-28 18:21:32 +0800 | [diff] [blame] | 330 | select SUPPORT_SPL |
Hans de Goede | 7bfe2bb | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 331 | |
Chen-Yu Tsai | 1fcaea0 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 332 | config MACH_SUN50I |
| 333 | bool "sun50i (Allwinner A64)" |
| 334 | select ARM64 |
Jagan Teki | 137fc75 | 2018-05-07 13:03:38 +0530 | [diff] [blame] | 335 | select PHY_SUN4I_USB |
Vasily Khoruzhick | 6f4c344 | 2018-11-05 20:24:30 -0800 | [diff] [blame] | 336 | select SUN6I_PRCM |
Jernej Skrabec | 9b4ca92 | 2017-03-27 19:22:31 +0200 | [diff] [blame] | 337 | select SUNXI_DE2 |
Chen-Yu Tsai | 1fcaea0 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 338 | select SUNXI_GEN_SUN6I |
Vasily Khoruzhick | a4e8dd9 | 2018-11-09 20:41:46 -0800 | [diff] [blame] | 339 | select MMC_SUNXI_HAS_NEW_MODE |
Andre Przywara | a563adc | 2017-01-02 11:48:45 +0000 | [diff] [blame] | 340 | select SUPPORT_SPL |
Icenowy Zheng | ca0bc02 | 2017-06-03 17:10:14 +0800 | [diff] [blame] | 341 | select SUNXI_DRAM_DW |
Icenowy Zheng | b260751 | 2017-06-03 17:10:16 +0800 | [diff] [blame] | 342 | select SUNXI_DRAM_DW_32BIT |
Andre Przywara | d836216 | 2017-04-26 01:32:48 +0100 | [diff] [blame] | 343 | select FIT |
| 344 | select SPL_LOAD_FIT |
Andre Przywara | d1de0bb | 2018-06-27 01:42:53 +0100 | [diff] [blame] | 345 | select SUNXI_A64_TIMER_ERRATUM |
Chen-Yu Tsai | 1fcaea0 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 346 | |
Andre Przywara | 5611a2d | 2017-02-16 01:20:28 +0000 | [diff] [blame] | 347 | config MACH_SUN50I_H5 |
| 348 | bool "sun50i (Allwinner H5)" |
| 349 | select ARM64 |
| 350 | select MACH_SUNXI_H3_H5 |
Andre Przywara | b8816f0 | 2021-05-05 10:04:41 +0100 | [diff] [blame] | 351 | select MMC_SUNXI_HAS_NEW_MODE |
Andre Przywara | d836216 | 2017-04-26 01:32:48 +0100 | [diff] [blame] | 352 | select FIT |
| 353 | select SPL_LOAD_FIT |
Andre Przywara | 5611a2d | 2017-02-16 01:20:28 +0000 | [diff] [blame] | 354 | |
Icenowy Zheng | 0c01b96 | 2018-07-21 16:20:31 +0800 | [diff] [blame] | 355 | config MACH_SUN50I_H6 |
| 356 | bool "sun50i (Allwinner H6)" |
| 357 | select ARM64 |
Andre Przywara | 213c297 | 2019-06-23 15:09:50 +0100 | [diff] [blame] | 358 | select PHY_SUN4I_USB |
Icenowy Zheng | 0c01b96 | 2018-07-21 16:20:31 +0800 | [diff] [blame] | 359 | select DRAM_SUN50I_H6 |
Jernej Skrabec | da8ae61 | 2021-01-11 21:11:34 +0100 | [diff] [blame] | 360 | select SUN50I_GEN_H6 |
Icenowy Zheng | 0c01b96 | 2018-07-21 16:20:31 +0800 | [diff] [blame] | 361 | |
Jernej Skrabec | e638e05 | 2021-01-11 21:11:46 +0100 | [diff] [blame] | 362 | config MACH_SUN50I_H616 |
| 363 | bool "sun50i (Allwinner H616)" |
| 364 | select ARM64 |
| 365 | select DRAM_SUN50I_H616 |
| 366 | select SUN50I_GEN_H6 |
| 367 | |
Ian Campbell | d8e69e0 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 368 | endchoice |
Maxime Ripard | 2c51941 | 2014-10-03 20:16:29 +0800 | [diff] [blame] | 369 | |
Hans de Goede | f055ed6 | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 370 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
| 371 | config MACH_SUN8I |
| 372 | bool |
Andre Przywara | 5fc2556 | 2022-01-23 00:27:19 +0000 | [diff] [blame] | 373 | select SPL_ARMV7_SET_CORTEX_SMPEN if !ARM64 |
Jagan Teki | 11f33e1 | 2018-01-11 13:23:02 +0530 | [diff] [blame] | 374 | select SUN6I_PRCM |
Chen-Yu Tsai | fa33746 | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 375 | default y if MACH_SUN8I_A23 |
| 376 | default y if MACH_SUN8I_A33 |
| 377 | default y if MACH_SUN8I_A83T |
| 378 | default y if MACH_SUNXI_H3_H5 |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 379 | default y if MACH_SUN8I_R40 |
Icenowy Zheng | 52e6188 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 380 | default y if MACH_SUN8I_V3S |
Hans de Goede | f055ed6 | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 381 | |
Andre Przywara | 06893b6 | 2017-01-02 11:48:35 +0000 | [diff] [blame] | 382 | config RESERVE_ALLWINNER_BOOT0_HEADER |
| 383 | bool "reserve space for Allwinner boot0 header" |
| 384 | select ENABLE_ARM_SOC_BOOT0_HOOK |
| 385 | ---help--- |
| 386 | Prepend a 1536 byte (empty) header to the U-Boot image file, to be |
| 387 | filled with magic values post build. The Allwinner provided boot0 |
| 388 | blob relies on this information to load and execute U-Boot. |
| 389 | Only needed on 64-bit Allwinner boards so far when using boot0. |
| 390 | |
Andre Przywara | 46c3d99 | 2017-01-02 11:48:36 +0000 | [diff] [blame] | 391 | config ARM_BOOT_HOOK_RMR |
| 392 | bool |
| 393 | depends on ARM64 |
| 394 | default y |
| 395 | select ENABLE_ARM_SOC_BOOT0_HOOK |
| 396 | ---help--- |
| 397 | Insert some ARM32 code at the very beginning of the U-Boot binary |
| 398 | which uses an RMR register write to bring the core into AArch64 mode. |
| 399 | The very first instruction acts as a switch, since it's carefully |
| 400 | chosen to be a NOP in one mode and a branch in the other, so the |
| 401 | code would only be executed if not already in AArch64. |
| 402 | This allows both the SPL and the U-Boot proper to be entered in |
| 403 | either mode and switch to AArch64 if needed. |
| 404 | |
Andre Przywara | 1c7a751 | 2019-07-15 02:27:06 +0100 | [diff] [blame] | 405 | if SUNXI_DRAM_DW || DRAM_SUN50I_H6 |
Icenowy Zheng | f09b48e | 2017-06-03 17:10:18 +0800 | [diff] [blame] | 406 | config SUNXI_DRAM_DDR3 |
| 407 | bool |
| 408 | |
Icenowy Zheng | e270a58 | 2017-06-03 17:10:20 +0800 | [diff] [blame] | 409 | config SUNXI_DRAM_DDR2 |
| 410 | bool |
| 411 | |
Icenowy Zheng | 3c1b9f1 | 2017-06-03 17:10:23 +0800 | [diff] [blame] | 412 | config SUNXI_DRAM_LPDDR3 |
| 413 | bool |
| 414 | |
Icenowy Zheng | f09b48e | 2017-06-03 17:10:18 +0800 | [diff] [blame] | 415 | choice |
| 416 | prompt "DRAM Type and Timing" |
Icenowy Zheng | fe05217 | 2017-06-03 17:10:21 +0800 | [diff] [blame] | 417 | default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S |
| 418 | default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S |
Icenowy Zheng | f09b48e | 2017-06-03 17:10:18 +0800 | [diff] [blame] | 419 | |
| 420 | config SUNXI_DRAM_DDR3_1333 |
| 421 | bool "DDR3 1333" |
| 422 | select SUNXI_DRAM_DDR3 |
| 423 | ---help--- |
| 424 | This option is the original only supported memory type, which suits |
| 425 | many H3/H5/A64 boards available now. |
| 426 | |
Icenowy Zheng | eb4766e | 2017-06-03 17:10:24 +0800 | [diff] [blame] | 427 | config SUNXI_DRAM_LPDDR3_STOCK |
| 428 | bool "LPDDR3 with Allwinner stock configuration" |
| 429 | select SUNXI_DRAM_LPDDR3 |
| 430 | ---help--- |
| 431 | This option is the LPDDR3 timing used by the stock boot0 by |
| 432 | Allwinner. |
| 433 | |
Andre Przywara | 1c7a751 | 2019-07-15 02:27:06 +0100 | [diff] [blame] | 434 | config SUNXI_DRAM_H6_LPDDR3 |
| 435 | bool "LPDDR3 DRAM chips on the H6 DRAM controller" |
| 436 | select SUNXI_DRAM_LPDDR3 |
| 437 | depends on DRAM_SUN50I_H6 |
| 438 | ---help--- |
| 439 | This option is the LPDDR3 timing used by the stock boot0 by |
| 440 | Allwinner. |
| 441 | |
Andre Przywara | 75d38d0 | 2019-07-15 02:27:08 +0100 | [diff] [blame] | 442 | config SUNXI_DRAM_H6_DDR3_1333 |
| 443 | bool "DDR3-1333 boot0 timings on the H6 DRAM controller" |
| 444 | select SUNXI_DRAM_DDR3 |
| 445 | depends on DRAM_SUN50I_H6 |
| 446 | ---help--- |
| 447 | This option is the DDR3 timing used by the boot0 on H6 TV boxes |
| 448 | which use a DDR3-1333 timing. |
| 449 | |
Icenowy Zheng | e270a58 | 2017-06-03 17:10:20 +0800 | [diff] [blame] | 450 | config SUNXI_DRAM_DDR2_V3S |
| 451 | bool "DDR2 found in V3s chip" |
| 452 | select SUNXI_DRAM_DDR2 |
Icenowy Zheng | fe05217 | 2017-06-03 17:10:21 +0800 | [diff] [blame] | 453 | depends on MACH_SUN8I_V3S |
Icenowy Zheng | e270a58 | 2017-06-03 17:10:20 +0800 | [diff] [blame] | 454 | ---help--- |
| 455 | This option is only for the DDR2 memory chip which is co-packaged in |
| 456 | Allwinner V3s SoC. |
| 457 | |
Icenowy Zheng | f09b48e | 2017-06-03 17:10:18 +0800 | [diff] [blame] | 458 | endchoice |
| 459 | endif |
| 460 | |
Vishnu Patekar | c49936f | 2016-01-12 01:20:58 +0800 | [diff] [blame] | 461 | config DRAM_TYPE |
| 462 | int "sunxi dram type" |
| 463 | depends on MACH_SUN8I_A83T |
| 464 | default 3 |
| 465 | ---help--- |
| 466 | Set the dram type, 3: DDR3, 7: LPDDR3 |
Hans de Goede | f055ed6 | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 467 | |
Hans de Goede | 3aeaa28 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 468 | config DRAM_CLK |
Hans de Goede | 59d9fc7 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 469 | int "sunxi dram clock speed" |
Philipp Tomsich | d36af1c | 2016-10-28 18:21:28 +0800 | [diff] [blame] | 470 | default 792 if MACH_SUN9I |
Chen-Yu Tsai | f361d56 | 2016-11-30 16:58:35 +0800 | [diff] [blame] | 471 | default 648 if MACH_SUN8I_R40 |
Hans de Goede | 59d9fc7 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 472 | default 312 if MACH_SUN6I || MACH_SUN8I |
Icenowy Zheng | b54209f | 2017-06-03 17:10:22 +0800 | [diff] [blame] | 473 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ |
| 474 | MACH_SUN8I_V3S |
Andre Przywara | afd6870 | 2017-01-02 11:48:37 +0000 | [diff] [blame] | 475 | default 672 if MACH_SUN50I |
Icenowy Zheng | 0c01b96 | 2018-07-21 16:20:31 +0800 | [diff] [blame] | 476 | default 744 if MACH_SUN50I_H6 |
Jernej Skrabec | e4aa24b | 2021-01-11 21:11:43 +0100 | [diff] [blame] | 477 | default 720 if MACH_SUN50I_H616 |
Hans de Goede | 3aeaa28 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 478 | ---help--- |
Philipp Tomsich | d36af1c | 2016-10-28 18:21:28 +0800 | [diff] [blame] | 479 | Set the dram clock speed, valid range 240 - 480 (prior to sun9i), |
| 480 | must be a multiple of 24. For the sun9i (A80), the tested values |
| 481 | (for DDR3-1600) are 312 to 792. |
Hans de Goede | 3aeaa28 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 482 | |
Siarhei Siamashka | 47359bb | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 483 | if MACH_SUN5I || MACH_SUN7I |
| 484 | config DRAM_MBUS_CLK |
| 485 | int "sunxi mbus clock speed" |
| 486 | default 300 |
| 487 | ---help--- |
| 488 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. |
| 489 | |
| 490 | endif |
| 491 | |
Hans de Goede | 3aeaa28 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 492 | config DRAM_ZQ |
Hans de Goede | 59d9fc7 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 493 | int "sunxi dram zq value" |
Jernej Skrabec | e4aa24b | 2021-01-11 21:11:43 +0100 | [diff] [blame] | 494 | depends on !MACH_SUN50I_H616 |
Paul Kocialkowski | 70373ca | 2019-03-14 11:36:14 +0100 | [diff] [blame] | 495 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \ |
Paul Kocialkowski | 4d492a3 | 2019-03-14 11:36:15 +0100 | [diff] [blame] | 496 | MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T |
Hans de Goede | 59d9fc7 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 497 | default 127 if MACH_SUN7I |
Icenowy Zheng | b54209f | 2017-06-03 17:10:22 +0800 | [diff] [blame] | 498 | default 14779 if MACH_SUN8I_V3S |
Paul Kocialkowski | 4d492a3 | 2019-03-14 11:36:15 +0100 | [diff] [blame] | 499 | default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6 |
Chen-Yu Tsai | 47bb306 | 2016-10-28 18:21:36 +0800 | [diff] [blame] | 500 | default 4145117 if MACH_SUN9I |
Andre Przywara | afd6870 | 2017-01-02 11:48:37 +0000 | [diff] [blame] | 501 | default 3881915 if MACH_SUN50I |
Hans de Goede | 3aeaa28 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 502 | ---help--- |
Hans de Goede | 06ddc45 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 503 | Set the dram zq value. |
Hans de Goede | 3aeaa28 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 504 | |
Hans de Goede | ffdc05c | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 505 | config DRAM_ODT_EN |
| 506 | bool "sunxi dram odt enable" |
Hans de Goede | ffdc05c | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 507 | default y if MACH_SUN8I_A23 |
Paul Kocialkowski | d6c5cfc | 2019-03-14 11:36:16 +0100 | [diff] [blame] | 508 | default y if MACH_SUNXI_H3_H5 |
Chen-Yu Tsai | f361d56 | 2016-11-30 16:58:35 +0800 | [diff] [blame] | 509 | default y if MACH_SUN8I_R40 |
Andre Przywara | a563adc | 2017-01-02 11:48:45 +0000 | [diff] [blame] | 510 | default y if MACH_SUN50I |
Icenowy Zheng | 0c01b96 | 2018-07-21 16:20:31 +0800 | [diff] [blame] | 511 | default y if MACH_SUN50I_H6 |
Jernej Skrabec | e4aa24b | 2021-01-11 21:11:43 +0100 | [diff] [blame] | 512 | default y if MACH_SUN50I_H616 |
Hans de Goede | ffdc05c | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 513 | ---help--- |
| 514 | Select this to enable dram odt (on die termination). |
| 515 | |
Hans de Goede | 59d9fc7 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 516 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
| 517 | config DRAM_EMR1 |
| 518 | int "sunxi dram emr1 value" |
| 519 | default 0 if MACH_SUN4I |
| 520 | default 4 if MACH_SUN5I || MACH_SUN7I |
| 521 | ---help--- |
Hans de Goede | 06ddc45 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 522 | Set the dram controller emr1 value. |
Siarhei Siamashka | 9900db1 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 523 | |
Siarhei Siamashka | 47359bb | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 524 | config DRAM_TPR3 |
| 525 | hex "sunxi dram tpr3 value" |
| 526 | default 0 |
| 527 | ---help--- |
| 528 | Set the dram controller tpr3 parameter. This parameter configures |
| 529 | the delay on the command lane and also phase shifts, which are |
| 530 | applied for sampling incoming read data. The default value 0 |
| 531 | means that no phase/delay adjustments are necessary. Properly |
| 532 | configuring this parameter increases reliability at high DRAM |
| 533 | clock speeds. |
| 534 | |
| 535 | config DRAM_DQS_GATING_DELAY |
| 536 | hex "sunxi dram dqs_gating_delay value" |
| 537 | default 0 |
| 538 | ---help--- |
| 539 | Set the dram controller dqs_gating_delay parmeter. Each byte |
| 540 | encodes the DQS gating delay for each byte lane. The delay |
| 541 | granularity is 1/4 cycle. For example, the value 0x05060606 |
| 542 | means that the delay is 5 quarter-cycles for one lane (1.25 |
| 543 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. |
| 544 | The default value 0 means autodetection. The results of hardware |
| 545 | autodetection are not very reliable and depend on the chip |
| 546 | temperature (sometimes producing different results on cold start |
| 547 | and warm reboot). But the accuracy of hardware autodetection |
| 548 | is usually good enough, unless running at really high DRAM |
| 549 | clocks speeds (up to 600MHz). If unsure, keep as 0. |
| 550 | |
Siarhei Siamashka | 9900db1 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 551 | choice |
| 552 | prompt "sunxi dram timings" |
| 553 | default DRAM_TIMINGS_VENDOR_MAGIC |
| 554 | ---help--- |
| 555 | Select the timings of the DDR3 chips. |
| 556 | |
| 557 | config DRAM_TIMINGS_VENDOR_MAGIC |
| 558 | bool "Magic vendor timings from Android" |
| 559 | ---help--- |
| 560 | The same DRAM timings as in the Allwinner boot0 bootloader. |
| 561 | |
| 562 | config DRAM_TIMINGS_DDR3_1066F_1333H |
| 563 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" |
| 564 | ---help--- |
| 565 | Use the timings of the standard JEDEC DDR3-1066F speed bin for |
| 566 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin |
| 567 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips |
| 568 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 |
| 569 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm |
| 570 | that down binning to DDR3-1066F is supported (because DDR3-1066F |
| 571 | uses a bit faster timings than DDR3-1333H). |
| 572 | |
| 573 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J |
| 574 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" |
| 575 | ---help--- |
| 576 | Use the timings of the slowest possible JEDEC speed bin for the |
| 577 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be |
| 578 | DDR3-800E, DDR3-1066G or DDR3-1333J. |
| 579 | |
| 580 | endchoice |
| 581 | |
Hans de Goede | 3aeaa28 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 582 | endif |
| 583 | |
Hans de Goede | ffdc05c | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 584 | if MACH_SUN8I_A23 |
| 585 | config DRAM_ODT_CORRECTION |
| 586 | int "sunxi dram odt correction value" |
| 587 | default 0 |
| 588 | ---help--- |
| 589 | Set the dram odt correction value (range -255 - 255). In allwinner |
| 590 | fex files, this option is found in bits 8-15 of the u32 odt_en variable |
| 591 | in the [dram] section. When bit 31 of the odt_en variable is set |
| 592 | then the correction is negative. Usually the value for this is 0. |
| 593 | endif |
| 594 | |
Iain Paton | 630df14 | 2015-03-28 10:26:38 +0000 | [diff] [blame] | 595 | config SYS_CLK_FREQ |
Icenowy Zheng | 8f2d1c0 | 2022-01-29 10:23:07 -0500 | [diff] [blame] | 596 | default 408000000 if MACH_SUNIV |
Chen-Yu Tsai | fa33746 | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 597 | default 1008000000 if MACH_SUN4I |
| 598 | default 1008000000 if MACH_SUN5I |
| 599 | default 1008000000 if MACH_SUN6I |
Iain Paton | 630df14 | 2015-03-28 10:26:38 +0000 | [diff] [blame] | 600 | default 912000000 if MACH_SUN7I |
Icenowy Zheng | 2e915b4 | 2017-10-31 07:36:28 +0800 | [diff] [blame] | 601 | default 816000000 if MACH_SUN50I || MACH_SUN50I_H5 |
Chen-Yu Tsai | fa33746 | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 602 | default 1008000000 if MACH_SUN8I |
| 603 | default 1008000000 if MACH_SUN9I |
Icenowy Zheng | 0c01b96 | 2018-07-21 16:20:31 +0800 | [diff] [blame] | 604 | default 888000000 if MACH_SUN50I_H6 |
Jernej Skrabec | e638e05 | 2021-01-11 21:11:46 +0100 | [diff] [blame] | 605 | default 1008000000 if MACH_SUN50I_H616 |
Iain Paton | 630df14 | 2015-03-28 10:26:38 +0000 | [diff] [blame] | 606 | |
Maxime Ripard | 2c51941 | 2014-10-03 20:16:29 +0800 | [diff] [blame] | 607 | config SYS_CONFIG_NAME |
Icenowy Zheng | 8f2d1c0 | 2022-01-29 10:23:07 -0500 | [diff] [blame] | 608 | default "suniv" if MACH_SUNIV |
Ian Campbell | 4a24a1c | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 609 | default "sun4i" if MACH_SUN4I |
| 610 | default "sun5i" if MACH_SUN5I |
| 611 | default "sun6i" if MACH_SUN6I |
| 612 | default "sun7i" if MACH_SUN7I |
| 613 | default "sun8i" if MACH_SUN8I |
Hans de Goede | 7bfe2bb | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 614 | default "sun9i" if MACH_SUN9I |
Siarhei Siamashka | 26c50fb | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 615 | default "sun50i" if MACH_SUN50I |
Icenowy Zheng | 0c01b96 | 2018-07-21 16:20:31 +0800 | [diff] [blame] | 616 | default "sun50i" if MACH_SUN50I_H6 |
Jernej Skrabec | e638e05 | 2021-01-11 21:11:46 +0100 | [diff] [blame] | 617 | default "sun50i" if MACH_SUN50I_H616 |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 618 | |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 619 | config SYS_BOARD |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 620 | default "sunxi" |
| 621 | |
| 622 | config SYS_SOC |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 623 | default "sunxi" |
| 624 | |
Siarhei Siamashka | 121161f | 2014-12-25 02:34:47 +0200 | [diff] [blame] | 625 | config UART0_PORT_F |
| 626 | bool "UART0 on MicroSD breakout board" |
Siarhei Siamashka | 121161f | 2014-12-25 02:34:47 +0200 | [diff] [blame] | 627 | ---help--- |
| 628 | Repurpose the SD card slot for getting access to the UART0 serial |
| 629 | console. Primarily useful only for low level u-boot debugging on |
| 630 | tablets, where normal UART0 is difficult to access and requires |
| 631 | device disassembly and/or soldering. As the SD card can't be used |
| 632 | at the same time, the system can be only booted in the FEL mode. |
| 633 | Only enable this if you really know what you are doing. |
| 634 | |
Hans de Goede | 05e5bcb | 2014-10-22 14:56:36 +0200 | [diff] [blame] | 635 | config OLD_SUNXI_KERNEL_COMPAT |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 636 | bool "Enable workarounds for booting old kernels" |
Hans de Goede | 05e5bcb | 2014-10-22 14:56:36 +0200 | [diff] [blame] | 637 | ---help--- |
| 638 | Set this to enable various workarounds for old kernels, this results in |
| 639 | sub-optimal settings for newer kernels, only enable if needed. |
| 640 | |
Mylène Josserand | 147c606 | 2017-04-02 12:59:10 +0200 | [diff] [blame] | 641 | config MACPWR |
| 642 | string "MAC power pin" |
| 643 | default "" |
| 644 | help |
| 645 | Set the pin used to power the MAC. This takes a string in the format |
| 646 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 647 | |
Hans de Goede | 7412ef8 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 648 | config MMC0_CD_PIN |
| 649 | string "Card detect pin for mmc0" |
Andre Przywara | 5fb9743 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 650 | default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I |
Hans de Goede | 7412ef8 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 651 | default "" |
| 652 | ---help--- |
| 653 | Set the card detect pin for mmc0, leave empty to not use cd. This |
| 654 | takes a string in the format understood by sunxi_name_to_gpio, e.g. |
| 655 | PH1 for pin 1 of port H. |
| 656 | |
| 657 | config MMC1_CD_PIN |
| 658 | string "Card detect pin for mmc1" |
| 659 | default "" |
| 660 | ---help--- |
| 661 | See MMC0_CD_PIN help text. |
| 662 | |
| 663 | config MMC2_CD_PIN |
| 664 | string "Card detect pin for mmc2" |
| 665 | default "" |
| 666 | ---help--- |
| 667 | See MMC0_CD_PIN help text. |
| 668 | |
| 669 | config MMC3_CD_PIN |
| 670 | string "Card detect pin for mmc3" |
| 671 | default "" |
| 672 | ---help--- |
| 673 | See MMC0_CD_PIN help text. |
| 674 | |
Samuel Holland | 5195105 | 2021-09-12 10:28:35 -0500 | [diff] [blame] | 675 | config MMC1_PINS_PH |
| 676 | bool "Pins for mmc1 are on Port H" |
| 677 | depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40 |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 678 | ---help--- |
Samuel Holland | 5195105 | 2021-09-12 10:28:35 -0500 | [diff] [blame] | 679 | Select this option for boards where mmc1 uses the Port H pinmux. |
Paul Kocialkowski | d390d8c | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 680 | |
Hans de Goede | af593e4 | 2014-10-02 20:43:50 +0200 | [diff] [blame] | 681 | config MMC_SUNXI_SLOT_EXTRA |
| 682 | int "mmc extra slot number" |
| 683 | default -1 |
| 684 | ---help--- |
| 685 | sunxi builds always enable mmc0, some boards also have a second sdcard |
| 686 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable |
| 687 | support for this. |
| 688 | |
Hans de Goede | 99c9fb0 | 2016-04-01 22:39:26 +0200 | [diff] [blame] | 689 | config INITIAL_USB_SCAN_DELAY |
| 690 | int "delay initial usb scan by x ms to allow builtin devices to init" |
| 691 | default 0 |
| 692 | ---help--- |
| 693 | Some boards have on board usb devices which need longer than the |
| 694 | USB spec's 1 second to connect from board powerup. Set this config |
| 695 | option to a non 0 value to add an extra delay before the first usb |
| 696 | bus scan. |
| 697 | |
Hans de Goede | e7b852a | 2015-01-07 15:26:06 +0100 | [diff] [blame] | 698 | config USB0_VBUS_PIN |
| 699 | string "Vbus enable pin for usb0 (otg)" |
| 700 | default "" |
| 701 | ---help--- |
| 702 | Set the Vbus enable pin for usb0 (otg). This takes a string in the |
| 703 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 704 | |
Hans de Goede | eaa0d70 | 2015-02-16 22:13:43 +0100 | [diff] [blame] | 705 | config USB0_VBUS_DET |
| 706 | string "Vbus detect pin for usb0 (otg)" |
Hans de Goede | eaa0d70 | 2015-02-16 22:13:43 +0100 | [diff] [blame] | 707 | default "" |
| 708 | ---help--- |
| 709 | Set the Vbus detect pin for usb0 (otg). This takes a string in the |
| 710 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 711 | |
Hans de Goede | aadd97f | 2015-06-14 17:29:53 +0200 | [diff] [blame] | 712 | config USB0_ID_DET |
| 713 | string "ID detect pin for usb0 (otg)" |
| 714 | default "" |
| 715 | ---help--- |
| 716 | Set the ID detect pin for usb0 (otg). This takes a string in the |
| 717 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 718 | |
Hans de Goede | af4273b | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 719 | config USB1_VBUS_PIN |
| 720 | string "Vbus enable pin for usb1 (ehci0)" |
| 721 | default "PH6" if MACH_SUN4I || MACH_SUN7I |
Hans de Goede | b5ab8ce | 2014-11-07 14:51:12 +0100 | [diff] [blame] | 722 | default "PH27" if MACH_SUN6I |
Hans de Goede | af4273b | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 723 | ---help--- |
| 724 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes |
| 725 | a string in the format understood by sunxi_name_to_gpio, e.g. |
| 726 | PH1 for pin 1 of port H. |
| 727 | |
| 728 | config USB2_VBUS_PIN |
| 729 | string "Vbus enable pin for usb2 (ehci1)" |
| 730 | default "PH3" if MACH_SUN4I || MACH_SUN7I |
Hans de Goede | b5ab8ce | 2014-11-07 14:51:12 +0100 | [diff] [blame] | 731 | default "PH24" if MACH_SUN6I |
Hans de Goede | af4273b | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 732 | ---help--- |
| 733 | See USB1_VBUS_PIN help text. |
| 734 | |
Hans de Goede | a60c3fc | 2016-03-18 08:42:01 +0100 | [diff] [blame] | 735 | config USB3_VBUS_PIN |
| 736 | string "Vbus enable pin for usb3 (ehci2)" |
| 737 | default "" |
| 738 | ---help--- |
| 739 | See USB1_VBUS_PIN help text. |
| 740 | |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 741 | config I2C0_ENABLE |
| 742 | bool "Enable I2C/TWI controller 0" |
Chen-Yu Tsai | 478a3c5 | 2016-11-30 15:30:30 +0800 | [diff] [blame] | 743 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 744 | default n if MACH_SUN6I || MACH_SUN8I |
Hans de Goede | 2c52640 | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 745 | select CMD_I2C |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 746 | ---help--- |
| 747 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling |
| 748 | its clock and setting up the bus. This is especially useful on devices |
| 749 | with slaves connected to the bus or with pins exposed through e.g. an |
| 750 | expansion port/header. |
| 751 | |
| 752 | config I2C1_ENABLE |
| 753 | bool "Enable I2C/TWI controller 1" |
Hans de Goede | 2c52640 | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 754 | select CMD_I2C |
Paul Kocialkowski | 0a3ec0a | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 755 | ---help--- |
| 756 | See I2C0_ENABLE help text. |
| 757 | |
Jernej Skrabec | 55a30a2 | 2021-01-11 21:11:38 +0100 | [diff] [blame] | 758 | if SUNXI_GEN_SUN6I || SUN50I_GEN_H6 |
Jelle van der Waa | 8d3d7c1 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 759 | config R_I2C_ENABLE |
| 760 | bool "Enable the PRCM I2C/TWI controller" |
Jelle van der Waa | 3f3a309 | 2016-02-23 18:47:19 +0100 | [diff] [blame] | 761 | # This is used for the pmic on H3 |
| 762 | default y if SY8106A_POWER |
Hans de Goede | 2c52640 | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 763 | select CMD_I2C |
Jelle van der Waa | 8d3d7c1 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 764 | ---help--- |
| 765 | Set this to y to enable the I2C controller which is part of the PRCM. |
Jelle van der Waa | 3f3a309 | 2016-02-23 18:47:19 +0100 | [diff] [blame] | 766 | endif |
Jelle van der Waa | 8d3d7c1 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 767 | |
Hans de Goede | 3ae1d13 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 768 | config AXP_GPIO |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 769 | bool "Enable support for gpio-s on axp PMICs" |
Samuel Holland | 623b804 | 2021-10-08 00:17:19 -0500 | [diff] [blame] | 770 | depends on AXP_PMIC_BUS |
Hans de Goede | 3ae1d13 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 771 | ---help--- |
| 772 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. |
| 773 | |
Chris Morgan | 2ff2a1d | 2022-01-21 13:37:32 +0000 | [diff] [blame] | 774 | config AXP_DISABLE_BOOT_ON_POWERON |
| 775 | bool "Disable device boot on power plug-in" |
| 776 | depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER |
| 777 | default n |
| 778 | ---help--- |
| 779 | Say Y here to prevent the device from booting up because of a plug-in |
| 780 | event. When set, the device will boot into the SPL briefly to |
| 781 | determine why it was powered on, and if it was determined because of |
| 782 | a plug-in event instead of a button press event it will shut back off. |
| 783 | |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 784 | config VIDEO_SUNXI |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 785 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
Chen-Yu Tsai | fa33746 | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 786 | depends on !MACH_SUN8I_A83T |
| 787 | depends on !MACH_SUNXI_H3_H5 |
Chen-Yu Tsai | cc2605e | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 788 | depends on !MACH_SUN8I_R40 |
Icenowy Zheng | 52e6188 | 2017-04-08 15:30:12 +0800 | [diff] [blame] | 789 | depends on !MACH_SUN8I_V3S |
Chen-Yu Tsai | fa33746 | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 790 | depends on !MACH_SUN9I |
| 791 | depends on !MACH_SUN50I |
Jernej Skrabec | da8ae61 | 2021-01-11 21:11:34 +0100 | [diff] [blame] | 792 | depends on !SUN50I_GEN_H6 |
Jagan Teki | 5bc34cb | 2021-02-22 00:12:34 +0000 | [diff] [blame] | 793 | select DM_VIDEO |
| 794 | select DISPLAY |
Icenowy Zheng | 60e4b8f | 2017-10-26 11:14:46 +0800 | [diff] [blame] | 795 | imply VIDEO_DT_SIMPLEFB |
Luc Verhaegen | b01df1e | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 796 | default y |
| 797 | ---help--- |
Jagan Teki | 5bc34cb | 2021-02-22 00:12:34 +0000 | [diff] [blame] | 798 | Say Y here to add support for using a graphical console on the HDMI, |
| 799 | LCD or VGA output found on older sunxi devices. This will also provide |
| 800 | a simple_framebuffer device for Linux. |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 801 | |
Hans de Goede | e954459 | 2014-12-23 23:04:35 +0100 | [diff] [blame] | 802 | config VIDEO_HDMI |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 803 | bool "HDMI output support" |
Icenowy Zheng | 8f2d1c0 | 2022-01-29 10:23:07 -0500 | [diff] [blame] | 804 | depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV |
Hans de Goede | e954459 | 2014-12-23 23:04:35 +0100 | [diff] [blame] | 805 | default y |
| 806 | ---help--- |
| 807 | Say Y here to add support for outputting video over HDMI. |
| 808 | |
Hans de Goede | 260f520 | 2014-12-25 13:58:06 +0100 | [diff] [blame] | 809 | config VIDEO_VGA |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 810 | bool "VGA output support" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 811 | depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I) |
Hans de Goede | 260f520 | 2014-12-25 13:58:06 +0100 | [diff] [blame] | 812 | ---help--- |
| 813 | Say Y here to add support for outputting video over VGA. |
| 814 | |
Hans de Goede | ac1633c | 2014-12-24 12:17:07 +0100 | [diff] [blame] | 815 | config VIDEO_VGA_VIA_LCD |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 816 | bool "VGA via LCD controller support" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 817 | depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
Hans de Goede | ac1633c | 2014-12-24 12:17:07 +0100 | [diff] [blame] | 818 | ---help--- |
| 819 | Say Y here to add support for external DACs connected to the parallel |
| 820 | LCD interface driving a VGA connector, such as found on the |
| 821 | Olimex A13 boards. |
| 822 | |
Hans de Goede | 18366f7 | 2015-01-25 15:33:07 +0100 | [diff] [blame] | 823 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 824 | bool "Force sync active high for VGA via LCD controller support" |
Hans de Goede | 18366f7 | 2015-01-25 15:33:07 +0100 | [diff] [blame] | 825 | depends on VIDEO_VGA_VIA_LCD |
Hans de Goede | 18366f7 | 2015-01-25 15:33:07 +0100 | [diff] [blame] | 826 | ---help--- |
| 827 | Say Y here if you've a board which uses opendrain drivers for the vga |
| 828 | hsync and vsync signals. Opendrain drivers cannot generate steep enough |
| 829 | positive edges for a stable video output, so on boards with opendrain |
| 830 | drivers the sync signals must always be active high. |
| 831 | |
Chen-Yu Tsai | 9ed1952 | 2015-01-12 18:02:11 +0800 | [diff] [blame] | 832 | config VIDEO_VGA_EXTERNAL_DAC_EN |
| 833 | string "LCD panel power enable pin" |
| 834 | depends on VIDEO_VGA_VIA_LCD |
| 835 | default "" |
| 836 | ---help--- |
| 837 | Set the enable pin for the external VGA DAC. This takes a string in the |
| 838 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 839 | |
Hans de Goede | c06e00e | 2015-08-03 19:20:26 +0200 | [diff] [blame] | 840 | config VIDEO_COMPOSITE |
Masahiro Yamada | 78cd22a | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 841 | bool "Composite video output support" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 842 | depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
Hans de Goede | c06e00e | 2015-08-03 19:20:26 +0200 | [diff] [blame] | 843 | ---help--- |
| 844 | Say Y here to add support for outputting composite video. |
| 845 | |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 846 | config VIDEO_LCD_MODE |
| 847 | string "LCD panel timing details" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 848 | depends on VIDEO_SUNXI |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 849 | default "" |
| 850 | ---help--- |
| 851 | LCD panel timing details string, leave empty if there is no LCD panel. |
| 852 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. |
| 853 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 |
Hans de Goede | 924c893 | 2015-08-16 11:23:42 +0200 | [diff] [blame] | 854 | Also see: http://linux-sunxi.org/LCD |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 855 | |
Hans de Goede | 481b664 | 2015-01-13 13:21:46 +0100 | [diff] [blame] | 856 | config VIDEO_LCD_DCLK_PHASE |
| 857 | int "LCD panel display clock phase" |
Vasily Khoruzhick | 2f0b6e5 | 2017-10-26 21:51:52 -0700 | [diff] [blame] | 858 | depends on VIDEO_SUNXI || DM_VIDEO |
Hans de Goede | 481b664 | 2015-01-13 13:21:46 +0100 | [diff] [blame] | 859 | default 1 |
| 860 | ---help--- |
| 861 | Select LCD panel display clock phase shift, range 0-3. |
| 862 | |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 863 | config VIDEO_LCD_POWER |
| 864 | string "LCD panel power enable pin" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 865 | depends on VIDEO_SUNXI |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 866 | default "" |
| 867 | ---help--- |
| 868 | Set the power enable pin for the LCD panel. This takes a string in the |
| 869 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 870 | |
Hans de Goede | ce9e332 | 2015-02-16 17:26:41 +0100 | [diff] [blame] | 871 | config VIDEO_LCD_RESET |
| 872 | string "LCD panel reset pin" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 873 | depends on VIDEO_SUNXI |
Hans de Goede | ce9e332 | 2015-02-16 17:26:41 +0100 | [diff] [blame] | 874 | default "" |
| 875 | ---help--- |
| 876 | Set the reset pin for the LCD panel. This takes a string in the format |
| 877 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 878 | |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 879 | config VIDEO_LCD_BL_EN |
| 880 | string "LCD panel backlight enable pin" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 881 | depends on VIDEO_SUNXI |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 882 | default "" |
| 883 | ---help--- |
| 884 | Set the backlight enable pin for the LCD panel. This takes a string in the |
| 885 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of |
| 886 | port H. |
| 887 | |
| 888 | config VIDEO_LCD_BL_PWM |
| 889 | string "LCD panel backlight pwm pin" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 890 | depends on VIDEO_SUNXI |
Hans de Goede | 7e68a1b | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 891 | default "" |
| 892 | ---help--- |
| 893 | Set the backlight pwm pin for the LCD panel. This takes a string in the |
| 894 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
Luc Verhaegen | b01df1e | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 895 | |
Hans de Goede | 2d5d302 | 2015-01-22 21:02:42 +0100 | [diff] [blame] | 896 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
| 897 | bool "LCD panel backlight pwm is inverted" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 898 | depends on VIDEO_SUNXI |
Hans de Goede | 2d5d302 | 2015-01-22 21:02:42 +0100 | [diff] [blame] | 899 | default y |
| 900 | ---help--- |
| 901 | Set this if the backlight pwm output is active low. |
| 902 | |
Hans de Goede | a5b4cfe | 2015-02-16 17:23:25 +0100 | [diff] [blame] | 903 | config VIDEO_LCD_PANEL_I2C |
| 904 | bool "LCD panel needs to be configured via i2c" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 905 | depends on VIDEO_SUNXI |
Samuel Holland | 75fe0f4 | 2021-10-08 00:17:24 -0500 | [diff] [blame] | 906 | select DM_I2C_GPIO |
Hans de Goede | a5b4cfe | 2015-02-16 17:23:25 +0100 | [diff] [blame] | 907 | ---help--- |
| 908 | Say y here if the LCD panel needs to be configured via i2c. This |
| 909 | will add a bitbang i2c controller using gpios to talk to the LCD. |
| 910 | |
Samuel Holland | 75fe0f4 | 2021-10-08 00:17:24 -0500 | [diff] [blame] | 911 | config VIDEO_LCD_PANEL_I2C_NAME |
| 912 | string "LCD panel i2c interface node name" |
Hans de Goede | a5b4cfe | 2015-02-16 17:23:25 +0100 | [diff] [blame] | 913 | depends on VIDEO_LCD_PANEL_I2C |
Samuel Holland | 75fe0f4 | 2021-10-08 00:17:24 -0500 | [diff] [blame] | 914 | default "i2c@0" |
Hans de Goede | a5b4cfe | 2015-02-16 17:23:25 +0100 | [diff] [blame] | 915 | ---help--- |
Samuel Holland | 75fe0f4 | 2021-10-08 00:17:24 -0500 | [diff] [blame] | 916 | Set the device tree node name for the LCD i2c interface. |
Hans de Goede | 797a0f5 | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 917 | |
| 918 | # Note only one of these may be selected at a time! But hidden choices are |
| 919 | # not supported by Kconfig |
| 920 | config VIDEO_LCD_IF_PARALLEL |
| 921 | bool |
| 922 | |
| 923 | config VIDEO_LCD_IF_LVDS |
| 924 | bool |
| 925 | |
Jernej Skrabec | 9b4ca92 | 2017-03-27 19:22:31 +0200 | [diff] [blame] | 926 | config SUNXI_DE2 |
| 927 | bool |
Jernej Skrabec | 9b4ca92 | 2017-03-27 19:22:31 +0200 | [diff] [blame] | 928 | |
Jernej Skrabec | 8d91b46 | 2017-03-27 19:22:32 +0200 | [diff] [blame] | 929 | config VIDEO_DE2 |
| 930 | bool "Display Engine 2 video driver" |
| 931 | depends on SUNXI_DE2 |
| 932 | select DM_VIDEO |
| 933 | select DISPLAY |
Jernej Skrabec | c2a50b1 | 2021-03-06 20:54:19 +0100 | [diff] [blame] | 934 | select VIDEO_DW_HDMI |
Icenowy Zheng | 82576de | 2017-10-26 11:14:47 +0800 | [diff] [blame] | 935 | imply VIDEO_DT_SIMPLEFB |
Jernej Skrabec | 8d91b46 | 2017-03-27 19:22:32 +0200 | [diff] [blame] | 936 | default y |
| 937 | ---help--- |
| 938 | Say y here if you want to build DE2 video driver which is present on |
| 939 | newer SoCs. Currently only HDMI output is supported. |
| 940 | |
Hans de Goede | 797a0f5 | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 941 | |
| 942 | choice |
| 943 | prompt "LCD panel support" |
Icenowy Zheng | 1fa956f | 2017-10-26 11:14:44 +0800 | [diff] [blame] | 944 | depends on VIDEO_SUNXI |
Hans de Goede | 797a0f5 | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 945 | ---help--- |
| 946 | Select which type of LCD panel to support. |
| 947 | |
| 948 | config VIDEO_LCD_PANEL_PARALLEL |
| 949 | bool "Generic parallel interface LCD panel" |
| 950 | select VIDEO_LCD_IF_PARALLEL |
| 951 | |
| 952 | config VIDEO_LCD_PANEL_LVDS |
| 953 | bool "Generic lvds interface LCD panel" |
| 954 | select VIDEO_LCD_IF_LVDS |
| 955 | |
Siarhei Siamashka | c02f052 | 2015-01-19 05:23:33 +0200 | [diff] [blame] | 956 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
| 957 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" |
| 958 | select VIDEO_LCD_SSD2828 |
| 959 | select VIDEO_LCD_IF_PARALLEL |
| 960 | ---help--- |
Hans de Goede | 91f1b82 | 2015-08-08 16:13:53 +0200 | [diff] [blame] | 961 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
| 962 | |
| 963 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 |
| 964 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" |
| 965 | select VIDEO_LCD_ANX9804 |
| 966 | select VIDEO_LCD_IF_PARALLEL |
| 967 | select VIDEO_LCD_PANEL_I2C |
| 968 | ---help--- |
| 969 | Select this for eDP LCD panels with 4 lanes running at 1.62G, |
| 970 | connected via an ANX9804 bridge chip. |
Siarhei Siamashka | c02f052 | 2015-01-19 05:23:33 +0200 | [diff] [blame] | 971 | |
Hans de Goede | 743fb955 | 2015-01-20 09:23:36 +0100 | [diff] [blame] | 972 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
| 973 | bool "Hitachi tx18d42vm LCD panel" |
| 974 | select VIDEO_LCD_HITACHI_TX18D42VM |
| 975 | select VIDEO_LCD_IF_LVDS |
| 976 | ---help--- |
| 977 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support |
| 978 | |
Hans de Goede | 613dade | 2015-02-16 17:49:47 +0100 | [diff] [blame] | 979 | config VIDEO_LCD_TL059WV5C0 |
| 980 | bool "tl059wv5c0 LCD panel" |
| 981 | select VIDEO_LCD_PANEL_I2C |
| 982 | select VIDEO_LCD_IF_PARALLEL |
| 983 | ---help--- |
| 984 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and |
| 985 | Aigo M60/M608/M606 tablets. |
| 986 | |
Hans de Goede | 797a0f5 | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 987 | endchoice |
| 988 | |
Mylène Josserand | 628426a | 2017-04-02 12:59:09 +0200 | [diff] [blame] | 989 | config SATAPWR |
| 990 | string "SATA power pin" |
| 991 | default "" |
| 992 | help |
| 993 | Set the pins used to power the SATA. This takes a string in the |
| 994 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of |
| 995 | port H. |
Hans de Goede | 797a0f5 | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 996 | |
Hans de Goede | bf880fe | 2015-01-25 12:10:48 +0100 | [diff] [blame] | 997 | config GMAC_TX_DELAY |
| 998 | int "GMAC Transmit Clock Delay Chain" |
| 999 | default 0 |
| 1000 | ---help--- |
| 1001 | Set the GMAC Transmit Clock Delay Chain value. |
| 1002 | |
Hans de Goede | 66ab79d | 2015-09-13 13:02:48 +0200 | [diff] [blame] | 1003 | config SPL_STACK_R_ADDR |
Icenowy Zheng | 8f2d1c0 | 2022-01-29 10:23:07 -0500 | [diff] [blame] | 1004 | default 0x81e00000 if MACH_SUNIV |
Chen-Yu Tsai | fa33746 | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 1005 | default 0x4fe00000 if MACH_SUN4I |
| 1006 | default 0x4fe00000 if MACH_SUN5I |
| 1007 | default 0x4fe00000 if MACH_SUN6I |
| 1008 | default 0x4fe00000 if MACH_SUN7I |
| 1009 | default 0x4fe00000 if MACH_SUN8I |
Hans de Goede | 66ab79d | 2015-09-13 13:02:48 +0200 | [diff] [blame] | 1010 | default 0x2fe00000 if MACH_SUN9I |
Chen-Yu Tsai | fa33746 | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 1011 | default 0x4fe00000 if MACH_SUN50I |
Jernej Skrabec | da8ae61 | 2021-01-11 21:11:34 +0100 | [diff] [blame] | 1012 | default 0x4fe00000 if SUN50I_GEN_H6 |
Hans de Goede | 66ab79d | 2015-09-13 13:02:48 +0200 | [diff] [blame] | 1013 | |
Jagan Teki | 4e159f8 | 2018-02-06 22:42:56 +0530 | [diff] [blame] | 1014 | config SPL_SPI_SUNXI |
| 1015 | bool "Support for SPI Flash on Allwinner SoCs in SPL" |
Jesse Taube | a8464a1 | 2022-02-11 19:32:35 -0500 | [diff] [blame] | 1016 | depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6 || MACH_SUNIV |
Jagan Teki | 4e159f8 | 2018-02-06 22:42:56 +0530 | [diff] [blame] | 1017 | help |
| 1018 | Enable support for SPI Flash. This option allows SPL to read from |
| 1019 | sunxi SPI Flash. It uses the same method as the boot ROM, so does |
| 1020 | not need any extra configuration. |
| 1021 | |
Icenowy Zheng | 2a269d3 | 2018-10-25 17:23:02 +0800 | [diff] [blame] | 1022 | config PINE64_DT_SELECTION |
| 1023 | bool "Enable Pine64 device tree selection code" |
| 1024 | depends on MACH_SUN50I |
| 1025 | help |
| 1026 | The original Pine A64 and Pine A64+ are similar but different |
| 1027 | boards and can be differed by the DRAM size. Pine A64 has |
| 1028 | 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this |
| 1029 | option, the device tree selection code specific to Pine64 which |
| 1030 | utilizes the DRAM size will be enabled. |
| 1031 | |
Samuel Holland | 9c7cefc | 2020-10-24 10:21:52 -0500 | [diff] [blame] | 1032 | config PINEPHONE_DT_SELECTION |
| 1033 | bool "Enable PinePhone device tree selection code" |
| 1034 | depends on MACH_SUN50I |
| 1035 | help |
| 1036 | Enable this option to automatically select the device tree for the |
| 1037 | correct PinePhone hardware revision during boot. |
| 1038 | |
Andre Heider | bf8c810 | 2021-10-01 19:29:00 +0100 | [diff] [blame] | 1039 | config BLUETOOTH_DT_DEVICE_FIXUP |
| 1040 | string "Fixup the Bluetooth controller address" |
| 1041 | default "" |
| 1042 | help |
| 1043 | This option specifies the DT compatible name of the Bluetooth |
| 1044 | controller for which to set the "local-bd-address" property. |
| 1045 | Set this option if your device ships with the Bluetooth controller |
| 1046 | default address. |
| 1047 | The used address is "bdaddr" if set, and "ethaddr" with the LSB |
| 1048 | flipped elsewise. |
| 1049 | |
Samuel Holland | 7591a04 | 2022-03-18 00:00:45 -0500 | [diff] [blame] | 1050 | source "board/sunxi/Kconfig" |
| 1051 | |
Masahiro Yamada | d3ae678 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1052 | endif |
Kory Maincent | fe4c155 | 2021-05-04 19:31:27 +0200 | [diff] [blame] | 1053 | |
| 1054 | config CHIP_DIP_SCAN |
| 1055 | bool "Enable DIPs detection for CHIP board" |
| 1056 | select SUPPORT_EXTENSION_SCAN |
| 1057 | select W1 |
| 1058 | select W1_GPIO |
| 1059 | select W1_EEPROM |
| 1060 | select W1_EEPROM_DS24XXX |
| 1061 | select CMD_EXTENSION |