blob: 4d465872140b11bf942d52706c7fd23bfd1eeffe [file] [log] [blame]
York Sunb3d71642016-09-26 08:09:26 -07001config ARCH_LS1012A
York Sunfcd0e742016-10-04 14:31:47 -07002 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +08003 select ARMV8_SET_SMPEN
Rajesh Bhagatcd786e82018-11-05 18:01:48 +00004 select ARM_ERRATA_855873 if !TFABOOT
Rajesh Bhagat52d237a2019-01-25 13:36:26 +00005 select FSL_LAYERSCAPE
York Sun4dd8c612016-10-04 14:31:48 -07006 select FSL_LSCH2
Sriram Dash4a943332018-01-30 15:58:44 +05307 select SYS_FSL_SRDS_1
8 select SYS_HAS_SERDES
York Sunb6fffd82016-10-04 18:03:08 -07009 select SYS_FSL_DDR_BE
York Sunb3d71642016-09-26 08:09:26 -070010 select SYS_FSL_MMDC
York Sun149eb332016-09-26 08:09:27 -070011 select SYS_FSL_ERRATUM_A010315
Ran Wang02dc77b2017-11-13 16:14:48 +080012 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
Simon Glass62adede2017-01-23 13:31:19 -070016 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070017 select BOARD_EARLY_INIT_F
Sriram Dash7122a0c2018-02-06 11:26:30 +053018 select SYS_I2C_MXC
Biwen Li0a759bb2019-12-31 15:33:41 +080019 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C
Masahiro Yamadaacede7a2017-12-04 12:37:00 +090021 imply PANIC_HANG
York Sun149eb332016-09-26 08:09:27 -070022
Yuantian Tang4aefa162019-04-10 16:43:33 +080023config ARCH_LS1028A
24 bool
25 select ARMV8_SET_SMPEN
Michael Walle66f2a532020-05-10 01:20:11 +020026 select FSL_LAYERSCAPE
Yuantian Tang4aefa162019-04-10 16:43:33 +080027 select FSL_LSCH3
28 select NXP_LSCH3_2
29 select SYS_FSL_HAS_CCI400
30 select SYS_FSL_SRDS_1
31 select SYS_HAS_SERDES
32 select SYS_FSL_DDR
33 select SYS_FSL_DDR_LE
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DDR3
36 select SYS_FSL_HAS_DDR4
37 select SYS_FSL_HAS_SEC
38 select SYS_FSL_SEC_COMPAT_5
39 select SYS_FSL_SEC_LE
40 select FSL_TZASC_1
41 select ARCH_EARLY_INIT_R
42 select BOARD_EARLY_INIT_F
43 select SYS_I2C_MXC
Ran Wange118acb2019-05-14 17:34:56 +080044 select SYS_FSL_ERRATUM_A008997
Yuantian Tang4aefa162019-04-10 16:43:33 +080045 select SYS_FSL_ERRATUM_A009007
46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
Laurentiu Tudor7ea2feb2019-10-18 09:01:56 +000049 select SYS_FSL_ERRATUM_A050382
Hou Zhiqiangce4a92a2020-04-28 10:19:31 +080050 select RESV_RAM if GIC_V3_ITS
Yuantian Tang4aefa162019-04-10 16:43:33 +080051 imply PANIC_HANG
52
York Sun149eb332016-09-26 08:09:27 -070053config ARCH_LS1043A
York Sunfcd0e742016-10-04 14:31:47 -070054 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080055 select ARMV8_SET_SMPEN
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000056 select ARM_ERRATA_855873 if !TFABOOT
Rajesh Bhagat52d237a2019-01-25 13:36:26 +000057 select FSL_LAYERSCAPE
York Sun4dd8c612016-10-04 14:31:48 -070058 select FSL_LSCH2
Sriram Dash4a943332018-01-30 15:58:44 +053059 select SYS_FSL_SRDS_1
60 select SYS_HAS_SERDES
York Sund297d392016-12-28 08:43:40 -080061 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070062 select SYS_FSL_DDR_BE
63 select SYS_FSL_DDR_VER_50
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000064 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
Ran Wange64f7472017-09-04 18:46:50 +080065 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +080066 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +080067 select SYS_FSL_ERRATUM_A009008
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000068 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
69 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
Ran Wang9e8fabc2017-09-04 18:46:49 +080070 select SYS_FSL_ERRATUM_A009798
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000071 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
York Sun149eb332016-09-26 08:09:27 -070072 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +080073 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -080074 select SYS_FSL_HAS_DDR3
75 select SYS_FSL_HAS_DDR4
Simon Glass62adede2017-01-23 13:31:19 -070076 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070077 select BOARD_EARLY_INIT_F
Biwen Li42637e72020-06-04 18:42:14 +080078 select SYS_I2C_MXC
Biwen Li014460b2020-02-05 22:02:16 +080079 select SYS_I2C_MXC_I2C1 if !DM_I2C
80 select SYS_I2C_MXC_I2C2 if !DM_I2C
81 select SYS_I2C_MXC_I2C3 if !DM_I2C
82 select SYS_I2C_MXC_I2C4 if !DM_I2C
Simon Glassc88a09a2017-08-04 16:34:34 -060083 imply CMD_PCI
York Sunb3d71642016-09-26 08:09:26 -070084
York Sunbad49842016-09-26 08:09:24 -070085config ARCH_LS1046A
York Sunfcd0e742016-10-04 14:31:47 -070086 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080087 select ARMV8_SET_SMPEN
Rajesh Bhagat52d237a2019-01-25 13:36:26 +000088 select FSL_LAYERSCAPE
York Sun4dd8c612016-10-04 14:31:48 -070089 select FSL_LSCH2
Sriram Dash4a943332018-01-30 15:58:44 +053090 select SYS_FSL_SRDS_1
91 select SYS_HAS_SERDES
York Sund297d392016-12-28 08:43:40 -080092 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070093 select SYS_FSL_DDR_BE
York Sunb6fffd82016-10-04 18:03:08 -070094 select SYS_FSL_DDR_VER_50
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000095 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
97 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
Ran Wange64f7472017-09-04 18:46:50 +080098 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +080099 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +0800100 select SYS_FSL_ERRATUM_A009008
Ran Wang9e8fabc2017-09-04 18:46:49 +0800101 select SYS_FSL_ERRATUM_A009798
York Sun1dc61ca2016-12-28 08:43:41 -0800102 select SYS_FSL_ERRATUM_A009801
Rajesh Bhagatcd786e82018-11-05 18:01:48 +0000103 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
104 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
105 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800106 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -0800107 select SYS_FSL_HAS_DDR4
York Sun6b62ef02016-10-04 18:01:34 -0700108 select SYS_FSL_SRDS_2
Simon Glass62adede2017-01-23 13:31:19 -0700109 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -0700110 select BOARD_EARLY_INIT_F
Biwen Li42637e72020-06-04 18:42:14 +0800111 select SYS_I2C_MXC
Biwen Lif0018f52020-02-05 22:02:17 +0800112 select SYS_I2C_MXC_I2C1 if !DM_I2C
113 select SYS_I2C_MXC_I2C2 if !DM_I2C
114 select SYS_I2C_MXC_I2C3 if !DM_I2C
115 select SYS_I2C_MXC_I2C4 if !DM_I2C
Simon Glass0e5faf02017-06-14 21:28:21 -0600116 imply SCSI
Tuomas Tynkkynenedf9f622017-12-08 15:36:19 +0200117 imply SCSI_AHCI
York Sunb3d71642016-09-26 08:09:26 -0700118
Ashish Kumarb25faa22017-08-31 16:12:53 +0530119config ARCH_LS1088A
120 bool
121 select ARMV8_SET_SMPEN
Pankit Gargf5c2a832018-12-27 04:37:55 +0000122 select ARM_ERRATA_855873 if !TFABOOT
Rajesh Bhagat52d237a2019-01-25 13:36:26 +0000123 select FSL_LAYERSCAPE
Ashish Kumarb25faa22017-08-31 16:12:53 +0530124 select FSL_LSCH3
Sriram Dash4a943332018-01-30 15:58:44 +0530125 select SYS_FSL_SRDS_1
126 select SYS_HAS_SERDES
Ashish Kumarb25faa22017-08-31 16:12:53 +0530127 select SYS_FSL_DDR
128 select SYS_FSL_DDR_LE
129 select SYS_FSL_DDR_VER_50
Ashish Kumarec455e22017-08-31 16:37:31 +0530130 select SYS_FSL_EC1
131 select SYS_FSL_EC2
Pankit Gargf5c2a832018-12-27 04:37:55 +0000132 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
133 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
134 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
135 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
136 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
Ran Wangef277072017-09-22 15:21:34 +0800137 select SYS_FSL_ERRATUM_A009007
Ashish Kumarb25faa22017-08-31 16:12:53 +0530138 select SYS_FSL_HAS_CCI400
139 select SYS_FSL_HAS_DDR4
Ashish Kumarec455e22017-08-31 16:37:31 +0530140 select SYS_FSL_HAS_RGMII
Ashish Kumarb25faa22017-08-31 16:12:53 +0530141 select SYS_FSL_HAS_SEC
142 select SYS_FSL_SEC_COMPAT_5
143 select SYS_FSL_SEC_LE
144 select SYS_FSL_SRDS_1
145 select SYS_FSL_SRDS_2
146 select FSL_TZASC_1
Rajesh Bhagat5756f7e2019-01-20 05:30:06 +0000147 select FSL_TZASC_400
148 select FSL_TZPC_BP147
Ashish Kumarb25faa22017-08-31 16:12:53 +0530149 select ARCH_EARLY_INIT_R
150 select BOARD_EARLY_INIT_F
Sriram Dash7122a0c2018-02-06 11:26:30 +0530151 select SYS_I2C_MXC
Chuanhua Han98a5e402019-07-26 20:25:37 +0800152 select SYS_I2C_MXC_I2C1 if !TFABOOT
153 select SYS_I2C_MXC_I2C2 if !TFABOOT
154 select SYS_I2C_MXC_I2C3 if !TFABOOT
155 select SYS_I2C_MXC_I2C4 if !TFABOOT
Hou Zhiqiangce4a92a2020-04-28 10:19:31 +0800156 select RESV_RAM if GIC_V3_ITS
Ashish Kumara179e562017-11-02 09:50:47 +0530157 imply SCSI
Masahiro Yamadaacede7a2017-12-04 12:37:00 +0900158 imply PANIC_HANG
Ashish Kumarb25faa22017-08-31 16:12:53 +0530159
York Sunfcd0e742016-10-04 14:31:47 -0700160config ARCH_LS2080A
161 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +0800162 select ARMV8_SET_SMPEN
Tom Rinibacb52c2017-03-07 07:13:42 -0500163 select ARM_ERRATA_826974
164 select ARM_ERRATA_828024
165 select ARM_ERRATA_829520
166 select ARM_ERRATA_833471
Rajesh Bhagat52d237a2019-01-25 13:36:26 +0000167 select FSL_LAYERSCAPE
York Sun4dd8c612016-10-04 14:31:48 -0700168 select FSL_LSCH3
Sriram Dash4a943332018-01-30 15:58:44 +0530169 select SYS_FSL_SRDS_1
170 select SYS_HAS_SERDES
York Sund297d392016-12-28 08:43:40 -0800171 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -0700172 select SYS_FSL_DDR_LE
173 select SYS_FSL_DDR_VER_50
Ashish Kumar97393d62017-08-18 10:54:36 +0530174 select SYS_FSL_HAS_CCN504
York Sun6b62ef02016-10-04 18:01:34 -0700175 select SYS_FSL_HAS_DP_DDR
York Sun92c36e22016-12-28 08:43:30 -0800176 select SYS_FSL_HAS_SEC
York Sund297d392016-12-28 08:43:40 -0800177 select SYS_FSL_HAS_DDR4
York Sun92c36e22016-12-28 08:43:30 -0800178 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -0800179 select SYS_FSL_SEC_LE
York Sun6b62ef02016-10-04 18:01:34 -0700180 select SYS_FSL_SRDS_2
Ashish kumar76bd6ce2017-04-07 11:40:32 +0530181 select FSL_TZASC_1
182 select FSL_TZASC_2
Rajesh Bhagat5756f7e2019-01-20 05:30:06 +0000183 select FSL_TZASC_400
184 select FSL_TZPC_BP147
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000185 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
186 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
187 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
York Sun1dc61ca2016-12-28 08:43:41 -0800188 select SYS_FSL_ERRATUM_A008585
Ran Wange64f7472017-09-04 18:46:50 +0800189 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +0800190 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +0800191 select SYS_FSL_ERRATUM_A009008
York Sun1dc61ca2016-12-28 08:43:41 -0800192 select SYS_FSL_ERRATUM_A009635
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000193 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
Ran Wang9e8fabc2017-09-04 18:46:49 +0800194 select SYS_FSL_ERRATUM_A009798
York Sun1dc61ca2016-12-28 08:43:41 -0800195 select SYS_FSL_ERRATUM_A009801
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000196 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
197 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
198 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
Ashish kumar3b52a232017-02-23 16:03:57 +0530199 select SYS_FSL_ERRATUM_A009203
Simon Glass62adede2017-01-23 13:31:19 -0700200 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -0700201 select BOARD_EARLY_INIT_F
Sriram Dash7122a0c2018-02-06 11:26:30 +0530202 select SYS_I2C_MXC
Chuanhua Han3f27fff2019-07-26 19:24:03 +0800203 select SYS_I2C_MXC_I2C1 if !TFABOOT
204 select SYS_I2C_MXC_I2C2 if !TFABOOT
205 select SYS_I2C_MXC_I2C3 if !TFABOOT
206 select SYS_I2C_MXC_I2C4 if !TFABOOT
Hou Zhiqiangce4a92a2020-04-28 10:19:31 +0800207 select RESV_RAM if GIC_V3_ITS
Masahiro Yamada9afc6c52018-04-25 18:47:52 +0900208 imply DISTRO_DEFAULTS
Masahiro Yamadaacede7a2017-12-04 12:37:00 +0900209 imply PANIC_HANG
York Sun4dd8c612016-10-04 14:31:48 -0700210
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530211config ARCH_LX2162A
212 bool
213 select ARMV8_SET_SMPEN
214 select FSL_LSCH3
215 select NXP_LSCH3_2
216 select SYS_HAS_SERDES
217 select SYS_FSL_SRDS_1
218 select SYS_FSL_SRDS_2
219 select SYS_FSL_DDR
220 select SYS_FSL_DDR_LE
221 select SYS_FSL_DDR_VER_50
222 select SYS_FSL_EC1
223 select SYS_FSL_EC2
224 select SYS_FSL_ERRATUM_A050106
225 select SYS_FSL_HAS_RGMII
226 select SYS_FSL_HAS_SEC
227 select SYS_FSL_HAS_CCN508
228 select SYS_FSL_HAS_DDR4
229 select SYS_FSL_SEC_COMPAT_5
230 select SYS_FSL_SEC_LE
231 select ARCH_EARLY_INIT_R
232 select BOARD_EARLY_INIT_F
233 select SYS_I2C_MXC
234 select RESV_RAM if GIC_V3_ITS
235 imply DISTRO_DEFAULTS
236 imply PANIC_HANG
237 imply SCSI
238 imply SCSI_AHCI
239
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000240config ARCH_LX2160A
241 bool
242 select ARMV8_SET_SMPEN
243 select FSL_LSCH3
244 select NXP_LSCH3_2
245 select SYS_HAS_SERDES
246 select SYS_FSL_SRDS_1
247 select SYS_FSL_SRDS_2
248 select SYS_NXP_SRDS_3
249 select SYS_FSL_DDR
250 select SYS_FSL_DDR_LE
251 select SYS_FSL_DDR_VER_50
252 select SYS_FSL_EC1
253 select SYS_FSL_EC2
Ran Wangd0270dc2019-11-26 11:40:40 +0800254 select SYS_FSL_ERRATUM_A050106
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000255 select SYS_FSL_HAS_RGMII
256 select SYS_FSL_HAS_SEC
257 select SYS_FSL_HAS_CCN508
258 select SYS_FSL_HAS_DDR4
259 select SYS_FSL_SEC_COMPAT_5
260 select SYS_FSL_SEC_LE
261 select ARCH_EARLY_INIT_R
262 select BOARD_EARLY_INIT_F
263 select SYS_I2C_MXC
Hou Zhiqiangce4a92a2020-04-28 10:19:31 +0800264 select RESV_RAM if GIC_V3_ITS
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000265 imply DISTRO_DEFAULTS
266 imply PANIC_HANG
267 imply SCSI
268 imply SCSI_AHCI
269
York Sun4dd8c612016-10-04 14:31:48 -0700270config FSL_LSCH2
271 bool
Ashish Kumar11234062017-08-11 11:09:14 +0530272 select SYS_FSL_HAS_CCI400
York Sun92c36e22016-12-28 08:43:30 -0800273 select SYS_FSL_HAS_SEC
274 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -0800275 select SYS_FSL_SEC_BE
York Sun4dd8c612016-10-04 14:31:48 -0700276
277config FSL_LSCH3
Alex Marginean47568ce2020-01-11 01:05:40 +0200278 select ARCH_MISC_INIT
York Sun4dd8c612016-10-04 14:31:48 -0700279 bool
280
Priyanka Jain88c25662018-10-29 09:11:29 +0000281config NXP_LSCH3_2
282 bool
283
York Sun4dd8c612016-10-04 14:31:48 -0700284menu "Layerscape architecture"
285 depends on FSL_LSCH2 || FSL_LSCH3
York Sunfcd0e742016-10-04 14:31:47 -0700286
Rajesh Bhagat52d237a2019-01-25 13:36:26 +0000287config FSL_LAYERSCAPE
288 bool
289
Wenbin Songa8f57a92017-01-17 18:31:15 +0800290config HAS_FEATURE_GIC64K_ALIGN
291 bool
292 default y if ARCH_LS1043A
293
Wenbin Songc6bc7c02017-01-17 18:31:16 +0800294config HAS_FEATURE_ENHANCED_MSI
295 bool
296 default y if ARCH_LS1043A
Wenbin Songa8f57a92017-01-17 18:31:15 +0800297
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800298menu "Layerscape PPA"
299config FSL_LS_PPA
300 bool "FSL Layerscape PPA firmware support"
macro.wave.z@gmail.com01bd3342016-12-08 11:58:22 +0800301 depends on !ARMV8_PSCI
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800302 select ARMV8_SEC_FIRMWARE_SUPPORT
Hou Zhiqiang6be115d2017-01-16 17:31:48 +0800303 select SEC_FIRMWARE_ARMV8_PSCI
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800304 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800305 help
306 The FSL Primary Protected Application (PPA) is a software component
307 which is loaded during boot stage, and then remains resident in RAM
308 and runs in the TrustZone after boot.
309 Say y to enable it.
York Sunf2aaf842017-05-15 08:52:00 -0700310
311config SPL_FSL_LS_PPA
312 bool "FSL Layerscape PPA firmware support for SPL build"
313 depends on !ARMV8_PSCI
314 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
315 select SEC_FIRMWARE_ARMV8_PSCI
316 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
317 help
318 The FSL Primary Protected Application (PPA) is a software component
319 which is loaded during boot stage, and then remains resident in RAM
320 and runs in the TrustZone after boot. This is to load PPA during SPL
321 stage instead of the RAM version of U-Boot. Once PPA is initialized,
322 the rest of U-Boot (including RAM version) runs at EL2.
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800323choice
324 prompt "FSL Layerscape PPA firmware loading-media select"
325 depends on FSL_LS_PPA
Hou Zhiqiangbd6e2cd2017-03-17 16:12:33 +0800326 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
327 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800328 default SYS_LS_PPA_FW_IN_XIP
329
330config SYS_LS_PPA_FW_IN_XIP
331 bool "XIP"
332 help
333 Say Y here if the PPA firmware locate at XIP flash, such
334 as NOR or QSPI flash.
335
Hou Zhiqiangbd6e2cd2017-03-17 16:12:33 +0800336config SYS_LS_PPA_FW_IN_MMC
337 bool "eMMC or SD Card"
338 help
339 Say Y here if the PPA firmware locate at eMMC/SD card.
340
341config SYS_LS_PPA_FW_IN_NAND
342 bool "NAND"
343 help
344 Say Y here if the PPA firmware locate at NAND flash.
345
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800346endchoice
347
Sumit Garg8fddf752017-04-20 05:09:11 +0530348config LS_PPA_ESBC_HDR_SIZE
349 hex "Length of PPA ESBC header"
350 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
351 default 0x2000
352 help
353 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
354 NAND to memory to validate PPA image.
355
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800356endmenu
357
Ran Wange64f7472017-09-04 18:46:50 +0800358config SYS_FSL_ERRATUM_A008997
359 bool "Workaround for USB PHY erratum A008997"
360
Ran Wang3ba69482017-09-04 18:46:51 +0800361config SYS_FSL_ERRATUM_A009007
362 bool
363 help
364 Workaround for USB PHY erratum A009007
365
Ran Wangb358b7b2017-09-04 18:46:48 +0800366config SYS_FSL_ERRATUM_A009008
367 bool "Workaround for USB PHY erratum A009008"
368
Ran Wang9e8fabc2017-09-04 18:46:49 +0800369config SYS_FSL_ERRATUM_A009798
370 bool "Workaround for USB PHY erratum A009798"
371
Ran Wangd0270dc2019-11-26 11:40:40 +0800372config SYS_FSL_ERRATUM_A050106
373 bool "Workaround for USB PHY erratum A050106"
374 help
375 USB3.0 Receiver needs to enable fixed equalization
376 for each of PHY instances in an SOC. This is similar
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530377 to erratum A-009007, but this one is for LX2160A and LX2162A,
Ran Wangd0270dc2019-11-26 11:40:40 +0800378 and the register value is different.
379
York Sun149eb332016-09-26 08:09:27 -0700380config SYS_FSL_ERRATUM_A010315
381 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800382
383config SYS_FSL_ERRATUM_A010539
384 bool "Workaround for PIN MUX erratum A010539"
York Sun4dd8c612016-10-04 14:31:48 -0700385
York Sunf188d222016-10-04 14:45:01 -0700386config MAX_CPUS
387 int "Maximum number of CPUs permitted for Layerscape"
Yuantian Tang4aefa162019-04-10 16:43:33 +0800388 default 2 if ARCH_LS1028A
York Sunf188d222016-10-04 14:45:01 -0700389 default 4 if ARCH_LS1043A
390 default 4 if ARCH_LS1046A
391 default 16 if ARCH_LS2080A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530392 default 8 if ARCH_LS1088A
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000393 default 16 if ARCH_LX2160A
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530394 default 16 if ARCH_LX2162A
York Sunf188d222016-10-04 14:45:01 -0700395 default 1
396 help
397 Set this number to the maximum number of possible CPUs in the SoC.
398 SoCs may have multiple clusters with each cluster may have multiple
399 ports. If some ports are reserved but higher ports are used for
400 cores, count the reserved ports. This will allocate enough memory
401 in spin table to properly handle all cores.
402
Meenakshi Aggarwalbbd33182018-11-30 22:32:11 +0530403config EMC2305
404 bool "Fan controller"
405 help
406 Enable the EMC2305 fan controller for configuration of fan
407 speed.
408
Udit Agarwal22ec2382019-11-07 16:11:32 +0000409config NXP_ESBC
410 bool "NXP_ESBC"
York Sun728e7002016-12-02 09:32:35 -0800411 help
412 Enable Freescale Secure Boot feature
413
Yuan Yao52ae4fd2016-12-01 10:13:52 +0800414config QSPI_AHB_INIT
415 bool "Init the QSPI AHB bus"
416 help
417 The default setting for QSPI AHB bus just support 3bytes addressing.
418 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
419 bus for those flashes to support the full QSPI flash size.
420
Kuldeep Singh34aafb02019-11-21 17:15:17 +0530421config FSPI_AHB_EN_4BYTE
422 bool "Enable 4-byte Fast Read command for AHB mode"
423 default n
424 help
425 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
426 But some FlexSPI flash sizes are up to 64MBytes.
427 This flag enables fast read command for AHB mode and modifies required
428 LUT to support full FlexSPI flash.
429
Ashish Kumar11234062017-08-11 11:09:14 +0530430config SYS_CCI400_OFFSET
431 hex "Offset for CCI400 base"
432 depends on SYS_FSL_HAS_CCI400
Yuantian Tang4aefa162019-04-10 16:43:33 +0800433 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
Ashish Kumar11234062017-08-11 11:09:14 +0530434 default 0x180000 if FSL_LSCH2
435 help
436 Offset for CCI400 base
437 CCI400 base addr = CCSRBAR + CCI400_OFFSET
438
York Sune7310a32016-10-04 14:45:54 -0700439config SYS_FSL_IFC_BANK_COUNT
440 int "Maximum banks of Integrated flash controller"
Ashish Kumarb25faa22017-08-31 16:12:53 +0530441 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
York Sune7310a32016-10-04 14:45:54 -0700442 default 4 if ARCH_LS1043A
443 default 4 if ARCH_LS1046A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530444 default 8 if ARCH_LS2080A || ARCH_LS1088A
York Sune7310a32016-10-04 14:45:54 -0700445
Ashish Kumar11234062017-08-11 11:09:14 +0530446config SYS_FSL_HAS_CCI400
447 bool
448
Ashish Kumar97393d62017-08-18 10:54:36 +0530449config SYS_FSL_HAS_CCN504
450 bool
451
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000452config SYS_FSL_HAS_CCN508
453 bool
454
York Sun0dc9abb2016-10-04 14:46:50 -0700455config SYS_FSL_HAS_DP_DDR
456 bool
457
York Sun6b62ef02016-10-04 18:01:34 -0700458config SYS_FSL_SRDS_1
459 bool
460
461config SYS_FSL_SRDS_2
462 bool
463
Priyanka Jain1a602532018-09-27 10:32:05 +0530464config SYS_NXP_SRDS_3
465 bool
466
York Sun6b62ef02016-10-04 18:01:34 -0700467config SYS_HAS_SERDES
468 bool
469
Ashish kumar76bd6ce2017-04-07 11:40:32 +0530470config FSL_TZASC_1
471 bool
472
473config FSL_TZASC_2
474 bool
475
Rajesh Bhagat5756f7e2019-01-20 05:30:06 +0000476config FSL_TZASC_400
477 bool
478
479config FSL_TZPC_BP147
480 bool
York Sun4dd8c612016-10-04 14:31:48 -0700481endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800482
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800483menu "Layerscape clock tree configuration"
484 depends on FSL_LSCH2 || FSL_LSCH3
485
486config SYS_FSL_CLK
487 bool "Enable clock tree initialization"
488 default y
489
490config CLUSTER_CLK_FREQ
491 int "Reference clock of core cluster"
492 depends on ARCH_LS1012A
493 default 100000000
494 help
495 This number is the reference clock frequency of core PLL.
496 For most platforms, the core PLL and Platform PLL have the same
497 reference clock, but for some platforms, LS1012A for instance,
498 they are provided sepatately.
499
500config SYS_FSL_PCLK_DIV
501 int "Platform clock divider"
Yuantian Tang4aefa162019-04-10 16:43:33 +0800502 default 1 if ARCH_LS1028A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800503 default 1 if ARCH_LS1043A
504 default 1 if ARCH_LS1046A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530505 default 1 if ARCH_LS1088A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800506 default 2
507 help
508 This is the divider that is used to derive Platform clock from
509 Platform PLL, in another word:
510 Platform_clk = Platform_PLL_freq / this_divider
511
512config SYS_FSL_DSPI_CLK_DIV
513 int "DSPI clock divider"
514 default 1 if ARCH_LS1043A
515 default 2
516 help
517 This is the divider that is used to derive DSPI clock from Platform
Hou Zhiqiang0c8fcb62017-07-03 18:37:11 +0800518 clock, in another word DSPI_clk = Platform_clk / this_divider.
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800519
520config SYS_FSL_DUART_CLK_DIV
521 int "DUART clock divider"
522 default 1 if ARCH_LS1043A
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000523 default 4 if ARCH_LX2160A
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530524 default 4 if ARCH_LX2162A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800525 default 2
526 help
527 This is the divider that is used to derive DUART clock from Platform
528 clock, in another word DUART_clk = Platform_clk / this_divider.
529
530config SYS_FSL_I2C_CLK_DIV
531 int "I2C clock divider"
532 default 1 if ARCH_LS1043A
Chuanhua Han44d4d332019-08-02 16:53:53 +0800533 default 4 if ARCH_LS1012A
534 default 4 if ARCH_LS1028A
535 default 8 if ARCH_LX2160A
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530536 default 8 if ARCH_LX2162A
Chuanhua Han44d4d332019-08-02 16:53:53 +0800537 default 8 if ARCH_LS1088A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800538 default 2
539 help
540 This is the divider that is used to derive I2C clock from Platform
541 clock, in another word I2C_clk = Platform_clk / this_divider.
542
543config SYS_FSL_IFC_CLK_DIV
544 int "IFC clock divider"
545 default 1 if ARCH_LS1043A
Chuanhua Han3df89cc2019-08-08 17:04:58 +0800546 default 4 if ARCH_LS1012A
547 default 4 if ARCH_LS1028A
548 default 8 if ARCH_LX2160A
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530549 default 8 if ARCH_LX2162A
Chuanhua Han3df89cc2019-08-08 17:04:58 +0800550 default 8 if ARCH_LS1088A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800551 default 2
552 help
553 This is the divider that is used to derive IFC clock from Platform
554 clock, in another word IFC_clk = Platform_clk / this_divider.
555
556config SYS_FSL_LPUART_CLK_DIV
557 int "LPUART clock divider"
558 default 1 if ARCH_LS1043A
559 default 2
560 help
561 This is the divider that is used to derive LPUART clock from Platform
562 clock, in another word LPUART_clk = Platform_clk / this_divider.
563
564config SYS_FSL_SDHC_CLK_DIV
565 int "SDHC clock divider"
566 default 1 if ARCH_LS1043A
567 default 1 if ARCH_LS1012A
568 default 2
569 help
570 This is the divider that is used to derive SDHC clock from Platform
571 clock, in another word SDHC_clk = Platform_clk / this_divider.
Hou Zhiqiangfef32c62018-04-25 16:28:44 +0800572
573config SYS_FSL_QMAN_CLK_DIV
574 int "QMAN clock divider"
575 default 1 if ARCH_LS1043A
576 default 2
577 help
578 This is the divider that is used to derive QMAN clock from Platform
579 clock, in another word QMAN_clk = Platform_clk / this_divider.
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800580endmenu
581
York Sund6964b32017-03-06 09:02:24 -0800582config RESV_RAM
583 bool
584 help
585 Reserve memory from the top, tracked by gd->arch.resv_ram. This
586 reserved RAM can be used by special driver that resides in memory
587 after U-Boot exits. It's up to implementation to allocate and allow
588 access to this reserved memory. For example, the reserved RAM can
589 be at the high end of physical memory. The reserve RAM may be
590 excluded from memory bank(s) passed to OS, or marked as reserved.
591
Ashish Kumarec455e22017-08-31 16:37:31 +0530592config SYS_FSL_EC1
593 bool
594 help
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000595 Ethernet controller 1, this is connected to
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530596 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
Ashish Kumarec455e22017-08-31 16:37:31 +0530597 Provides DPAA2 capabilities
598
599config SYS_FSL_EC2
600 bool
601 help
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000602 Ethernet controller 2, this is connected to
Meenakshi Aggarwalccb5d5d2020-10-29 19:16:16 +0530603 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
Ashish Kumarec455e22017-08-31 16:37:31 +0530604 Provides DPAA2 capabilities
605
York Sun1dc61ca2016-12-28 08:43:41 -0800606config SYS_FSL_ERRATUM_A008336
607 bool
608
609config SYS_FSL_ERRATUM_A008514
610 bool
611
612config SYS_FSL_ERRATUM_A008585
613 bool
614
615config SYS_FSL_ERRATUM_A008850
616 bool
617
Ashish kumar3b52a232017-02-23 16:03:57 +0530618config SYS_FSL_ERRATUM_A009203
619 bool
620
York Sun1dc61ca2016-12-28 08:43:41 -0800621config SYS_FSL_ERRATUM_A009635
622 bool
623
624config SYS_FSL_ERRATUM_A009660
625 bool
626
Laurentiu Tudor7ea2feb2019-10-18 09:01:56 +0000627config SYS_FSL_ERRATUM_A050382
628 bool
Ashish Kumarec455e22017-08-31 16:37:31 +0530629
630config SYS_FSL_HAS_RGMII
631 bool
632 depends on SYS_FSL_EC1 || SYS_FSL_EC2
633
Philipp Tomsich2d6a0cc2017-08-03 23:23:55 +0200634config SPL_LDSCRIPT
635 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
Ran Wang5959f842017-10-23 10:09:21 +0800636
637config HAS_FSL_XHCI_USB
638 bool
639 default y if ARCH_LS1043A || ARCH_LS1046A
640 help
641 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
642 pins, select it when the pins are assigned to USB.