blob: 116b6b0617b090efbfdb62e9c4e7116fc7b9e833 [file] [log] [blame]
York Sunb3d71642016-09-26 08:09:26 -07001config ARCH_LS1012A
York Sunfcd0e742016-10-04 14:31:47 -07002 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +08003 select ARMV8_SET_SMPEN
Rajesh Bhagatcd786e82018-11-05 18:01:48 +00004 select ARM_ERRATA_855873 if !TFABOOT
Rajesh Bhagat52d237a2019-01-25 13:36:26 +00005 select FSL_LAYERSCAPE
York Sun4dd8c612016-10-04 14:31:48 -07006 select FSL_LSCH2
Sriram Dash4a943332018-01-30 15:58:44 +05307 select SYS_FSL_SRDS_1
8 select SYS_HAS_SERDES
York Sunb6fffd82016-10-04 18:03:08 -07009 select SYS_FSL_DDR_BE
York Sunb3d71642016-09-26 08:09:26 -070010 select SYS_FSL_MMDC
York Sun149eb332016-09-26 08:09:27 -070011 select SYS_FSL_ERRATUM_A010315
Ran Wang02dc77b2017-11-13 16:14:48 +080012 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
Simon Glass62adede2017-01-23 13:31:19 -070016 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070017 select BOARD_EARLY_INIT_F
Sriram Dash7122a0c2018-02-06 11:26:30 +053018 select SYS_I2C_MXC
Biwen Li0a759bb2019-12-31 15:33:41 +080019 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C
Masahiro Yamadaacede7a2017-12-04 12:37:00 +090021 imply PANIC_HANG
York Sun149eb332016-09-26 08:09:27 -070022
Yuantian Tang4aefa162019-04-10 16:43:33 +080023config ARCH_LS1028A
24 bool
25 select ARMV8_SET_SMPEN
Michael Walle66f2a532020-05-10 01:20:11 +020026 select FSL_LAYERSCAPE
Yuantian Tang4aefa162019-04-10 16:43:33 +080027 select FSL_LSCH3
28 select NXP_LSCH3_2
29 select SYS_FSL_HAS_CCI400
30 select SYS_FSL_SRDS_1
31 select SYS_HAS_SERDES
32 select SYS_FSL_DDR
33 select SYS_FSL_DDR_LE
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DDR3
36 select SYS_FSL_HAS_DDR4
37 select SYS_FSL_HAS_SEC
38 select SYS_FSL_SEC_COMPAT_5
39 select SYS_FSL_SEC_LE
40 select FSL_TZASC_1
41 select ARCH_EARLY_INIT_R
42 select BOARD_EARLY_INIT_F
43 select SYS_I2C_MXC
Ran Wange118acb2019-05-14 17:34:56 +080044 select SYS_FSL_ERRATUM_A008997
Yuantian Tang4aefa162019-04-10 16:43:33 +080045 select SYS_FSL_ERRATUM_A009007
46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
Laurentiu Tudor7ea2feb2019-10-18 09:01:56 +000049 select SYS_FSL_ERRATUM_A050382
Hou Zhiqiangce4a92a2020-04-28 10:19:31 +080050 select RESV_RAM if GIC_V3_ITS
Yuantian Tang4aefa162019-04-10 16:43:33 +080051 imply PANIC_HANG
52
York Sun149eb332016-09-26 08:09:27 -070053config ARCH_LS1043A
York Sunfcd0e742016-10-04 14:31:47 -070054 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080055 select ARMV8_SET_SMPEN
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000056 select ARM_ERRATA_855873 if !TFABOOT
Rajesh Bhagat52d237a2019-01-25 13:36:26 +000057 select FSL_LAYERSCAPE
York Sun4dd8c612016-10-04 14:31:48 -070058 select FSL_LSCH2
Sriram Dash4a943332018-01-30 15:58:44 +053059 select SYS_FSL_SRDS_1
60 select SYS_HAS_SERDES
York Sund297d392016-12-28 08:43:40 -080061 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070062 select SYS_FSL_DDR_BE
63 select SYS_FSL_DDR_VER_50
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000064 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
Ran Wange64f7472017-09-04 18:46:50 +080065 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +080066 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +080067 select SYS_FSL_ERRATUM_A009008
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000068 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
69 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
Ran Wang9e8fabc2017-09-04 18:46:49 +080070 select SYS_FSL_ERRATUM_A009798
York Sun1dc61ca2016-12-28 08:43:41 -080071 select SYS_FSL_ERRATUM_A009929
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000072 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
York Sun149eb332016-09-26 08:09:27 -070073 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +080074 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -080075 select SYS_FSL_HAS_DDR3
76 select SYS_FSL_HAS_DDR4
Simon Glass62adede2017-01-23 13:31:19 -070077 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070078 select BOARD_EARLY_INIT_F
Biwen Li014460b2020-02-05 22:02:16 +080079 select SYS_I2C_MXC if !DM_I2C
80 select SYS_I2C_MXC_I2C1 if !DM_I2C
81 select SYS_I2C_MXC_I2C2 if !DM_I2C
82 select SYS_I2C_MXC_I2C3 if !DM_I2C
83 select SYS_I2C_MXC_I2C4 if !DM_I2C
Simon Glassc88a09a2017-08-04 16:34:34 -060084 imply CMD_PCI
York Sunb3d71642016-09-26 08:09:26 -070085
York Sunbad49842016-09-26 08:09:24 -070086config ARCH_LS1046A
York Sunfcd0e742016-10-04 14:31:47 -070087 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080088 select ARMV8_SET_SMPEN
Rajesh Bhagat52d237a2019-01-25 13:36:26 +000089 select FSL_LAYERSCAPE
York Sun4dd8c612016-10-04 14:31:48 -070090 select FSL_LSCH2
Sriram Dash4a943332018-01-30 15:58:44 +053091 select SYS_FSL_SRDS_1
92 select SYS_HAS_SERDES
York Sund297d392016-12-28 08:43:40 -080093 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070094 select SYS_FSL_DDR_BE
York Sunb6fffd82016-10-04 18:03:08 -070095 select SYS_FSL_DDR_VER_50
Rajesh Bhagatcd786e82018-11-05 18:01:48 +000096 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
97 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
98 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
Ran Wange64f7472017-09-04 18:46:50 +080099 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +0800100 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +0800101 select SYS_FSL_ERRATUM_A009008
Ran Wang9e8fabc2017-09-04 18:46:49 +0800102 select SYS_FSL_ERRATUM_A009798
York Sun1dc61ca2016-12-28 08:43:41 -0800103 select SYS_FSL_ERRATUM_A009801
Rajesh Bhagatcd786e82018-11-05 18:01:48 +0000104 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
105 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
106 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800107 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -0800108 select SYS_FSL_HAS_DDR4
York Sun6b62ef02016-10-04 18:01:34 -0700109 select SYS_FSL_SRDS_2
Simon Glass62adede2017-01-23 13:31:19 -0700110 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -0700111 select BOARD_EARLY_INIT_F
Biwen Lif0018f52020-02-05 22:02:17 +0800112 select SYS_I2C_MXC if !DM_I2C
113 select SYS_I2C_MXC_I2C1 if !DM_I2C
114 select SYS_I2C_MXC_I2C2 if !DM_I2C
115 select SYS_I2C_MXC_I2C3 if !DM_I2C
116 select SYS_I2C_MXC_I2C4 if !DM_I2C
Simon Glass0e5faf02017-06-14 21:28:21 -0600117 imply SCSI
Tuomas Tynkkynenedf9f622017-12-08 15:36:19 +0200118 imply SCSI_AHCI
York Sunb3d71642016-09-26 08:09:26 -0700119
Ashish Kumarb25faa22017-08-31 16:12:53 +0530120config ARCH_LS1088A
121 bool
122 select ARMV8_SET_SMPEN
Pankit Gargf5c2a832018-12-27 04:37:55 +0000123 select ARM_ERRATA_855873 if !TFABOOT
Rajesh Bhagat52d237a2019-01-25 13:36:26 +0000124 select FSL_LAYERSCAPE
Ashish Kumarb25faa22017-08-31 16:12:53 +0530125 select FSL_LSCH3
Sriram Dash4a943332018-01-30 15:58:44 +0530126 select SYS_FSL_SRDS_1
127 select SYS_HAS_SERDES
Ashish Kumarb25faa22017-08-31 16:12:53 +0530128 select SYS_FSL_DDR
129 select SYS_FSL_DDR_LE
130 select SYS_FSL_DDR_VER_50
Ashish Kumarec455e22017-08-31 16:37:31 +0530131 select SYS_FSL_EC1
132 select SYS_FSL_EC2
Pankit Gargf5c2a832018-12-27 04:37:55 +0000133 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
134 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
135 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
136 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
137 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
Ran Wangef277072017-09-22 15:21:34 +0800138 select SYS_FSL_ERRATUM_A009007
Ashish Kumarb25faa22017-08-31 16:12:53 +0530139 select SYS_FSL_HAS_CCI400
140 select SYS_FSL_HAS_DDR4
Ashish Kumarec455e22017-08-31 16:37:31 +0530141 select SYS_FSL_HAS_RGMII
Ashish Kumarb25faa22017-08-31 16:12:53 +0530142 select SYS_FSL_HAS_SEC
143 select SYS_FSL_SEC_COMPAT_5
144 select SYS_FSL_SEC_LE
145 select SYS_FSL_SRDS_1
146 select SYS_FSL_SRDS_2
147 select FSL_TZASC_1
Rajesh Bhagat5756f7e2019-01-20 05:30:06 +0000148 select FSL_TZASC_400
149 select FSL_TZPC_BP147
Ashish Kumarb25faa22017-08-31 16:12:53 +0530150 select ARCH_EARLY_INIT_R
151 select BOARD_EARLY_INIT_F
Sriram Dash7122a0c2018-02-06 11:26:30 +0530152 select SYS_I2C_MXC
Chuanhua Han98a5e402019-07-26 20:25:37 +0800153 select SYS_I2C_MXC_I2C1 if !TFABOOT
154 select SYS_I2C_MXC_I2C2 if !TFABOOT
155 select SYS_I2C_MXC_I2C3 if !TFABOOT
156 select SYS_I2C_MXC_I2C4 if !TFABOOT
Hou Zhiqiangce4a92a2020-04-28 10:19:31 +0800157 select RESV_RAM if GIC_V3_ITS
Ashish Kumara179e562017-11-02 09:50:47 +0530158 imply SCSI
Masahiro Yamadaacede7a2017-12-04 12:37:00 +0900159 imply PANIC_HANG
Ashish Kumarb25faa22017-08-31 16:12:53 +0530160
York Sunfcd0e742016-10-04 14:31:47 -0700161config ARCH_LS2080A
162 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +0800163 select ARMV8_SET_SMPEN
Tom Rinibacb52c2017-03-07 07:13:42 -0500164 select ARM_ERRATA_826974
165 select ARM_ERRATA_828024
166 select ARM_ERRATA_829520
167 select ARM_ERRATA_833471
Rajesh Bhagat52d237a2019-01-25 13:36:26 +0000168 select FSL_LAYERSCAPE
York Sun4dd8c612016-10-04 14:31:48 -0700169 select FSL_LSCH3
Sriram Dash4a943332018-01-30 15:58:44 +0530170 select SYS_FSL_SRDS_1
171 select SYS_HAS_SERDES
York Sund297d392016-12-28 08:43:40 -0800172 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -0700173 select SYS_FSL_DDR_LE
174 select SYS_FSL_DDR_VER_50
Ashish Kumar97393d62017-08-18 10:54:36 +0530175 select SYS_FSL_HAS_CCN504
York Sun6b62ef02016-10-04 18:01:34 -0700176 select SYS_FSL_HAS_DP_DDR
York Sun92c36e22016-12-28 08:43:30 -0800177 select SYS_FSL_HAS_SEC
York Sund297d392016-12-28 08:43:40 -0800178 select SYS_FSL_HAS_DDR4
York Sun92c36e22016-12-28 08:43:30 -0800179 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -0800180 select SYS_FSL_SEC_LE
York Sun6b62ef02016-10-04 18:01:34 -0700181 select SYS_FSL_SRDS_2
Ashish kumar76bd6ce2017-04-07 11:40:32 +0530182 select FSL_TZASC_1
183 select FSL_TZASC_2
Rajesh Bhagat5756f7e2019-01-20 05:30:06 +0000184 select FSL_TZASC_400
185 select FSL_TZPC_BP147
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000186 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
187 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
188 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
York Sun1dc61ca2016-12-28 08:43:41 -0800189 select SYS_FSL_ERRATUM_A008585
Ran Wange64f7472017-09-04 18:46:50 +0800190 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +0800191 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +0800192 select SYS_FSL_ERRATUM_A009008
York Sun1dc61ca2016-12-28 08:43:41 -0800193 select SYS_FSL_ERRATUM_A009635
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000194 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
Ran Wang9e8fabc2017-09-04 18:46:49 +0800195 select SYS_FSL_ERRATUM_A009798
York Sun1dc61ca2016-12-28 08:43:41 -0800196 select SYS_FSL_ERRATUM_A009801
Rajesh Bhagatd5691be2018-12-27 04:37:59 +0000197 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
198 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
199 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
Ashish kumar3b52a232017-02-23 16:03:57 +0530200 select SYS_FSL_ERRATUM_A009203
Simon Glass62adede2017-01-23 13:31:19 -0700201 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -0700202 select BOARD_EARLY_INIT_F
Sriram Dash7122a0c2018-02-06 11:26:30 +0530203 select SYS_I2C_MXC
Chuanhua Han3f27fff2019-07-26 19:24:03 +0800204 select SYS_I2C_MXC_I2C1 if !TFABOOT
205 select SYS_I2C_MXC_I2C2 if !TFABOOT
206 select SYS_I2C_MXC_I2C3 if !TFABOOT
207 select SYS_I2C_MXC_I2C4 if !TFABOOT
Hou Zhiqiangce4a92a2020-04-28 10:19:31 +0800208 select RESV_RAM if GIC_V3_ITS
Masahiro Yamada9afc6c52018-04-25 18:47:52 +0900209 imply DISTRO_DEFAULTS
Masahiro Yamadaacede7a2017-12-04 12:37:00 +0900210 imply PANIC_HANG
York Sun4dd8c612016-10-04 14:31:48 -0700211
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000212config ARCH_LX2160A
213 bool
214 select ARMV8_SET_SMPEN
215 select FSL_LSCH3
216 select NXP_LSCH3_2
217 select SYS_HAS_SERDES
218 select SYS_FSL_SRDS_1
219 select SYS_FSL_SRDS_2
220 select SYS_NXP_SRDS_3
221 select SYS_FSL_DDR
222 select SYS_FSL_DDR_LE
223 select SYS_FSL_DDR_VER_50
224 select SYS_FSL_EC1
225 select SYS_FSL_EC2
Ran Wangd0270dc2019-11-26 11:40:40 +0800226 select SYS_FSL_ERRATUM_A050106
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000227 select SYS_FSL_HAS_RGMII
228 select SYS_FSL_HAS_SEC
229 select SYS_FSL_HAS_CCN508
230 select SYS_FSL_HAS_DDR4
231 select SYS_FSL_SEC_COMPAT_5
232 select SYS_FSL_SEC_LE
233 select ARCH_EARLY_INIT_R
234 select BOARD_EARLY_INIT_F
235 select SYS_I2C_MXC
Hou Zhiqiangce4a92a2020-04-28 10:19:31 +0800236 select RESV_RAM if GIC_V3_ITS
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000237 imply DISTRO_DEFAULTS
238 imply PANIC_HANG
239 imply SCSI
240 imply SCSI_AHCI
241
York Sun4dd8c612016-10-04 14:31:48 -0700242config FSL_LSCH2
243 bool
Ashish Kumar11234062017-08-11 11:09:14 +0530244 select SYS_FSL_HAS_CCI400
York Sun92c36e22016-12-28 08:43:30 -0800245 select SYS_FSL_HAS_SEC
246 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -0800247 select SYS_FSL_SEC_BE
York Sun4dd8c612016-10-04 14:31:48 -0700248
249config FSL_LSCH3
Alex Marginean47568ce2020-01-11 01:05:40 +0200250 select ARCH_MISC_INIT
York Sun4dd8c612016-10-04 14:31:48 -0700251 bool
252
Priyanka Jain88c25662018-10-29 09:11:29 +0000253config NXP_LSCH3_2
254 bool
255
York Sun4dd8c612016-10-04 14:31:48 -0700256menu "Layerscape architecture"
257 depends on FSL_LSCH2 || FSL_LSCH3
York Sunfcd0e742016-10-04 14:31:47 -0700258
Rajesh Bhagat52d237a2019-01-25 13:36:26 +0000259config FSL_LAYERSCAPE
260 bool
261
Wenbin Songa8f57a92017-01-17 18:31:15 +0800262config HAS_FEATURE_GIC64K_ALIGN
263 bool
264 default y if ARCH_LS1043A
265
Wenbin Songc6bc7c02017-01-17 18:31:16 +0800266config HAS_FEATURE_ENHANCED_MSI
267 bool
268 default y if ARCH_LS1043A
Wenbin Songa8f57a92017-01-17 18:31:15 +0800269
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800270menu "Layerscape PPA"
271config FSL_LS_PPA
272 bool "FSL Layerscape PPA firmware support"
macro.wave.z@gmail.com01bd3342016-12-08 11:58:22 +0800273 depends on !ARMV8_PSCI
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800274 select ARMV8_SEC_FIRMWARE_SUPPORT
Hou Zhiqiang6be115d2017-01-16 17:31:48 +0800275 select SEC_FIRMWARE_ARMV8_PSCI
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800276 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800277 help
278 The FSL Primary Protected Application (PPA) is a software component
279 which is loaded during boot stage, and then remains resident in RAM
280 and runs in the TrustZone after boot.
281 Say y to enable it.
York Sunf2aaf842017-05-15 08:52:00 -0700282
283config SPL_FSL_LS_PPA
284 bool "FSL Layerscape PPA firmware support for SPL build"
285 depends on !ARMV8_PSCI
286 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
287 select SEC_FIRMWARE_ARMV8_PSCI
288 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
289 help
290 The FSL Primary Protected Application (PPA) is a software component
291 which is loaded during boot stage, and then remains resident in RAM
292 and runs in the TrustZone after boot. This is to load PPA during SPL
293 stage instead of the RAM version of U-Boot. Once PPA is initialized,
294 the rest of U-Boot (including RAM version) runs at EL2.
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800295choice
296 prompt "FSL Layerscape PPA firmware loading-media select"
297 depends on FSL_LS_PPA
Hou Zhiqiangbd6e2cd2017-03-17 16:12:33 +0800298 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
299 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800300 default SYS_LS_PPA_FW_IN_XIP
301
302config SYS_LS_PPA_FW_IN_XIP
303 bool "XIP"
304 help
305 Say Y here if the PPA firmware locate at XIP flash, such
306 as NOR or QSPI flash.
307
Hou Zhiqiangbd6e2cd2017-03-17 16:12:33 +0800308config SYS_LS_PPA_FW_IN_MMC
309 bool "eMMC or SD Card"
310 help
311 Say Y here if the PPA firmware locate at eMMC/SD card.
312
313config SYS_LS_PPA_FW_IN_NAND
314 bool "NAND"
315 help
316 Say Y here if the PPA firmware locate at NAND flash.
317
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800318endchoice
319
Sumit Garg8fddf752017-04-20 05:09:11 +0530320config LS_PPA_ESBC_HDR_SIZE
321 hex "Length of PPA ESBC header"
322 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
323 default 0x2000
324 help
325 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
326 NAND to memory to validate PPA image.
327
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800328endmenu
329
Ran Wange64f7472017-09-04 18:46:50 +0800330config SYS_FSL_ERRATUM_A008997
331 bool "Workaround for USB PHY erratum A008997"
332
Ran Wang3ba69482017-09-04 18:46:51 +0800333config SYS_FSL_ERRATUM_A009007
334 bool
335 help
336 Workaround for USB PHY erratum A009007
337
Ran Wangb358b7b2017-09-04 18:46:48 +0800338config SYS_FSL_ERRATUM_A009008
339 bool "Workaround for USB PHY erratum A009008"
340
Ran Wang9e8fabc2017-09-04 18:46:49 +0800341config SYS_FSL_ERRATUM_A009798
342 bool "Workaround for USB PHY erratum A009798"
343
Ran Wangd0270dc2019-11-26 11:40:40 +0800344config SYS_FSL_ERRATUM_A050106
345 bool "Workaround for USB PHY erratum A050106"
346 help
347 USB3.0 Receiver needs to enable fixed equalization
348 for each of PHY instances in an SOC. This is similar
349 to erratum A-009007, but this one is for LX2160A,
350 and the register value is different.
351
York Sun149eb332016-09-26 08:09:27 -0700352config SYS_FSL_ERRATUM_A010315
353 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800354
355config SYS_FSL_ERRATUM_A010539
356 bool "Workaround for PIN MUX erratum A010539"
York Sun4dd8c612016-10-04 14:31:48 -0700357
York Sunf188d222016-10-04 14:45:01 -0700358config MAX_CPUS
359 int "Maximum number of CPUs permitted for Layerscape"
Yuantian Tang4aefa162019-04-10 16:43:33 +0800360 default 2 if ARCH_LS1028A
York Sunf188d222016-10-04 14:45:01 -0700361 default 4 if ARCH_LS1043A
362 default 4 if ARCH_LS1046A
363 default 16 if ARCH_LS2080A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530364 default 8 if ARCH_LS1088A
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000365 default 16 if ARCH_LX2160A
York Sunf188d222016-10-04 14:45:01 -0700366 default 1
367 help
368 Set this number to the maximum number of possible CPUs in the SoC.
369 SoCs may have multiple clusters with each cluster may have multiple
370 ports. If some ports are reserved but higher ports are used for
371 cores, count the reserved ports. This will allocate enough memory
372 in spin table to properly handle all cores.
373
Meenakshi Aggarwalbbd33182018-11-30 22:32:11 +0530374config EMC2305
375 bool "Fan controller"
376 help
377 Enable the EMC2305 fan controller for configuration of fan
378 speed.
379
Udit Agarwal22ec2382019-11-07 16:11:32 +0000380config NXP_ESBC
381 bool "NXP_ESBC"
York Sun728e7002016-12-02 09:32:35 -0800382 help
383 Enable Freescale Secure Boot feature
384
Yuan Yao52ae4fd2016-12-01 10:13:52 +0800385config QSPI_AHB_INIT
386 bool "Init the QSPI AHB bus"
387 help
388 The default setting for QSPI AHB bus just support 3bytes addressing.
389 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
390 bus for those flashes to support the full QSPI flash size.
391
Kuldeep Singh34aafb02019-11-21 17:15:17 +0530392config FSPI_AHB_EN_4BYTE
393 bool "Enable 4-byte Fast Read command for AHB mode"
394 default n
395 help
396 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
397 But some FlexSPI flash sizes are up to 64MBytes.
398 This flag enables fast read command for AHB mode and modifies required
399 LUT to support full FlexSPI flash.
400
Ashish Kumar11234062017-08-11 11:09:14 +0530401config SYS_CCI400_OFFSET
402 hex "Offset for CCI400 base"
403 depends on SYS_FSL_HAS_CCI400
Yuantian Tang4aefa162019-04-10 16:43:33 +0800404 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
Ashish Kumar11234062017-08-11 11:09:14 +0530405 default 0x180000 if FSL_LSCH2
406 help
407 Offset for CCI400 base
408 CCI400 base addr = CCSRBAR + CCI400_OFFSET
409
York Sune7310a32016-10-04 14:45:54 -0700410config SYS_FSL_IFC_BANK_COUNT
411 int "Maximum banks of Integrated flash controller"
Ashish Kumarb25faa22017-08-31 16:12:53 +0530412 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
York Sune7310a32016-10-04 14:45:54 -0700413 default 4 if ARCH_LS1043A
414 default 4 if ARCH_LS1046A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530415 default 8 if ARCH_LS2080A || ARCH_LS1088A
York Sune7310a32016-10-04 14:45:54 -0700416
Ashish Kumar11234062017-08-11 11:09:14 +0530417config SYS_FSL_HAS_CCI400
418 bool
419
Ashish Kumar97393d62017-08-18 10:54:36 +0530420config SYS_FSL_HAS_CCN504
421 bool
422
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000423config SYS_FSL_HAS_CCN508
424 bool
425
York Sun0dc9abb2016-10-04 14:46:50 -0700426config SYS_FSL_HAS_DP_DDR
427 bool
428
York Sun6b62ef02016-10-04 18:01:34 -0700429config SYS_FSL_SRDS_1
430 bool
431
432config SYS_FSL_SRDS_2
433 bool
434
Priyanka Jain1a602532018-09-27 10:32:05 +0530435config SYS_NXP_SRDS_3
436 bool
437
York Sun6b62ef02016-10-04 18:01:34 -0700438config SYS_HAS_SERDES
439 bool
440
Ashish kumar76bd6ce2017-04-07 11:40:32 +0530441config FSL_TZASC_1
442 bool
443
444config FSL_TZASC_2
445 bool
446
Rajesh Bhagat5756f7e2019-01-20 05:30:06 +0000447config FSL_TZASC_400
448 bool
449
450config FSL_TZPC_BP147
451 bool
York Sun4dd8c612016-10-04 14:31:48 -0700452endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800453
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800454menu "Layerscape clock tree configuration"
455 depends on FSL_LSCH2 || FSL_LSCH3
456
457config SYS_FSL_CLK
458 bool "Enable clock tree initialization"
459 default y
460
461config CLUSTER_CLK_FREQ
462 int "Reference clock of core cluster"
463 depends on ARCH_LS1012A
464 default 100000000
465 help
466 This number is the reference clock frequency of core PLL.
467 For most platforms, the core PLL and Platform PLL have the same
468 reference clock, but for some platforms, LS1012A for instance,
469 they are provided sepatately.
470
471config SYS_FSL_PCLK_DIV
472 int "Platform clock divider"
Yuantian Tang4aefa162019-04-10 16:43:33 +0800473 default 1 if ARCH_LS1028A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800474 default 1 if ARCH_LS1043A
475 default 1 if ARCH_LS1046A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530476 default 1 if ARCH_LS1088A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800477 default 2
478 help
479 This is the divider that is used to derive Platform clock from
480 Platform PLL, in another word:
481 Platform_clk = Platform_PLL_freq / this_divider
482
483config SYS_FSL_DSPI_CLK_DIV
484 int "DSPI clock divider"
485 default 1 if ARCH_LS1043A
486 default 2
487 help
488 This is the divider that is used to derive DSPI clock from Platform
Hou Zhiqiang0c8fcb62017-07-03 18:37:11 +0800489 clock, in another word DSPI_clk = Platform_clk / this_divider.
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800490
491config SYS_FSL_DUART_CLK_DIV
492 int "DUART clock divider"
493 default 1 if ARCH_LS1043A
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000494 default 4 if ARCH_LX2160A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800495 default 2
496 help
497 This is the divider that is used to derive DUART clock from Platform
498 clock, in another word DUART_clk = Platform_clk / this_divider.
499
500config SYS_FSL_I2C_CLK_DIV
501 int "I2C clock divider"
502 default 1 if ARCH_LS1043A
Chuanhua Han44d4d332019-08-02 16:53:53 +0800503 default 4 if ARCH_LS1012A
504 default 4 if ARCH_LS1028A
505 default 8 if ARCH_LX2160A
506 default 8 if ARCH_LS1088A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800507 default 2
508 help
509 This is the divider that is used to derive I2C clock from Platform
510 clock, in another word I2C_clk = Platform_clk / this_divider.
511
512config SYS_FSL_IFC_CLK_DIV
513 int "IFC clock divider"
514 default 1 if ARCH_LS1043A
Chuanhua Han3df89cc2019-08-08 17:04:58 +0800515 default 4 if ARCH_LS1012A
516 default 4 if ARCH_LS1028A
517 default 8 if ARCH_LX2160A
518 default 8 if ARCH_LS1088A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800519 default 2
520 help
521 This is the divider that is used to derive IFC clock from Platform
522 clock, in another word IFC_clk = Platform_clk / this_divider.
523
524config SYS_FSL_LPUART_CLK_DIV
525 int "LPUART clock divider"
526 default 1 if ARCH_LS1043A
527 default 2
528 help
529 This is the divider that is used to derive LPUART clock from Platform
530 clock, in another word LPUART_clk = Platform_clk / this_divider.
531
532config SYS_FSL_SDHC_CLK_DIV
533 int "SDHC clock divider"
534 default 1 if ARCH_LS1043A
535 default 1 if ARCH_LS1012A
536 default 2
537 help
538 This is the divider that is used to derive SDHC clock from Platform
539 clock, in another word SDHC_clk = Platform_clk / this_divider.
Hou Zhiqiangfef32c62018-04-25 16:28:44 +0800540
541config SYS_FSL_QMAN_CLK_DIV
542 int "QMAN clock divider"
543 default 1 if ARCH_LS1043A
544 default 2
545 help
546 This is the divider that is used to derive QMAN clock from Platform
547 clock, in another word QMAN_clk = Platform_clk / this_divider.
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800548endmenu
549
York Sund6964b32017-03-06 09:02:24 -0800550config RESV_RAM
551 bool
552 help
553 Reserve memory from the top, tracked by gd->arch.resv_ram. This
554 reserved RAM can be used by special driver that resides in memory
555 after U-Boot exits. It's up to implementation to allocate and allow
556 access to this reserved memory. For example, the reserved RAM can
557 be at the high end of physical memory. The reserve RAM may be
558 excluded from memory bank(s) passed to OS, or marked as reserved.
559
Ashish Kumarec455e22017-08-31 16:37:31 +0530560config SYS_FSL_EC1
561 bool
562 help
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000563 Ethernet controller 1, this is connected to
564 MAC17 for LX2160A or to MAC3 for other SoCs
Ashish Kumarec455e22017-08-31 16:37:31 +0530565 Provides DPAA2 capabilities
566
567config SYS_FSL_EC2
568 bool
569 help
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000570 Ethernet controller 2, this is connected to
571 MAC18 for LX2160A or to MAC4 for other SoCs
Ashish Kumarec455e22017-08-31 16:37:31 +0530572 Provides DPAA2 capabilities
573
York Sun1dc61ca2016-12-28 08:43:41 -0800574config SYS_FSL_ERRATUM_A008336
575 bool
576
577config SYS_FSL_ERRATUM_A008514
578 bool
579
580config SYS_FSL_ERRATUM_A008585
581 bool
582
583config SYS_FSL_ERRATUM_A008850
584 bool
585
Ashish kumar3b52a232017-02-23 16:03:57 +0530586config SYS_FSL_ERRATUM_A009203
587 bool
588
York Sun1dc61ca2016-12-28 08:43:41 -0800589config SYS_FSL_ERRATUM_A009635
590 bool
591
592config SYS_FSL_ERRATUM_A009660
593 bool
594
595config SYS_FSL_ERRATUM_A009929
596 bool
York Sun1a770752017-03-06 09:02:26 -0800597
Laurentiu Tudor7ea2feb2019-10-18 09:01:56 +0000598config SYS_FSL_ERRATUM_A050382
599 bool
Ashish Kumarec455e22017-08-31 16:37:31 +0530600
601config SYS_FSL_HAS_RGMII
602 bool
603 depends on SYS_FSL_EC1 || SYS_FSL_EC2
604
Philipp Tomsich2d6a0cc2017-08-03 23:23:55 +0200605config SPL_LDSCRIPT
606 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
Ran Wang5959f842017-10-23 10:09:21 +0800607
608config HAS_FSL_XHCI_USB
609 bool
610 default y if ARCH_LS1043A || ARCH_LS1046A
611 help
612 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
613 pins, select it when the pins are assigned to USB.