York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 1 | config ARCH_LS1012A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 2 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 3 | select ARMV8_SET_SMPEN |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 4 | select FSL_LSCH2 |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 5 | select SYS_FSL_DDR_BE |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 6 | select SYS_FSL_MMDC |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 7 | select SYS_FSL_ERRATUM_A010315 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 8 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 9 | select BOARD_EARLY_INIT_F |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 10 | |
| 11 | config ARCH_LS1043A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 12 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 13 | select ARMV8_SET_SMPEN |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 14 | select FSL_LSCH2 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 15 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 16 | select SYS_FSL_DDR_BE |
| 17 | select SYS_FSL_DDR_VER_50 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 18 | select SYS_FSL_ERRATUM_A008850 |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 19 | select SYS_FSL_ERRATUM_A009008 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 20 | select SYS_FSL_ERRATUM_A009660 |
| 21 | select SYS_FSL_ERRATUM_A009663 |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame^] | 22 | select SYS_FSL_ERRATUM_A009798 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 23 | select SYS_FSL_ERRATUM_A009929 |
| 24 | select SYS_FSL_ERRATUM_A009942 |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 25 | select SYS_FSL_ERRATUM_A010315 |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 26 | select SYS_FSL_ERRATUM_A010539 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 27 | select SYS_FSL_HAS_DDR3 |
| 28 | select SYS_FSL_HAS_DDR4 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 29 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 30 | select BOARD_EARLY_INIT_F |
Simon Glass | 0e5faf0 | 2017-06-14 21:28:21 -0600 | [diff] [blame] | 31 | imply SCSI |
Simon Glass | c88a09a | 2017-08-04 16:34:34 -0600 | [diff] [blame] | 32 | imply CMD_PCI |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 33 | |
York Sun | bad4984 | 2016-09-26 08:09:24 -0700 | [diff] [blame] | 34 | config ARCH_LS1046A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 35 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 36 | select ARMV8_SET_SMPEN |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 37 | select FSL_LSCH2 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 38 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 39 | select SYS_FSL_DDR_BE |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 40 | select SYS_FSL_DDR_VER_50 |
York Sun | f195cf7 | 2017-01-27 09:57:31 -0800 | [diff] [blame] | 41 | select SYS_FSL_ERRATUM_A008336 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 42 | select SYS_FSL_ERRATUM_A008511 |
Shengzhou Liu | a7c37c6 | 2017-03-23 18:14:40 +0800 | [diff] [blame] | 43 | select SYS_FSL_ERRATUM_A008850 |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 44 | select SYS_FSL_ERRATUM_A009008 |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame^] | 45 | select SYS_FSL_ERRATUM_A009798 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 46 | select SYS_FSL_ERRATUM_A009801 |
| 47 | select SYS_FSL_ERRATUM_A009803 |
| 48 | select SYS_FSL_ERRATUM_A009942 |
| 49 | select SYS_FSL_ERRATUM_A010165 |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 50 | select SYS_FSL_ERRATUM_A010539 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 51 | select SYS_FSL_HAS_DDR4 |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 52 | select SYS_FSL_SRDS_2 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 53 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 54 | select BOARD_EARLY_INIT_F |
Simon Glass | 0e5faf0 | 2017-06-14 21:28:21 -0600 | [diff] [blame] | 55 | imply SCSI |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 56 | |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 57 | config ARCH_LS1088A |
| 58 | bool |
| 59 | select ARMV8_SET_SMPEN |
| 60 | select FSL_LSCH3 |
| 61 | select SYS_FSL_DDR |
| 62 | select SYS_FSL_DDR_LE |
| 63 | select SYS_FSL_DDR_VER_50 |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 64 | select SYS_FSL_EC1 |
| 65 | select SYS_FSL_EC2 |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 66 | select SYS_FSL_ERRATUM_A009803 |
| 67 | select SYS_FSL_ERRATUM_A009942 |
| 68 | select SYS_FSL_ERRATUM_A010165 |
| 69 | select SYS_FSL_ERRATUM_A008511 |
| 70 | select SYS_FSL_ERRATUM_A008850 |
| 71 | select SYS_FSL_HAS_CCI400 |
| 72 | select SYS_FSL_HAS_DDR4 |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 73 | select SYS_FSL_HAS_RGMII |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 74 | select SYS_FSL_HAS_SEC |
| 75 | select SYS_FSL_SEC_COMPAT_5 |
| 76 | select SYS_FSL_SEC_LE |
| 77 | select SYS_FSL_SRDS_1 |
| 78 | select SYS_FSL_SRDS_2 |
| 79 | select FSL_TZASC_1 |
| 80 | select ARCH_EARLY_INIT_R |
| 81 | select BOARD_EARLY_INIT_F |
| 82 | |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 83 | config ARCH_LS2080A |
| 84 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 85 | select ARMV8_SET_SMPEN |
Tom Rini | bacb52c | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 86 | select ARM_ERRATA_826974 |
| 87 | select ARM_ERRATA_828024 |
| 88 | select ARM_ERRATA_829520 |
| 89 | select ARM_ERRATA_833471 |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 90 | select FSL_LSCH3 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 91 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 92 | select SYS_FSL_DDR_LE |
| 93 | select SYS_FSL_DDR_VER_50 |
Ashish Kumar | 97393d6 | 2017-08-18 10:54:36 +0530 | [diff] [blame] | 94 | select SYS_FSL_HAS_CCN504 |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 95 | select SYS_FSL_HAS_DP_DDR |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 96 | select SYS_FSL_HAS_SEC |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 97 | select SYS_FSL_HAS_DDR4 |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 98 | select SYS_FSL_SEC_COMPAT_5 |
York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 99 | select SYS_FSL_SEC_LE |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 100 | select SYS_FSL_SRDS_2 |
Ashish kumar | 76bd6ce | 2017-04-07 11:40:32 +0530 | [diff] [blame] | 101 | select FSL_TZASC_1 |
| 102 | select FSL_TZASC_2 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 103 | select SYS_FSL_ERRATUM_A008336 |
| 104 | select SYS_FSL_ERRATUM_A008511 |
| 105 | select SYS_FSL_ERRATUM_A008514 |
| 106 | select SYS_FSL_ERRATUM_A008585 |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 107 | select SYS_FSL_ERRATUM_A009008 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 108 | select SYS_FSL_ERRATUM_A009635 |
| 109 | select SYS_FSL_ERRATUM_A009663 |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame^] | 110 | select SYS_FSL_ERRATUM_A009798 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 111 | select SYS_FSL_ERRATUM_A009801 |
| 112 | select SYS_FSL_ERRATUM_A009803 |
| 113 | select SYS_FSL_ERRATUM_A009942 |
| 114 | select SYS_FSL_ERRATUM_A010165 |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 115 | select SYS_FSL_ERRATUM_A009203 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 116 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 117 | select BOARD_EARLY_INIT_F |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 118 | |
| 119 | config FSL_LSCH2 |
| 120 | bool |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 121 | select SYS_FSL_HAS_CCI400 |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 122 | select SYS_FSL_HAS_SEC |
| 123 | select SYS_FSL_SEC_COMPAT_5 |
York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 124 | select SYS_FSL_SEC_BE |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 125 | select SYS_FSL_SRDS_1 |
| 126 | select SYS_HAS_SERDES |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 127 | |
| 128 | config FSL_LSCH3 |
| 129 | bool |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 130 | select SYS_FSL_SRDS_1 |
| 131 | select SYS_HAS_SERDES |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 132 | |
York Sun | 6c08974 | 2017-03-06 09:02:25 -0800 | [diff] [blame] | 133 | config FSL_MC_ENET |
| 134 | bool "Management Complex network" |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 135 | depends on ARCH_LS2080A || ARCH_LS1088A |
York Sun | 6c08974 | 2017-03-06 09:02:25 -0800 | [diff] [blame] | 136 | default y |
| 137 | select RESV_RAM |
| 138 | help |
| 139 | Enable Management Complex (MC) network |
| 140 | |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 141 | menu "Layerscape architecture" |
| 142 | depends on FSL_LSCH2 || FSL_LSCH3 |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 143 | |
Hou Zhiqiang | d553bf2 | 2016-12-13 14:54:24 +0800 | [diff] [blame] | 144 | config FSL_PCIE_COMPAT |
| 145 | string "PCIe compatible of Kernel DT" |
| 146 | depends on PCIE_LAYERSCAPE |
| 147 | default "fsl,ls1012a-pcie" if ARCH_LS1012A |
| 148 | default "fsl,ls1043a-pcie" if ARCH_LS1043A |
| 149 | default "fsl,ls1046a-pcie" if ARCH_LS1046A |
| 150 | default "fsl,ls2080a-pcie" if ARCH_LS2080A |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 151 | default "fsl,ls1088a-pcie" if ARCH_LS1088A |
Hou Zhiqiang | d553bf2 | 2016-12-13 14:54:24 +0800 | [diff] [blame] | 152 | help |
| 153 | This compatible is used to find pci controller node in Kernel DT |
| 154 | to complete fixup. |
| 155 | |
Wenbin Song | a8f57a9 | 2017-01-17 18:31:15 +0800 | [diff] [blame] | 156 | config HAS_FEATURE_GIC64K_ALIGN |
| 157 | bool |
| 158 | default y if ARCH_LS1043A |
| 159 | |
Wenbin Song | c6bc7c0 | 2017-01-17 18:31:16 +0800 | [diff] [blame] | 160 | config HAS_FEATURE_ENHANCED_MSI |
| 161 | bool |
| 162 | default y if ARCH_LS1043A |
Wenbin Song | a8f57a9 | 2017-01-17 18:31:15 +0800 | [diff] [blame] | 163 | |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 164 | menu "Layerscape PPA" |
| 165 | config FSL_LS_PPA |
| 166 | bool "FSL Layerscape PPA firmware support" |
macro.wave.z@gmail.com | 01bd334 | 2016-12-08 11:58:22 +0800 | [diff] [blame] | 167 | depends on !ARMV8_PSCI |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 168 | select ARMV8_SEC_FIRMWARE_SUPPORT |
Hou Zhiqiang | 6be115d | 2017-01-16 17:31:48 +0800 | [diff] [blame] | 169 | select SEC_FIRMWARE_ARMV8_PSCI |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 170 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 171 | help |
| 172 | The FSL Primary Protected Application (PPA) is a software component |
| 173 | which is loaded during boot stage, and then remains resident in RAM |
| 174 | and runs in the TrustZone after boot. |
| 175 | Say y to enable it. |
York Sun | f2aaf84 | 2017-05-15 08:52:00 -0700 | [diff] [blame] | 176 | |
| 177 | config SPL_FSL_LS_PPA |
| 178 | bool "FSL Layerscape PPA firmware support for SPL build" |
| 179 | depends on !ARMV8_PSCI |
| 180 | select SPL_ARMV8_SEC_FIRMWARE_SUPPORT |
| 181 | select SEC_FIRMWARE_ARMV8_PSCI |
| 182 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
| 183 | help |
| 184 | The FSL Primary Protected Application (PPA) is a software component |
| 185 | which is loaded during boot stage, and then remains resident in RAM |
| 186 | and runs in the TrustZone after boot. This is to load PPA during SPL |
| 187 | stage instead of the RAM version of U-Boot. Once PPA is initialized, |
| 188 | the rest of U-Boot (including RAM version) runs at EL2. |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 189 | choice |
| 190 | prompt "FSL Layerscape PPA firmware loading-media select" |
| 191 | depends on FSL_LS_PPA |
Hou Zhiqiang | bd6e2cd | 2017-03-17 16:12:33 +0800 | [diff] [blame] | 192 | default SYS_LS_PPA_FW_IN_MMC if SD_BOOT |
| 193 | default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 194 | default SYS_LS_PPA_FW_IN_XIP |
| 195 | |
| 196 | config SYS_LS_PPA_FW_IN_XIP |
| 197 | bool "XIP" |
| 198 | help |
| 199 | Say Y here if the PPA firmware locate at XIP flash, such |
| 200 | as NOR or QSPI flash. |
| 201 | |
Hou Zhiqiang | bd6e2cd | 2017-03-17 16:12:33 +0800 | [diff] [blame] | 202 | config SYS_LS_PPA_FW_IN_MMC |
| 203 | bool "eMMC or SD Card" |
| 204 | help |
| 205 | Say Y here if the PPA firmware locate at eMMC/SD card. |
| 206 | |
| 207 | config SYS_LS_PPA_FW_IN_NAND |
| 208 | bool "NAND" |
| 209 | help |
| 210 | Say Y here if the PPA firmware locate at NAND flash. |
| 211 | |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 212 | endchoice |
| 213 | |
| 214 | config SYS_LS_PPA_FW_ADDR |
| 215 | hex "Address of PPA firmware loading from" |
| 216 | depends on FSL_LS_PPA |
Priyanka Jain | 7d05b99 | 2017-04-28 10:41:35 +0530 | [diff] [blame] | 217 | default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 218 | default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT |
Santan Kumar | 0f0173d | 2017-04-28 12:47:24 +0530 | [diff] [blame] | 219 | default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A |
Ashish Kumar | 227b4bc | 2017-08-31 16:12:54 +0530 | [diff] [blame] | 220 | default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A |
Alison Wang | b5b8bfa | 2017-05-16 10:45:58 +0800 | [diff] [blame] | 221 | default 0x60400000 if SYS_LS_PPA_FW_IN_XIP |
| 222 | default 0x400000 if SYS_LS_PPA_FW_IN_MMC |
| 223 | default 0x400000 if SYS_LS_PPA_FW_IN_NAND |
Hou Zhiqiang | bd6e2cd | 2017-03-17 16:12:33 +0800 | [diff] [blame] | 224 | |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 225 | help |
| 226 | If the PPA firmware locate at XIP flash, such as NOR or |
| 227 | QSPI flash, this address is a directly memory-mapped. |
| 228 | If it is in a serial accessed flash, such as NAND and SD |
| 229 | card, it is a byte offset. |
Vinitha Pillai-B57223 | a4b3ded | 2017-03-23 13:48:14 +0530 | [diff] [blame] | 230 | |
| 231 | config SYS_LS_PPA_ESBC_ADDR |
| 232 | hex "hdr address of PPA firmware loading from" |
| 233 | depends on FSL_LS_PPA && CHAIN_OF_TRUST |
Sumit Garg | 666bbd0 | 2017-08-16 07:13:28 -0400 | [diff] [blame] | 234 | default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A |
| 235 | default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A |
| 236 | default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A |
Udit Agarwal | c83ea8a | 2017-08-16 07:13:29 -0400 | [diff] [blame] | 237 | default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A |
| 238 | default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A |
Sumit Garg | 666bbd0 | 2017-08-16 07:13:28 -0400 | [diff] [blame] | 239 | default 0x680000 if SYS_LS_PPA_FW_IN_MMC |
| 240 | default 0x680000 if SYS_LS_PPA_FW_IN_NAND |
Vinitha Pillai-B57223 | a4b3ded | 2017-03-23 13:48:14 +0530 | [diff] [blame] | 241 | help |
| 242 | If the PPA header firmware locate at XIP flash, such as NOR or |
| 243 | QSPI flash, this address is a directly memory-mapped. |
| 244 | If it is in a serial accessed flash, such as NAND and SD |
| 245 | card, it is a byte offset. |
| 246 | |
Sumit Garg | 8fddf75 | 2017-04-20 05:09:11 +0530 | [diff] [blame] | 247 | config LS_PPA_ESBC_HDR_SIZE |
| 248 | hex "Length of PPA ESBC header" |
| 249 | depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP |
| 250 | default 0x2000 |
| 251 | help |
| 252 | Length (in bytes) of PPA ESBC header to be copied from MMC/SD or |
| 253 | NAND to memory to validate PPA image. |
| 254 | |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 255 | endmenu |
| 256 | |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 257 | config SYS_FSL_ERRATUM_A009008 |
| 258 | bool "Workaround for USB PHY erratum A009008" |
| 259 | |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame^] | 260 | config SYS_FSL_ERRATUM_A009798 |
| 261 | bool "Workaround for USB PHY erratum A009798" |
| 262 | |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 263 | config SYS_FSL_ERRATUM_A010315 |
| 264 | bool "Workaround for PCIe erratum A010315" |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 265 | |
| 266 | config SYS_FSL_ERRATUM_A010539 |
| 267 | bool "Workaround for PIN MUX erratum A010539" |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 268 | |
York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 269 | config MAX_CPUS |
| 270 | int "Maximum number of CPUs permitted for Layerscape" |
| 271 | default 4 if ARCH_LS1043A |
| 272 | default 4 if ARCH_LS1046A |
| 273 | default 16 if ARCH_LS2080A |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 274 | default 8 if ARCH_LS1088A |
York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 275 | default 1 |
| 276 | help |
| 277 | Set this number to the maximum number of possible CPUs in the SoC. |
| 278 | SoCs may have multiple clusters with each cluster may have multiple |
| 279 | ports. If some ports are reserved but higher ports are used for |
| 280 | cores, count the reserved ports. This will allocate enough memory |
| 281 | in spin table to properly handle all cores. |
| 282 | |
York Sun | 728e700 | 2016-12-02 09:32:35 -0800 | [diff] [blame] | 283 | config SECURE_BOOT |
York Sun | 8a3d8ed | 2017-01-04 10:32:08 -0800 | [diff] [blame] | 284 | bool "Secure Boot" |
York Sun | 728e700 | 2016-12-02 09:32:35 -0800 | [diff] [blame] | 285 | help |
| 286 | Enable Freescale Secure Boot feature |
| 287 | |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 288 | config QSPI_AHB_INIT |
| 289 | bool "Init the QSPI AHB bus" |
| 290 | help |
| 291 | The default setting for QSPI AHB bus just support 3bytes addressing. |
| 292 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB |
| 293 | bus for those flashes to support the full QSPI flash size. |
| 294 | |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 295 | config SYS_CCI400_OFFSET |
| 296 | hex "Offset for CCI400 base" |
| 297 | depends on SYS_FSL_HAS_CCI400 |
| 298 | default 0x3090000 if ARCH_LS1088A |
| 299 | default 0x180000 if FSL_LSCH2 |
| 300 | help |
| 301 | Offset for CCI400 base |
| 302 | CCI400 base addr = CCSRBAR + CCI400_OFFSET |
| 303 | |
York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 304 | config SYS_FSL_IFC_BANK_COUNT |
| 305 | int "Maximum banks of Integrated flash controller" |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 306 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A |
York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 307 | default 4 if ARCH_LS1043A |
| 308 | default 4 if ARCH_LS1046A |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 309 | default 8 if ARCH_LS2080A || ARCH_LS1088A |
York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 310 | |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 311 | config SYS_FSL_HAS_CCI400 |
| 312 | bool |
| 313 | |
Ashish Kumar | 97393d6 | 2017-08-18 10:54:36 +0530 | [diff] [blame] | 314 | config SYS_FSL_HAS_CCN504 |
| 315 | bool |
| 316 | |
York Sun | 0dc9abb | 2016-10-04 14:46:50 -0700 | [diff] [blame] | 317 | config SYS_FSL_HAS_DP_DDR |
| 318 | bool |
| 319 | |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 320 | config SYS_FSL_SRDS_1 |
| 321 | bool |
| 322 | |
| 323 | config SYS_FSL_SRDS_2 |
| 324 | bool |
| 325 | |
| 326 | config SYS_HAS_SERDES |
| 327 | bool |
| 328 | |
Ashish kumar | 76bd6ce | 2017-04-07 11:40:32 +0530 | [diff] [blame] | 329 | config FSL_TZASC_1 |
| 330 | bool |
| 331 | |
| 332 | config FSL_TZASC_2 |
| 333 | bool |
| 334 | |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 335 | endmenu |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 336 | |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 337 | menu "Layerscape clock tree configuration" |
| 338 | depends on FSL_LSCH2 || FSL_LSCH3 |
| 339 | |
| 340 | config SYS_FSL_CLK |
| 341 | bool "Enable clock tree initialization" |
| 342 | default y |
| 343 | |
| 344 | config CLUSTER_CLK_FREQ |
| 345 | int "Reference clock of core cluster" |
| 346 | depends on ARCH_LS1012A |
| 347 | default 100000000 |
| 348 | help |
| 349 | This number is the reference clock frequency of core PLL. |
| 350 | For most platforms, the core PLL and Platform PLL have the same |
| 351 | reference clock, but for some platforms, LS1012A for instance, |
| 352 | they are provided sepatately. |
| 353 | |
| 354 | config SYS_FSL_PCLK_DIV |
| 355 | int "Platform clock divider" |
| 356 | default 1 if ARCH_LS1043A |
| 357 | default 1 if ARCH_LS1046A |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 358 | default 1 if ARCH_LS1088A |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 359 | default 2 |
| 360 | help |
| 361 | This is the divider that is used to derive Platform clock from |
| 362 | Platform PLL, in another word: |
| 363 | Platform_clk = Platform_PLL_freq / this_divider |
| 364 | |
| 365 | config SYS_FSL_DSPI_CLK_DIV |
| 366 | int "DSPI clock divider" |
| 367 | default 1 if ARCH_LS1043A |
| 368 | default 2 |
| 369 | help |
| 370 | This is the divider that is used to derive DSPI clock from Platform |
Hou Zhiqiang | 0c8fcb6 | 2017-07-03 18:37:11 +0800 | [diff] [blame] | 371 | clock, in another word DSPI_clk = Platform_clk / this_divider. |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 372 | |
| 373 | config SYS_FSL_DUART_CLK_DIV |
| 374 | int "DUART clock divider" |
| 375 | default 1 if ARCH_LS1043A |
| 376 | default 2 |
| 377 | help |
| 378 | This is the divider that is used to derive DUART clock from Platform |
| 379 | clock, in another word DUART_clk = Platform_clk / this_divider. |
| 380 | |
| 381 | config SYS_FSL_I2C_CLK_DIV |
| 382 | int "I2C clock divider" |
| 383 | default 1 if ARCH_LS1043A |
| 384 | default 2 |
| 385 | help |
| 386 | This is the divider that is used to derive I2C clock from Platform |
| 387 | clock, in another word I2C_clk = Platform_clk / this_divider. |
| 388 | |
| 389 | config SYS_FSL_IFC_CLK_DIV |
| 390 | int "IFC clock divider" |
| 391 | default 1 if ARCH_LS1043A |
| 392 | default 2 |
| 393 | help |
| 394 | This is the divider that is used to derive IFC clock from Platform |
| 395 | clock, in another word IFC_clk = Platform_clk / this_divider. |
| 396 | |
| 397 | config SYS_FSL_LPUART_CLK_DIV |
| 398 | int "LPUART clock divider" |
| 399 | default 1 if ARCH_LS1043A |
| 400 | default 2 |
| 401 | help |
| 402 | This is the divider that is used to derive LPUART clock from Platform |
| 403 | clock, in another word LPUART_clk = Platform_clk / this_divider. |
| 404 | |
| 405 | config SYS_FSL_SDHC_CLK_DIV |
| 406 | int "SDHC clock divider" |
| 407 | default 1 if ARCH_LS1043A |
| 408 | default 1 if ARCH_LS1012A |
| 409 | default 2 |
| 410 | help |
| 411 | This is the divider that is used to derive SDHC clock from Platform |
| 412 | clock, in another word SDHC_clk = Platform_clk / this_divider. |
| 413 | endmenu |
| 414 | |
York Sun | d6964b3 | 2017-03-06 09:02:24 -0800 | [diff] [blame] | 415 | config RESV_RAM |
| 416 | bool |
| 417 | help |
| 418 | Reserve memory from the top, tracked by gd->arch.resv_ram. This |
| 419 | reserved RAM can be used by special driver that resides in memory |
| 420 | after U-Boot exits. It's up to implementation to allocate and allow |
| 421 | access to this reserved memory. For example, the reserved RAM can |
| 422 | be at the high end of physical memory. The reserve RAM may be |
| 423 | excluded from memory bank(s) passed to OS, or marked as reserved. |
| 424 | |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 425 | config SYS_FSL_EC1 |
| 426 | bool |
| 427 | help |
| 428 | Ethernet controller 1, this is connected to MAC3. |
| 429 | Provides DPAA2 capabilities |
| 430 | |
| 431 | config SYS_FSL_EC2 |
| 432 | bool |
| 433 | help |
| 434 | Ethernet controller 2, this is connected to MAC4. |
| 435 | Provides DPAA2 capabilities |
| 436 | |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 437 | config SYS_FSL_ERRATUM_A008336 |
| 438 | bool |
| 439 | |
| 440 | config SYS_FSL_ERRATUM_A008514 |
| 441 | bool |
| 442 | |
| 443 | config SYS_FSL_ERRATUM_A008585 |
| 444 | bool |
| 445 | |
| 446 | config SYS_FSL_ERRATUM_A008850 |
| 447 | bool |
| 448 | |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 449 | config SYS_FSL_ERRATUM_A009203 |
| 450 | bool |
| 451 | |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 452 | config SYS_FSL_ERRATUM_A009635 |
| 453 | bool |
| 454 | |
| 455 | config SYS_FSL_ERRATUM_A009660 |
| 456 | bool |
| 457 | |
| 458 | config SYS_FSL_ERRATUM_A009929 |
| 459 | bool |
York Sun | 1a77075 | 2017-03-06 09:02:26 -0800 | [diff] [blame] | 460 | |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 461 | |
| 462 | config SYS_FSL_HAS_RGMII |
| 463 | bool |
| 464 | depends on SYS_FSL_EC1 || SYS_FSL_EC2 |
| 465 | |
| 466 | |
York Sun | 1a77075 | 2017-03-06 09:02:26 -0800 | [diff] [blame] | 467 | config SYS_MC_RSV_MEM_ALIGN |
| 468 | hex "Management Complex reserved memory alignment" |
| 469 | depends on RESV_RAM |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 470 | default 0x20000000 if ARCH_LS2080A |
| 471 | default 0x70000000 if ARCH_LS1088A |
York Sun | 1a77075 | 2017-03-06 09:02:26 -0800 | [diff] [blame] | 472 | help |
| 473 | Reserved memory needs to be aligned for MC to use. Default value |
| 474 | is 512MB. |
Philipp Tomsich | 2d6a0cc | 2017-08-03 23:23:55 +0200 | [diff] [blame] | 475 | |
| 476 | config SPL_LDSCRIPT |
| 477 | default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A |