York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 1 | config ARCH_LS1012A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 2 | bool |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 3 | select FSL_LSCH2 |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 4 | select SYS_FSL_DDR_BE |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 5 | select SYS_FSL_MMDC |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 6 | select SYS_FSL_ERRATUM_A010315 |
| 7 | |
| 8 | config ARCH_LS1043A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 9 | bool |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 10 | select FSL_LSCH2 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame^] | 11 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 12 | select SYS_FSL_DDR_BE |
| 13 | select SYS_FSL_DDR_VER_50 |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 14 | select SYS_FSL_ERRATUM_A010315 |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 15 | select SYS_FSL_ERRATUM_A010539 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame^] | 16 | select SYS_FSL_HAS_DDR3 |
| 17 | select SYS_FSL_HAS_DDR4 |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 18 | |
York Sun | bad4984 | 2016-09-26 08:09:24 -0700 | [diff] [blame] | 19 | config ARCH_LS1046A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 20 | bool |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 21 | select FSL_LSCH2 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame^] | 22 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 23 | select SYS_FSL_DDR_BE |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 24 | select SYS_FSL_DDR_VER_50 |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 25 | select SYS_FSL_ERRATUM_A010539 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame^] | 26 | select SYS_FSL_HAS_DDR4 |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 27 | select SYS_FSL_SRDS_2 |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 28 | |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 29 | config ARCH_LS2080A |
| 30 | bool |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 31 | select FSL_LSCH3 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame^] | 32 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 33 | select SYS_FSL_DDR_LE |
| 34 | select SYS_FSL_DDR_VER_50 |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 35 | select SYS_FSL_HAS_DP_DDR |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 36 | select SYS_FSL_HAS_SEC |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame^] | 37 | select SYS_FSL_HAS_DDR4 |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 38 | select SYS_FSL_SEC_COMPAT_5 |
York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 39 | select SYS_FSL_SEC_LE |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 40 | select SYS_FSL_SRDS_2 |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 41 | |
| 42 | config FSL_LSCH2 |
| 43 | bool |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 44 | select SYS_FSL_HAS_SEC |
| 45 | select SYS_FSL_SEC_COMPAT_5 |
York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 46 | select SYS_FSL_SEC_BE |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 47 | select SYS_FSL_SRDS_1 |
| 48 | select SYS_HAS_SERDES |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 49 | |
| 50 | config FSL_LSCH3 |
| 51 | bool |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 52 | select SYS_FSL_SRDS_1 |
| 53 | select SYS_HAS_SERDES |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 54 | |
| 55 | menu "Layerscape architecture" |
| 56 | depends on FSL_LSCH2 || FSL_LSCH3 |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 57 | |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 58 | menu "Layerscape PPA" |
| 59 | config FSL_LS_PPA |
| 60 | bool "FSL Layerscape PPA firmware support" |
macro.wave.z@gmail.com | 01bd334 | 2016-12-08 11:58:22 +0800 | [diff] [blame] | 61 | depends on !ARMV8_PSCI |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 62 | depends on ARCH_LS1043A || ARCH_LS1046A |
| 63 | select FSL_PPA_ARMV8_PSCI |
| 64 | help |
| 65 | The FSL Primary Protected Application (PPA) is a software component |
| 66 | which is loaded during boot stage, and then remains resident in RAM |
| 67 | and runs in the TrustZone after boot. |
| 68 | Say y to enable it. |
| 69 | |
| 70 | config FSL_PPA_ARMV8_PSCI |
| 71 | bool "PSCI implementation in PPA firmware" |
| 72 | depends on FSL_LS_PPA |
| 73 | help |
| 74 | This config enables the ARMv8 PSCI implementation in PPA firmware. |
| 75 | This is a private PSCI implementation and different from those |
| 76 | implemented under the common ARMv8 PSCI framework. |
| 77 | endmenu |
| 78 | |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 79 | config SYS_FSL_ERRATUM_A010315 |
| 80 | bool "Workaround for PCIe erratum A010315" |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 81 | |
| 82 | config SYS_FSL_ERRATUM_A010539 |
| 83 | bool "Workaround for PIN MUX erratum A010539" |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 84 | |
York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 85 | config MAX_CPUS |
| 86 | int "Maximum number of CPUs permitted for Layerscape" |
| 87 | default 4 if ARCH_LS1043A |
| 88 | default 4 if ARCH_LS1046A |
| 89 | default 16 if ARCH_LS2080A |
| 90 | default 1 |
| 91 | help |
| 92 | Set this number to the maximum number of possible CPUs in the SoC. |
| 93 | SoCs may have multiple clusters with each cluster may have multiple |
| 94 | ports. If some ports are reserved but higher ports are used for |
| 95 | cores, count the reserved ports. This will allocate enough memory |
| 96 | in spin table to properly handle all cores. |
| 97 | |
York Sun | 0dc9abb | 2016-10-04 14:46:50 -0700 | [diff] [blame] | 98 | config NUM_DDR_CONTROLLERS |
| 99 | int "Maximum DDR controllers" |
| 100 | default 3 if ARCH_LS2080A |
| 101 | default 1 |
| 102 | |
York Sun | 728e700 | 2016-12-02 09:32:35 -0800 | [diff] [blame] | 103 | config SECURE_BOOT |
| 104 | bool |
| 105 | help |
| 106 | Enable Freescale Secure Boot feature |
| 107 | |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 108 | config QSPI_AHB_INIT |
| 109 | bool "Init the QSPI AHB bus" |
| 110 | help |
| 111 | The default setting for QSPI AHB bus just support 3bytes addressing. |
| 112 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB |
| 113 | bus for those flashes to support the full QSPI flash size. |
| 114 | |
York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 115 | config SYS_FSL_IFC_BANK_COUNT |
| 116 | int "Maximum banks of Integrated flash controller" |
| 117 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A |
| 118 | default 4 if ARCH_LS1043A |
| 119 | default 4 if ARCH_LS1046A |
| 120 | default 8 if ARCH_LS2080A |
| 121 | |
York Sun | 0dc9abb | 2016-10-04 14:46:50 -0700 | [diff] [blame] | 122 | config SYS_FSL_HAS_DP_DDR |
| 123 | bool |
| 124 | |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 125 | config SYS_FSL_SRDS_1 |
| 126 | bool |
| 127 | |
| 128 | config SYS_FSL_SRDS_2 |
| 129 | bool |
| 130 | |
| 131 | config SYS_HAS_SERDES |
| 132 | bool |
| 133 | |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 134 | endmenu |