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git01.mediatek.com / filogic / uboot / 6b62ef0d98f0695009771abbbc8003ae266365d4 / . / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig
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York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]1config ARCH_LS1012A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]2 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]3 select FSL_LSCH2
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]4 select SYS_FSL_MMDC
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]5 select SYS_FSL_ERRATUM_A010315
6
7config ARCH_LS1043A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]8 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]9 select FSL_LSCH2
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]10 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]11 select SYS_FSL_ERRATUM_A010539
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]12
York Sunbad49842016-09-26 08:09:24 -0700[diff] [blame]13config ARCH_LS1046A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]14 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]15 select FSL_LSCH2
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]16 select SYS_FSL_ERRATUM_A010539
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame^]17 select SYS_FSL_SRDS_2
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]18
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]19config ARCH_LS2080A
20 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]21 select FSL_LSCH3
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame^]22 select SYS_FSL_HAS_DP_DDR
23 select SYS_FSL_SRDS_2
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]24
25config FSL_LSCH2
26 bool
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame^]27 select SYS_FSL_SRDS_1
28 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]29
30config FSL_LSCH3
31 bool
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame^]32 select SYS_FSL_SRDS_1
33 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]34
35menu "Layerscape architecture"
36 depends on FSL_LSCH2 || FSL_LSCH3
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]37
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]38config SYS_FSL_MMDC
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]39 bool
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]40
41config SYS_FSL_ERRATUM_A010315
42 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]43
44config SYS_FSL_ERRATUM_A010539
45 bool "Workaround for PIN MUX erratum A010539"
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]46
York Sunf188d222016-10-04 14:45:01 -0700[diff] [blame]47config MAX_CPUS
48 int "Maximum number of CPUs permitted for Layerscape"
49 default 4 if ARCH_LS1043A
50 default 4 if ARCH_LS1046A
51 default 16 if ARCH_LS2080A
52 default 1
53 help
54 Set this number to the maximum number of possible CPUs in the SoC.
55 SoCs may have multiple clusters with each cluster may have multiple
56 ports. If some ports are reserved but higher ports are used for
57 cores, count the reserved ports. This will allocate enough memory
58 in spin table to properly handle all cores.
59
York Sun0dc9abb2016-10-04 14:46:50 -0700[diff] [blame]60config NUM_DDR_CONTROLLERS
61 int "Maximum DDR controllers"
62 default 3 if ARCH_LS2080A
63 default 1
64
York Sune7310a32016-10-04 14:45:54 -0700[diff] [blame]65config SYS_FSL_IFC_BANK_COUNT
66 int "Maximum banks of Integrated flash controller"
67 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
68 default 4 if ARCH_LS1043A
69 default 4 if ARCH_LS1046A
70 default 8 if ARCH_LS2080A
71
York Sun0dc9abb2016-10-04 14:46:50 -0700[diff] [blame]72config SYS_FSL_HAS_DP_DDR
73 bool
74
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame^]75config SYS_FSL_SRDS_1
76 bool
77
78config SYS_FSL_SRDS_2
79 bool
80
81config SYS_HAS_SERDES
82 bool
83
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]84endmenu