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git01.mediatek.com / filogic / uboot / b6fffd8eae7160f6072cfca681c336c2c77c6604 / . / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig
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York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]1config ARCH_LS1012A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]2 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]3 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame^]4 select SYS_FSL_DDR_BE
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]5 select SYS_FSL_MMDC
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]6 select SYS_FSL_ERRATUM_A010315
7
8config ARCH_LS1043A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]9 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]10 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame^]11 select SYS_FSL_DDR_BE
12 select SYS_FSL_DDR_VER_50
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]13 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]14 select SYS_FSL_ERRATUM_A010539
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]15
York Sunbad49842016-09-26 08:09:24 -0700[diff] [blame]16config ARCH_LS1046A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]17 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]18 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame^]19 select SYS_FSL_DDR_BE
20 select SYS_FSL_DDR4
21 select SYS_FSL_DDR_VER_50
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]22 select SYS_FSL_ERRATUM_A010539
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]23 select SYS_FSL_SRDS_2
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]24
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]25config ARCH_LS2080A
26 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]27 select FSL_LSCH3
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame^]28 select SYS_FSL_DDR4
29 select SYS_FSL_DDR_LE
30 select SYS_FSL_DDR_VER_50
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]31 select SYS_FSL_HAS_DP_DDR
32 select SYS_FSL_SRDS_2
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]33
34config FSL_LSCH2
35 bool
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]36 select SYS_FSL_SRDS_1
37 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]38
39config FSL_LSCH3
40 bool
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]41 select SYS_FSL_SRDS_1
42 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]43
44menu "Layerscape architecture"
45 depends on FSL_LSCH2 || FSL_LSCH3
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]46
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]47config SYS_FSL_MMDC
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]48 bool
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]49
50config SYS_FSL_ERRATUM_A010315
51 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]52
53config SYS_FSL_ERRATUM_A010539
54 bool "Workaround for PIN MUX erratum A010539"
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]55
York Sunf188d222016-10-04 14:45:01 -0700[diff] [blame]56config MAX_CPUS
57 int "Maximum number of CPUs permitted for Layerscape"
58 default 4 if ARCH_LS1043A
59 default 4 if ARCH_LS1046A
60 default 16 if ARCH_LS2080A
61 default 1
62 help
63 Set this number to the maximum number of possible CPUs in the SoC.
64 SoCs may have multiple clusters with each cluster may have multiple
65 ports. If some ports are reserved but higher ports are used for
66 cores, count the reserved ports. This will allocate enough memory
67 in spin table to properly handle all cores.
68
York Sun0dc9abb2016-10-04 14:46:50 -0700[diff] [blame]69config NUM_DDR_CONTROLLERS
70 int "Maximum DDR controllers"
71 default 3 if ARCH_LS2080A
72 default 1
73
York Sune7310a32016-10-04 14:45:54 -0700[diff] [blame]74config SYS_FSL_IFC_BANK_COUNT
75 int "Maximum banks of Integrated flash controller"
76 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
77 default 4 if ARCH_LS1043A
78 default 4 if ARCH_LS1046A
79 default 8 if ARCH_LS2080A
80
York Sun0dc9abb2016-10-04 14:46:50 -0700[diff] [blame]81config SYS_FSL_HAS_DP_DDR
82 bool
83
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]84config SYS_FSL_SRDS_1
85 bool
86
87config SYS_FSL_SRDS_2
88 bool
89
90config SYS_HAS_SERDES
91 bool
92
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame^]93config SYS_FSL_DDR
94 bool "Freescale DDR driver"
95 help
96 Select Freescale General DDR driver, shared between most Freescale
97 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
98 based Layerscape SoCs (such as ls2080a).
99
100config SYS_FSL_DDR_BE
101 bool
102 help
103 Access DDR registers in big-endian.
104
105config SYS_FSL_DDR_LE
106 bool
107 help
108 Access DDR registers in little-endian.
109
110config SYS_FSL_DDR_VER
111 int
112 default 50 if SYS_FSL_DDR_VER_50
113
114config SYS_FSL_DDR_VER_50
115 bool
116
117config SYS_FSL_DDRC_ARM_GEN3
118 bool
119
120config SYS_FSL_DDRC_GEN4
121 bool
122
123config SYS_FSL_DDR3
124 bool "Freescale DDR3 controller"
125 depends on !SYS_FSL_DDR4
126 select SYS_FSL_DDR
127 select SYS_FSL_DDRC_ARM_GEN3
128 help
129 Enable Freescale DDR3 controller on ARM-based SoCs.
130
131config SYS_FSL_DDR4
132 bool "Freescale DDR4 controller"
133 select SYS_FSL_DDR
134 select SYS_FSL_DDRC_GEN4
135 help
136 Enable Freescale DDR4 controller.
137
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]138endmenu