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git01.mediatek.com / filogic / uboot / 52ae4fd60032e0d7828d8cb5fc784a3874f865e1 / . / arch / arm / cpu / armv8 / fsl-layerscape / Kconfig
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York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]1config ARCH_LS1012A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]2 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]3 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame]4 select SYS_FSL_DDR_BE
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]5 select SYS_FSL_MMDC
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]6 select SYS_FSL_ERRATUM_A010315
7
8config ARCH_LS1043A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]9 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]10 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame]11 select SYS_FSL_DDR_BE
12 select SYS_FSL_DDR_VER_50
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]13 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]14 select SYS_FSL_ERRATUM_A010539
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]15
York Sunbad49842016-09-26 08:09:24 -0700[diff] [blame]16config ARCH_LS1046A
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]17 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]18 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame]19 select SYS_FSL_DDR_BE
20 select SYS_FSL_DDR4
21 select SYS_FSL_DDR_VER_50
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]22 select SYS_FSL_ERRATUM_A010539
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]23 select SYS_FSL_SRDS_2
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]24
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]25config ARCH_LS2080A
26 bool
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]27 select FSL_LSCH3
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame]28 select SYS_FSL_DDR4
29 select SYS_FSL_DDR_LE
30 select SYS_FSL_DDR_VER_50
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]31 select SYS_FSL_HAS_DP_DDR
32 select SYS_FSL_SRDS_2
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]33
34config FSL_LSCH2
35 bool
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]36 select SYS_FSL_SRDS_1
37 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]38
39config FSL_LSCH3
40 bool
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]41 select SYS_FSL_SRDS_1
42 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]43
44menu "Layerscape architecture"
45 depends on FSL_LSCH2 || FSL_LSCH3
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]46
York Sunb3d71642016-09-26 08:09:26 -0700[diff] [blame]47config SYS_FSL_MMDC
York Sunfcd0e742016-10-04 14:31:47 -0700[diff] [blame]48 bool
York Sun149eb332016-09-26 08:09:27 -0700[diff] [blame]49
50config SYS_FSL_ERRATUM_A010315
51 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800[diff] [blame]52
53config SYS_FSL_ERRATUM_A010539
54 bool "Workaround for PIN MUX erratum A010539"
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]55
York Sunf188d222016-10-04 14:45:01 -0700[diff] [blame]56config MAX_CPUS
57 int "Maximum number of CPUs permitted for Layerscape"
58 default 4 if ARCH_LS1043A
59 default 4 if ARCH_LS1046A
60 default 16 if ARCH_LS2080A
61 default 1
62 help
63 Set this number to the maximum number of possible CPUs in the SoC.
64 SoCs may have multiple clusters with each cluster may have multiple
65 ports. If some ports are reserved but higher ports are used for
66 cores, count the reserved ports. This will allocate enough memory
67 in spin table to properly handle all cores.
68
York Sun0dc9abb2016-10-04 14:46:50 -0700[diff] [blame]69config NUM_DDR_CONTROLLERS
70 int "Maximum DDR controllers"
71 default 3 if ARCH_LS2080A
72 default 1
73
York Sun728e7002016-12-02 09:32:35 -0800[diff] [blame]74config SECURE_BOOT
75 bool
76 help
77 Enable Freescale Secure Boot feature
78
Yuan Yao52ae4fd2016-12-01 10:13:52 +0800[diff] [blame^]79config QSPI_AHB_INIT
80 bool "Init the QSPI AHB bus"
81 help
82 The default setting for QSPI AHB bus just support 3bytes addressing.
83 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
84 bus for those flashes to support the full QSPI flash size.
85
York Sune7310a32016-10-04 14:45:54 -0700[diff] [blame]86config SYS_FSL_IFC_BANK_COUNT
87 int "Maximum banks of Integrated flash controller"
88 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
89 default 4 if ARCH_LS1043A
90 default 4 if ARCH_LS1046A
91 default 8 if ARCH_LS2080A
92
York Sun0dc9abb2016-10-04 14:46:50 -0700[diff] [blame]93config SYS_FSL_HAS_DP_DDR
94 bool
95
York Sun6b62ef02016-10-04 18:01:34 -0700[diff] [blame]96config SYS_FSL_SRDS_1
97 bool
98
99config SYS_FSL_SRDS_2
100 bool
101
102config SYS_HAS_SERDES
103 bool
104
York Sunb6fffd82016-10-04 18:03:08 -0700[diff] [blame]105config SYS_FSL_DDR
106 bool "Freescale DDR driver"
107 help
108 Select Freescale General DDR driver, shared between most Freescale
109 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
110 based Layerscape SoCs (such as ls2080a).
111
112config SYS_FSL_DDR_BE
113 bool
114 help
115 Access DDR registers in big-endian.
116
117config SYS_FSL_DDR_LE
118 bool
119 help
120 Access DDR registers in little-endian.
121
122config SYS_FSL_DDR_VER
123 int
124 default 50 if SYS_FSL_DDR_VER_50
125
126config SYS_FSL_DDR_VER_50
127 bool
128
129config SYS_FSL_DDRC_ARM_GEN3
130 bool
131
132config SYS_FSL_DDRC_GEN4
133 bool
134
135config SYS_FSL_DDR3
136 bool "Freescale DDR3 controller"
137 depends on !SYS_FSL_DDR4
138 select SYS_FSL_DDR
139 select SYS_FSL_DDRC_ARM_GEN3
140 help
141 Enable Freescale DDR3 controller on ARM-based SoCs.
142
143config SYS_FSL_DDR4
144 bool "Freescale DDR4 controller"
145 select SYS_FSL_DDR
146 select SYS_FSL_DDRC_GEN4
147 help
148 Enable Freescale DDR4 controller.
149
York Sun4dd8c612016-10-04 14:31:48 -0700[diff] [blame]150endmenu