York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 1 | config ARCH_LS1012A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 2 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 3 | select ARMV8_SET_SMPEN |
Rajesh Bhagat | cd786e8 | 2018-11-05 18:01:48 +0000 | [diff] [blame] | 4 | select ARM_ERRATA_855873 if !TFABOOT |
Rajesh Bhagat | 52d237a | 2019-01-25 13:36:26 +0000 | [diff] [blame] | 5 | select FSL_LAYERSCAPE |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 6 | select FSL_LSCH2 |
Sriram Dash | 4a94333 | 2018-01-30 15:58:44 +0530 | [diff] [blame] | 7 | select SYS_FSL_SRDS_1 |
| 8 | select SYS_HAS_SERDES |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 9 | select SYS_FSL_DDR_BE |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 10 | select SYS_FSL_MMDC |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 11 | select SYS_FSL_ERRATUM_A010315 |
Ran Wang | 02dc77b | 2017-11-13 16:14:48 +0800 | [diff] [blame] | 12 | select SYS_FSL_ERRATUM_A009798 |
| 13 | select SYS_FSL_ERRATUM_A008997 |
| 14 | select SYS_FSL_ERRATUM_A009007 |
| 15 | select SYS_FSL_ERRATUM_A009008 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 16 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 17 | select BOARD_EARLY_INIT_F |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 18 | select SYS_I2C_MXC |
Biwen Li | 0a759bb | 2019-12-31 15:33:41 +0800 | [diff] [blame] | 19 | select SYS_I2C_MXC_I2C1 if !DM_I2C |
| 20 | select SYS_I2C_MXC_I2C2 if !DM_I2C |
Masahiro Yamada | acede7a | 2017-12-04 12:37:00 +0900 | [diff] [blame] | 21 | imply PANIC_HANG |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 22 | |
Yuantian Tang | 4aefa16 | 2019-04-10 16:43:33 +0800 | [diff] [blame] | 23 | config ARCH_LS1028A |
| 24 | bool |
| 25 | select ARMV8_SET_SMPEN |
| 26 | select FSL_LSCH3 |
| 27 | select NXP_LSCH3_2 |
| 28 | select SYS_FSL_HAS_CCI400 |
| 29 | select SYS_FSL_SRDS_1 |
| 30 | select SYS_HAS_SERDES |
| 31 | select SYS_FSL_DDR |
| 32 | select SYS_FSL_DDR_LE |
| 33 | select SYS_FSL_DDR_VER_50 |
| 34 | select SYS_FSL_HAS_DDR3 |
| 35 | select SYS_FSL_HAS_DDR4 |
| 36 | select SYS_FSL_HAS_SEC |
| 37 | select SYS_FSL_SEC_COMPAT_5 |
| 38 | select SYS_FSL_SEC_LE |
| 39 | select FSL_TZASC_1 |
| 40 | select ARCH_EARLY_INIT_R |
| 41 | select BOARD_EARLY_INIT_F |
| 42 | select SYS_I2C_MXC |
Ran Wang | e118acb | 2019-05-14 17:34:56 +0800 | [diff] [blame] | 43 | select SYS_FSL_ERRATUM_A008997 |
Yuantian Tang | 4aefa16 | 2019-04-10 16:43:33 +0800 | [diff] [blame] | 44 | select SYS_FSL_ERRATUM_A009007 |
| 45 | select SYS_FSL_ERRATUM_A008514 if !TFABOOT |
| 46 | select SYS_FSL_ERRATUM_A009663 if !TFABOOT |
| 47 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT |
Laurentiu Tudor | 7ea2feb | 2019-10-18 09:01:56 +0000 | [diff] [blame] | 48 | select SYS_FSL_ERRATUM_A050382 |
Yuantian Tang | 4aefa16 | 2019-04-10 16:43:33 +0800 | [diff] [blame] | 49 | imply PANIC_HANG |
| 50 | |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 51 | config ARCH_LS1043A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 52 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 53 | select ARMV8_SET_SMPEN |
Rajesh Bhagat | cd786e8 | 2018-11-05 18:01:48 +0000 | [diff] [blame] | 54 | select ARM_ERRATA_855873 if !TFABOOT |
Rajesh Bhagat | 52d237a | 2019-01-25 13:36:26 +0000 | [diff] [blame] | 55 | select FSL_LAYERSCAPE |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 56 | select FSL_LSCH2 |
Sriram Dash | 4a94333 | 2018-01-30 15:58:44 +0530 | [diff] [blame] | 57 | select SYS_FSL_SRDS_1 |
| 58 | select SYS_HAS_SERDES |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 59 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 60 | select SYS_FSL_DDR_BE |
| 61 | select SYS_FSL_DDR_VER_50 |
Rajesh Bhagat | cd786e8 | 2018-11-05 18:01:48 +0000 | [diff] [blame] | 62 | select SYS_FSL_ERRATUM_A008850 if !TFABOOT |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 63 | select SYS_FSL_ERRATUM_A008997 |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 64 | select SYS_FSL_ERRATUM_A009007 |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 65 | select SYS_FSL_ERRATUM_A009008 |
Rajesh Bhagat | cd786e8 | 2018-11-05 18:01:48 +0000 | [diff] [blame] | 66 | select SYS_FSL_ERRATUM_A009660 if !TFABOOT |
| 67 | select SYS_FSL_ERRATUM_A009663 if !TFABOOT |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 68 | select SYS_FSL_ERRATUM_A009798 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 69 | select SYS_FSL_ERRATUM_A009929 |
Rajesh Bhagat | cd786e8 | 2018-11-05 18:01:48 +0000 | [diff] [blame] | 70 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 71 | select SYS_FSL_ERRATUM_A010315 |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 72 | select SYS_FSL_ERRATUM_A010539 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 73 | select SYS_FSL_HAS_DDR3 |
| 74 | select SYS_FSL_HAS_DDR4 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 75 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 76 | select BOARD_EARLY_INIT_F |
Biwen Li | 014460b | 2020-02-05 22:02:16 +0800 | [diff] [blame^] | 77 | select SYS_I2C_MXC if !DM_I2C |
| 78 | select SYS_I2C_MXC_I2C1 if !DM_I2C |
| 79 | select SYS_I2C_MXC_I2C2 if !DM_I2C |
| 80 | select SYS_I2C_MXC_I2C3 if !DM_I2C |
| 81 | select SYS_I2C_MXC_I2C4 if !DM_I2C |
Simon Glass | c88a09a | 2017-08-04 16:34:34 -0600 | [diff] [blame] | 82 | imply CMD_PCI |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 83 | |
York Sun | bad4984 | 2016-09-26 08:09:24 -0700 | [diff] [blame] | 84 | config ARCH_LS1046A |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 85 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 86 | select ARMV8_SET_SMPEN |
Rajesh Bhagat | 52d237a | 2019-01-25 13:36:26 +0000 | [diff] [blame] | 87 | select FSL_LAYERSCAPE |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 88 | select FSL_LSCH2 |
Sriram Dash | 4a94333 | 2018-01-30 15:58:44 +0530 | [diff] [blame] | 89 | select SYS_FSL_SRDS_1 |
| 90 | select SYS_HAS_SERDES |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 91 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 92 | select SYS_FSL_DDR_BE |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 93 | select SYS_FSL_DDR_VER_50 |
Rajesh Bhagat | cd786e8 | 2018-11-05 18:01:48 +0000 | [diff] [blame] | 94 | select SYS_FSL_ERRATUM_A008336 if !TFABOOT |
| 95 | select SYS_FSL_ERRATUM_A008511 if !TFABOOT |
| 96 | select SYS_FSL_ERRATUM_A008850 if !TFABOOT |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 97 | select SYS_FSL_ERRATUM_A008997 |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 98 | select SYS_FSL_ERRATUM_A009007 |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 99 | select SYS_FSL_ERRATUM_A009008 |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 100 | select SYS_FSL_ERRATUM_A009798 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 101 | select SYS_FSL_ERRATUM_A009801 |
Rajesh Bhagat | cd786e8 | 2018-11-05 18:01:48 +0000 | [diff] [blame] | 102 | select SYS_FSL_ERRATUM_A009803 if !TFABOOT |
| 103 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT |
| 104 | select SYS_FSL_ERRATUM_A010165 if !TFABOOT |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 105 | select SYS_FSL_ERRATUM_A010539 |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 106 | select SYS_FSL_HAS_DDR4 |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 107 | select SYS_FSL_SRDS_2 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 108 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 109 | select BOARD_EARLY_INIT_F |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 110 | select SYS_I2C_MXC |
| 111 | select SYS_I2C_MXC_I2C1 |
| 112 | select SYS_I2C_MXC_I2C2 |
| 113 | select SYS_I2C_MXC_I2C3 |
| 114 | select SYS_I2C_MXC_I2C4 |
Simon Glass | 0e5faf0 | 2017-06-14 21:28:21 -0600 | [diff] [blame] | 115 | imply SCSI |
Tuomas Tynkkynen | edf9f62 | 2017-12-08 15:36:19 +0200 | [diff] [blame] | 116 | imply SCSI_AHCI |
York Sun | b3d7164 | 2016-09-26 08:09:26 -0700 | [diff] [blame] | 117 | |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 118 | config ARCH_LS1088A |
| 119 | bool |
| 120 | select ARMV8_SET_SMPEN |
Pankit Garg | f5c2a83 | 2018-12-27 04:37:55 +0000 | [diff] [blame] | 121 | select ARM_ERRATA_855873 if !TFABOOT |
Rajesh Bhagat | 52d237a | 2019-01-25 13:36:26 +0000 | [diff] [blame] | 122 | select FSL_LAYERSCAPE |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 123 | select FSL_LSCH3 |
Sriram Dash | 4a94333 | 2018-01-30 15:58:44 +0530 | [diff] [blame] | 124 | select SYS_FSL_SRDS_1 |
| 125 | select SYS_HAS_SERDES |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 126 | select SYS_FSL_DDR |
| 127 | select SYS_FSL_DDR_LE |
| 128 | select SYS_FSL_DDR_VER_50 |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 129 | select SYS_FSL_EC1 |
| 130 | select SYS_FSL_EC2 |
Pankit Garg | f5c2a83 | 2018-12-27 04:37:55 +0000 | [diff] [blame] | 131 | select SYS_FSL_ERRATUM_A009803 if !TFABOOT |
| 132 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT |
| 133 | select SYS_FSL_ERRATUM_A010165 if !TFABOOT |
| 134 | select SYS_FSL_ERRATUM_A008511 if !TFABOOT |
| 135 | select SYS_FSL_ERRATUM_A008850 if !TFABOOT |
Ran Wang | ef27707 | 2017-09-22 15:21:34 +0800 | [diff] [blame] | 136 | select SYS_FSL_ERRATUM_A009007 |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 137 | select SYS_FSL_HAS_CCI400 |
| 138 | select SYS_FSL_HAS_DDR4 |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 139 | select SYS_FSL_HAS_RGMII |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 140 | select SYS_FSL_HAS_SEC |
| 141 | select SYS_FSL_SEC_COMPAT_5 |
| 142 | select SYS_FSL_SEC_LE |
| 143 | select SYS_FSL_SRDS_1 |
| 144 | select SYS_FSL_SRDS_2 |
| 145 | select FSL_TZASC_1 |
Rajesh Bhagat | 5756f7e | 2019-01-20 05:30:06 +0000 | [diff] [blame] | 146 | select FSL_TZASC_400 |
| 147 | select FSL_TZPC_BP147 |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 148 | select ARCH_EARLY_INIT_R |
| 149 | select BOARD_EARLY_INIT_F |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 150 | select SYS_I2C_MXC |
Chuanhua Han | 98a5e40 | 2019-07-26 20:25:37 +0800 | [diff] [blame] | 151 | select SYS_I2C_MXC_I2C1 if !TFABOOT |
| 152 | select SYS_I2C_MXC_I2C2 if !TFABOOT |
| 153 | select SYS_I2C_MXC_I2C3 if !TFABOOT |
| 154 | select SYS_I2C_MXC_I2C4 if !TFABOOT |
Ashish Kumar | a179e56 | 2017-11-02 09:50:47 +0530 | [diff] [blame] | 155 | imply SCSI |
Masahiro Yamada | acede7a | 2017-12-04 12:37:00 +0900 | [diff] [blame] | 156 | imply PANIC_HANG |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 157 | |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 158 | config ARCH_LS2080A |
| 159 | bool |
Hou Zhiqiang | 4d1525a | 2017-01-06 17:41:11 +0800 | [diff] [blame] | 160 | select ARMV8_SET_SMPEN |
Tom Rini | bacb52c | 2017-03-07 07:13:42 -0500 | [diff] [blame] | 161 | select ARM_ERRATA_826974 |
| 162 | select ARM_ERRATA_828024 |
| 163 | select ARM_ERRATA_829520 |
| 164 | select ARM_ERRATA_833471 |
Rajesh Bhagat | 52d237a | 2019-01-25 13:36:26 +0000 | [diff] [blame] | 165 | select FSL_LAYERSCAPE |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 166 | select FSL_LSCH3 |
Sriram Dash | 4a94333 | 2018-01-30 15:58:44 +0530 | [diff] [blame] | 167 | select SYS_FSL_SRDS_1 |
| 168 | select SYS_HAS_SERDES |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 169 | select SYS_FSL_DDR |
York Sun | b6fffd8 | 2016-10-04 18:03:08 -0700 | [diff] [blame] | 170 | select SYS_FSL_DDR_LE |
| 171 | select SYS_FSL_DDR_VER_50 |
Ashish Kumar | 97393d6 | 2017-08-18 10:54:36 +0530 | [diff] [blame] | 172 | select SYS_FSL_HAS_CCN504 |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 173 | select SYS_FSL_HAS_DP_DDR |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 174 | select SYS_FSL_HAS_SEC |
York Sun | d297d39 | 2016-12-28 08:43:40 -0800 | [diff] [blame] | 175 | select SYS_FSL_HAS_DDR4 |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 176 | select SYS_FSL_SEC_COMPAT_5 |
York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 177 | select SYS_FSL_SEC_LE |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 178 | select SYS_FSL_SRDS_2 |
Ashish kumar | 76bd6ce | 2017-04-07 11:40:32 +0530 | [diff] [blame] | 179 | select FSL_TZASC_1 |
| 180 | select FSL_TZASC_2 |
Rajesh Bhagat | 5756f7e | 2019-01-20 05:30:06 +0000 | [diff] [blame] | 181 | select FSL_TZASC_400 |
| 182 | select FSL_TZPC_BP147 |
Rajesh Bhagat | d5691be | 2018-12-27 04:37:59 +0000 | [diff] [blame] | 183 | select SYS_FSL_ERRATUM_A008336 if !TFABOOT |
| 184 | select SYS_FSL_ERRATUM_A008511 if !TFABOOT |
| 185 | select SYS_FSL_ERRATUM_A008514 if !TFABOOT |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 186 | select SYS_FSL_ERRATUM_A008585 |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 187 | select SYS_FSL_ERRATUM_A008997 |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 188 | select SYS_FSL_ERRATUM_A009007 |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 189 | select SYS_FSL_ERRATUM_A009008 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 190 | select SYS_FSL_ERRATUM_A009635 |
Rajesh Bhagat | d5691be | 2018-12-27 04:37:59 +0000 | [diff] [blame] | 191 | select SYS_FSL_ERRATUM_A009663 if !TFABOOT |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 192 | select SYS_FSL_ERRATUM_A009798 |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 193 | select SYS_FSL_ERRATUM_A009801 |
Rajesh Bhagat | d5691be | 2018-12-27 04:37:59 +0000 | [diff] [blame] | 194 | select SYS_FSL_ERRATUM_A009803 if !TFABOOT |
| 195 | select SYS_FSL_ERRATUM_A009942 if !TFABOOT |
| 196 | select SYS_FSL_ERRATUM_A010165 if !TFABOOT |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 197 | select SYS_FSL_ERRATUM_A009203 |
Simon Glass | 62adede | 2017-01-23 13:31:19 -0700 | [diff] [blame] | 198 | select ARCH_EARLY_INIT_R |
Simon Glass | 7a99a87 | 2017-01-23 13:31:20 -0700 | [diff] [blame] | 199 | select BOARD_EARLY_INIT_F |
Sriram Dash | 7122a0c | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 200 | select SYS_I2C_MXC |
Chuanhua Han | 3f27fff | 2019-07-26 19:24:03 +0800 | [diff] [blame] | 201 | select SYS_I2C_MXC_I2C1 if !TFABOOT |
| 202 | select SYS_I2C_MXC_I2C2 if !TFABOOT |
| 203 | select SYS_I2C_MXC_I2C3 if !TFABOOT |
| 204 | select SYS_I2C_MXC_I2C4 if !TFABOOT |
Masahiro Yamada | 9afc6c5 | 2018-04-25 18:47:52 +0900 | [diff] [blame] | 205 | imply DISTRO_DEFAULTS |
Masahiro Yamada | acede7a | 2017-12-04 12:37:00 +0900 | [diff] [blame] | 206 | imply PANIC_HANG |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 207 | |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 208 | config ARCH_LX2160A |
| 209 | bool |
| 210 | select ARMV8_SET_SMPEN |
| 211 | select FSL_LSCH3 |
| 212 | select NXP_LSCH3_2 |
| 213 | select SYS_HAS_SERDES |
| 214 | select SYS_FSL_SRDS_1 |
| 215 | select SYS_FSL_SRDS_2 |
| 216 | select SYS_NXP_SRDS_3 |
| 217 | select SYS_FSL_DDR |
| 218 | select SYS_FSL_DDR_LE |
| 219 | select SYS_FSL_DDR_VER_50 |
| 220 | select SYS_FSL_EC1 |
| 221 | select SYS_FSL_EC2 |
Ran Wang | d0270dc | 2019-11-26 11:40:40 +0800 | [diff] [blame] | 222 | select SYS_FSL_ERRATUM_A050106 |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 223 | select SYS_FSL_HAS_RGMII |
| 224 | select SYS_FSL_HAS_SEC |
| 225 | select SYS_FSL_HAS_CCN508 |
| 226 | select SYS_FSL_HAS_DDR4 |
| 227 | select SYS_FSL_SEC_COMPAT_5 |
| 228 | select SYS_FSL_SEC_LE |
| 229 | select ARCH_EARLY_INIT_R |
| 230 | select BOARD_EARLY_INIT_F |
| 231 | select SYS_I2C_MXC |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 232 | imply DISTRO_DEFAULTS |
| 233 | imply PANIC_HANG |
| 234 | imply SCSI |
| 235 | imply SCSI_AHCI |
| 236 | |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 237 | config FSL_LSCH2 |
| 238 | bool |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 239 | select SYS_FSL_HAS_CCI400 |
York Sun | 92c36e2 | 2016-12-28 08:43:30 -0800 | [diff] [blame] | 240 | select SYS_FSL_HAS_SEC |
| 241 | select SYS_FSL_SEC_COMPAT_5 |
York Sun | fa419942 | 2016-12-28 08:43:31 -0800 | [diff] [blame] | 242 | select SYS_FSL_SEC_BE |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 243 | |
| 244 | config FSL_LSCH3 |
Alex Marginean | 47568ce | 2020-01-11 01:05:40 +0200 | [diff] [blame] | 245 | select ARCH_MISC_INIT |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 246 | bool |
| 247 | |
Priyanka Jain | 88c2566 | 2018-10-29 09:11:29 +0000 | [diff] [blame] | 248 | config NXP_LSCH3_2 |
| 249 | bool |
| 250 | |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 251 | menu "Layerscape architecture" |
| 252 | depends on FSL_LSCH2 || FSL_LSCH3 |
York Sun | fcd0e74 | 2016-10-04 14:31:47 -0700 | [diff] [blame] | 253 | |
Rajesh Bhagat | 52d237a | 2019-01-25 13:36:26 +0000 | [diff] [blame] | 254 | config FSL_LAYERSCAPE |
| 255 | bool |
| 256 | |
Wenbin Song | a8f57a9 | 2017-01-17 18:31:15 +0800 | [diff] [blame] | 257 | config HAS_FEATURE_GIC64K_ALIGN |
| 258 | bool |
| 259 | default y if ARCH_LS1043A |
| 260 | |
Wenbin Song | c6bc7c0 | 2017-01-17 18:31:16 +0800 | [diff] [blame] | 261 | config HAS_FEATURE_ENHANCED_MSI |
| 262 | bool |
| 263 | default y if ARCH_LS1043A |
Wenbin Song | a8f57a9 | 2017-01-17 18:31:15 +0800 | [diff] [blame] | 264 | |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 265 | menu "Layerscape PPA" |
| 266 | config FSL_LS_PPA |
| 267 | bool "FSL Layerscape PPA firmware support" |
macro.wave.z@gmail.com | 01bd334 | 2016-12-08 11:58:22 +0800 | [diff] [blame] | 268 | depends on !ARMV8_PSCI |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 269 | select ARMV8_SEC_FIRMWARE_SUPPORT |
Hou Zhiqiang | 6be115d | 2017-01-16 17:31:48 +0800 | [diff] [blame] | 270 | select SEC_FIRMWARE_ARMV8_PSCI |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 271 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 272 | help |
| 273 | The FSL Primary Protected Application (PPA) is a software component |
| 274 | which is loaded during boot stage, and then remains resident in RAM |
| 275 | and runs in the TrustZone after boot. |
| 276 | Say y to enable it. |
York Sun | f2aaf84 | 2017-05-15 08:52:00 -0700 | [diff] [blame] | 277 | |
| 278 | config SPL_FSL_LS_PPA |
| 279 | bool "FSL Layerscape PPA firmware support for SPL build" |
| 280 | depends on !ARMV8_PSCI |
| 281 | select SPL_ARMV8_SEC_FIRMWARE_SUPPORT |
| 282 | select SEC_FIRMWARE_ARMV8_PSCI |
| 283 | select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 |
| 284 | help |
| 285 | The FSL Primary Protected Application (PPA) is a software component |
| 286 | which is loaded during boot stage, and then remains resident in RAM |
| 287 | and runs in the TrustZone after boot. This is to load PPA during SPL |
| 288 | stage instead of the RAM version of U-Boot. Once PPA is initialized, |
| 289 | the rest of U-Boot (including RAM version) runs at EL2. |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 290 | choice |
| 291 | prompt "FSL Layerscape PPA firmware loading-media select" |
| 292 | depends on FSL_LS_PPA |
Hou Zhiqiang | bd6e2cd | 2017-03-17 16:12:33 +0800 | [diff] [blame] | 293 | default SYS_LS_PPA_FW_IN_MMC if SD_BOOT |
| 294 | default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 295 | default SYS_LS_PPA_FW_IN_XIP |
| 296 | |
| 297 | config SYS_LS_PPA_FW_IN_XIP |
| 298 | bool "XIP" |
| 299 | help |
| 300 | Say Y here if the PPA firmware locate at XIP flash, such |
| 301 | as NOR or QSPI flash. |
| 302 | |
Hou Zhiqiang | bd6e2cd | 2017-03-17 16:12:33 +0800 | [diff] [blame] | 303 | config SYS_LS_PPA_FW_IN_MMC |
| 304 | bool "eMMC or SD Card" |
| 305 | help |
| 306 | Say Y here if the PPA firmware locate at eMMC/SD card. |
| 307 | |
| 308 | config SYS_LS_PPA_FW_IN_NAND |
| 309 | bool "NAND" |
| 310 | help |
| 311 | Say Y here if the PPA firmware locate at NAND flash. |
| 312 | |
Hou Zhiqiang | bff56d5 | 2017-01-16 17:31:49 +0800 | [diff] [blame] | 313 | endchoice |
| 314 | |
Sumit Garg | 8fddf75 | 2017-04-20 05:09:11 +0530 | [diff] [blame] | 315 | config LS_PPA_ESBC_HDR_SIZE |
| 316 | hex "Length of PPA ESBC header" |
| 317 | depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP |
| 318 | default 0x2000 |
| 319 | help |
| 320 | Length (in bytes) of PPA ESBC header to be copied from MMC/SD or |
| 321 | NAND to memory to validate PPA image. |
| 322 | |
macro.wave.z@gmail.com | ec2d7ed | 2016-12-08 11:58:21 +0800 | [diff] [blame] | 323 | endmenu |
| 324 | |
Ran Wang | e64f747 | 2017-09-04 18:46:50 +0800 | [diff] [blame] | 325 | config SYS_FSL_ERRATUM_A008997 |
| 326 | bool "Workaround for USB PHY erratum A008997" |
| 327 | |
Ran Wang | 3ba6948 | 2017-09-04 18:46:51 +0800 | [diff] [blame] | 328 | config SYS_FSL_ERRATUM_A009007 |
| 329 | bool |
| 330 | help |
| 331 | Workaround for USB PHY erratum A009007 |
| 332 | |
Ran Wang | b358b7b | 2017-09-04 18:46:48 +0800 | [diff] [blame] | 333 | config SYS_FSL_ERRATUM_A009008 |
| 334 | bool "Workaround for USB PHY erratum A009008" |
| 335 | |
Ran Wang | 9e8fabc | 2017-09-04 18:46:49 +0800 | [diff] [blame] | 336 | config SYS_FSL_ERRATUM_A009798 |
| 337 | bool "Workaround for USB PHY erratum A009798" |
| 338 | |
Ran Wang | d0270dc | 2019-11-26 11:40:40 +0800 | [diff] [blame] | 339 | config SYS_FSL_ERRATUM_A050106 |
| 340 | bool "Workaround for USB PHY erratum A050106" |
| 341 | help |
| 342 | USB3.0 Receiver needs to enable fixed equalization |
| 343 | for each of PHY instances in an SOC. This is similar |
| 344 | to erratum A-009007, but this one is for LX2160A, |
| 345 | and the register value is different. |
| 346 | |
York Sun | 149eb33 | 2016-09-26 08:09:27 -0700 | [diff] [blame] | 347 | config SYS_FSL_ERRATUM_A010315 |
| 348 | bool "Workaround for PCIe erratum A010315" |
Hou Zhiqiang | c06b30a | 2016-09-29 12:42:44 +0800 | [diff] [blame] | 349 | |
| 350 | config SYS_FSL_ERRATUM_A010539 |
| 351 | bool "Workaround for PIN MUX erratum A010539" |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 352 | |
York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 353 | config MAX_CPUS |
| 354 | int "Maximum number of CPUs permitted for Layerscape" |
Yuantian Tang | 4aefa16 | 2019-04-10 16:43:33 +0800 | [diff] [blame] | 355 | default 2 if ARCH_LS1028A |
York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 356 | default 4 if ARCH_LS1043A |
| 357 | default 4 if ARCH_LS1046A |
| 358 | default 16 if ARCH_LS2080A |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 359 | default 8 if ARCH_LS1088A |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 360 | default 16 if ARCH_LX2160A |
York Sun | f188d22 | 2016-10-04 14:45:01 -0700 | [diff] [blame] | 361 | default 1 |
| 362 | help |
| 363 | Set this number to the maximum number of possible CPUs in the SoC. |
| 364 | SoCs may have multiple clusters with each cluster may have multiple |
| 365 | ports. If some ports are reserved but higher ports are used for |
| 366 | cores, count the reserved ports. This will allocate enough memory |
| 367 | in spin table to properly handle all cores. |
| 368 | |
Meenakshi Aggarwal | bbd3318 | 2018-11-30 22:32:11 +0530 | [diff] [blame] | 369 | config EMC2305 |
| 370 | bool "Fan controller" |
| 371 | help |
| 372 | Enable the EMC2305 fan controller for configuration of fan |
| 373 | speed. |
| 374 | |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 375 | config NXP_ESBC |
| 376 | bool "NXP_ESBC" |
York Sun | 728e700 | 2016-12-02 09:32:35 -0800 | [diff] [blame] | 377 | help |
| 378 | Enable Freescale Secure Boot feature |
| 379 | |
Yuan Yao | 52ae4fd | 2016-12-01 10:13:52 +0800 | [diff] [blame] | 380 | config QSPI_AHB_INIT |
| 381 | bool "Init the QSPI AHB bus" |
| 382 | help |
| 383 | The default setting for QSPI AHB bus just support 3bytes addressing. |
| 384 | But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB |
| 385 | bus for those flashes to support the full QSPI flash size. |
| 386 | |
Kuldeep Singh | 34aafb0 | 2019-11-21 17:15:17 +0530 | [diff] [blame] | 387 | config FSPI_AHB_EN_4BYTE |
| 388 | bool "Enable 4-byte Fast Read command for AHB mode" |
| 389 | default n |
| 390 | help |
| 391 | The default setting for FlexSPI AHB bus just supports 3-byte addressing. |
| 392 | But some FlexSPI flash sizes are up to 64MBytes. |
| 393 | This flag enables fast read command for AHB mode and modifies required |
| 394 | LUT to support full FlexSPI flash. |
| 395 | |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 396 | config SYS_CCI400_OFFSET |
| 397 | hex "Offset for CCI400 base" |
| 398 | depends on SYS_FSL_HAS_CCI400 |
Yuantian Tang | 4aefa16 | 2019-04-10 16:43:33 +0800 | [diff] [blame] | 399 | default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 400 | default 0x180000 if FSL_LSCH2 |
| 401 | help |
| 402 | Offset for CCI400 base |
| 403 | CCI400 base addr = CCSRBAR + CCI400_OFFSET |
| 404 | |
York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 405 | config SYS_FSL_IFC_BANK_COUNT |
| 406 | int "Maximum banks of Integrated flash controller" |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 407 | depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A |
York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 408 | default 4 if ARCH_LS1043A |
| 409 | default 4 if ARCH_LS1046A |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 410 | default 8 if ARCH_LS2080A || ARCH_LS1088A |
York Sun | e7310a3 | 2016-10-04 14:45:54 -0700 | [diff] [blame] | 411 | |
Ashish Kumar | 1123406 | 2017-08-11 11:09:14 +0530 | [diff] [blame] | 412 | config SYS_FSL_HAS_CCI400 |
| 413 | bool |
| 414 | |
Ashish Kumar | 97393d6 | 2017-08-18 10:54:36 +0530 | [diff] [blame] | 415 | config SYS_FSL_HAS_CCN504 |
| 416 | bool |
| 417 | |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 418 | config SYS_FSL_HAS_CCN508 |
| 419 | bool |
| 420 | |
York Sun | 0dc9abb | 2016-10-04 14:46:50 -0700 | [diff] [blame] | 421 | config SYS_FSL_HAS_DP_DDR |
| 422 | bool |
| 423 | |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 424 | config SYS_FSL_SRDS_1 |
| 425 | bool |
| 426 | |
| 427 | config SYS_FSL_SRDS_2 |
| 428 | bool |
| 429 | |
Priyanka Jain | 1a60253 | 2018-09-27 10:32:05 +0530 | [diff] [blame] | 430 | config SYS_NXP_SRDS_3 |
| 431 | bool |
| 432 | |
York Sun | 6b62ef0 | 2016-10-04 18:01:34 -0700 | [diff] [blame] | 433 | config SYS_HAS_SERDES |
| 434 | bool |
| 435 | |
Ashish kumar | 76bd6ce | 2017-04-07 11:40:32 +0530 | [diff] [blame] | 436 | config FSL_TZASC_1 |
| 437 | bool |
| 438 | |
| 439 | config FSL_TZASC_2 |
| 440 | bool |
| 441 | |
Rajesh Bhagat | 5756f7e | 2019-01-20 05:30:06 +0000 | [diff] [blame] | 442 | config FSL_TZASC_400 |
| 443 | bool |
| 444 | |
| 445 | config FSL_TZPC_BP147 |
| 446 | bool |
York Sun | 4dd8c61 | 2016-10-04 14:31:48 -0700 | [diff] [blame] | 447 | endmenu |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 448 | |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 449 | menu "Layerscape clock tree configuration" |
| 450 | depends on FSL_LSCH2 || FSL_LSCH3 |
| 451 | |
| 452 | config SYS_FSL_CLK |
| 453 | bool "Enable clock tree initialization" |
| 454 | default y |
| 455 | |
| 456 | config CLUSTER_CLK_FREQ |
| 457 | int "Reference clock of core cluster" |
| 458 | depends on ARCH_LS1012A |
| 459 | default 100000000 |
| 460 | help |
| 461 | This number is the reference clock frequency of core PLL. |
| 462 | For most platforms, the core PLL and Platform PLL have the same |
| 463 | reference clock, but for some platforms, LS1012A for instance, |
| 464 | they are provided sepatately. |
| 465 | |
| 466 | config SYS_FSL_PCLK_DIV |
| 467 | int "Platform clock divider" |
Yuantian Tang | 4aefa16 | 2019-04-10 16:43:33 +0800 | [diff] [blame] | 468 | default 1 if ARCH_LS1028A |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 469 | default 1 if ARCH_LS1043A |
| 470 | default 1 if ARCH_LS1046A |
Ashish Kumar | b25faa2 | 2017-08-31 16:12:53 +0530 | [diff] [blame] | 471 | default 1 if ARCH_LS1088A |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 472 | default 2 |
| 473 | help |
| 474 | This is the divider that is used to derive Platform clock from |
| 475 | Platform PLL, in another word: |
| 476 | Platform_clk = Platform_PLL_freq / this_divider |
| 477 | |
| 478 | config SYS_FSL_DSPI_CLK_DIV |
| 479 | int "DSPI clock divider" |
| 480 | default 1 if ARCH_LS1043A |
| 481 | default 2 |
| 482 | help |
| 483 | This is the divider that is used to derive DSPI clock from Platform |
Hou Zhiqiang | 0c8fcb6 | 2017-07-03 18:37:11 +0800 | [diff] [blame] | 484 | clock, in another word DSPI_clk = Platform_clk / this_divider. |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 485 | |
| 486 | config SYS_FSL_DUART_CLK_DIV |
| 487 | int "DUART clock divider" |
| 488 | default 1 if ARCH_LS1043A |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 489 | default 4 if ARCH_LX2160A |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 490 | default 2 |
| 491 | help |
| 492 | This is the divider that is used to derive DUART clock from Platform |
| 493 | clock, in another word DUART_clk = Platform_clk / this_divider. |
| 494 | |
| 495 | config SYS_FSL_I2C_CLK_DIV |
| 496 | int "I2C clock divider" |
| 497 | default 1 if ARCH_LS1043A |
Chuanhua Han | 44d4d33 | 2019-08-02 16:53:53 +0800 | [diff] [blame] | 498 | default 4 if ARCH_LS1012A |
| 499 | default 4 if ARCH_LS1028A |
| 500 | default 8 if ARCH_LX2160A |
| 501 | default 8 if ARCH_LS1088A |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 502 | default 2 |
| 503 | help |
| 504 | This is the divider that is used to derive I2C clock from Platform |
| 505 | clock, in another word I2C_clk = Platform_clk / this_divider. |
| 506 | |
| 507 | config SYS_FSL_IFC_CLK_DIV |
| 508 | int "IFC clock divider" |
| 509 | default 1 if ARCH_LS1043A |
Chuanhua Han | 3df89cc | 2019-08-08 17:04:58 +0800 | [diff] [blame] | 510 | default 4 if ARCH_LS1012A |
| 511 | default 4 if ARCH_LS1028A |
| 512 | default 8 if ARCH_LX2160A |
| 513 | default 8 if ARCH_LS1088A |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 514 | default 2 |
| 515 | help |
| 516 | This is the divider that is used to derive IFC clock from Platform |
| 517 | clock, in another word IFC_clk = Platform_clk / this_divider. |
| 518 | |
| 519 | config SYS_FSL_LPUART_CLK_DIV |
| 520 | int "LPUART clock divider" |
| 521 | default 1 if ARCH_LS1043A |
| 522 | default 2 |
| 523 | help |
| 524 | This is the divider that is used to derive LPUART clock from Platform |
| 525 | clock, in another word LPUART_clk = Platform_clk / this_divider. |
| 526 | |
| 527 | config SYS_FSL_SDHC_CLK_DIV |
| 528 | int "SDHC clock divider" |
| 529 | default 1 if ARCH_LS1043A |
| 530 | default 1 if ARCH_LS1012A |
| 531 | default 2 |
| 532 | help |
| 533 | This is the divider that is used to derive SDHC clock from Platform |
| 534 | clock, in another word SDHC_clk = Platform_clk / this_divider. |
Hou Zhiqiang | fef32c6 | 2018-04-25 16:28:44 +0800 | [diff] [blame] | 535 | |
| 536 | config SYS_FSL_QMAN_CLK_DIV |
| 537 | int "QMAN clock divider" |
| 538 | default 1 if ARCH_LS1043A |
| 539 | default 2 |
| 540 | help |
| 541 | This is the divider that is used to derive QMAN clock from Platform |
| 542 | clock, in another word QMAN_clk = Platform_clk / this_divider. |
Hou Zhiqiang | 3f91cda | 2017-01-10 16:44:15 +0800 | [diff] [blame] | 543 | endmenu |
| 544 | |
York Sun | d6964b3 | 2017-03-06 09:02:24 -0800 | [diff] [blame] | 545 | config RESV_RAM |
| 546 | bool |
| 547 | help |
| 548 | Reserve memory from the top, tracked by gd->arch.resv_ram. This |
| 549 | reserved RAM can be used by special driver that resides in memory |
| 550 | after U-Boot exits. It's up to implementation to allocate and allow |
| 551 | access to this reserved memory. For example, the reserved RAM can |
| 552 | be at the high end of physical memory. The reserve RAM may be |
| 553 | excluded from memory bank(s) passed to OS, or marked as reserved. |
| 554 | |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 555 | config SYS_FSL_EC1 |
| 556 | bool |
| 557 | help |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 558 | Ethernet controller 1, this is connected to |
| 559 | MAC17 for LX2160A or to MAC3 for other SoCs |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 560 | Provides DPAA2 capabilities |
| 561 | |
| 562 | config SYS_FSL_EC2 |
| 563 | bool |
| 564 | help |
Priyanka Jain | ef76b2e | 2018-10-29 09:17:09 +0000 | [diff] [blame] | 565 | Ethernet controller 2, this is connected to |
| 566 | MAC18 for LX2160A or to MAC4 for other SoCs |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 567 | Provides DPAA2 capabilities |
| 568 | |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 569 | config SYS_FSL_ERRATUM_A008336 |
| 570 | bool |
| 571 | |
| 572 | config SYS_FSL_ERRATUM_A008514 |
| 573 | bool |
| 574 | |
| 575 | config SYS_FSL_ERRATUM_A008585 |
| 576 | bool |
| 577 | |
| 578 | config SYS_FSL_ERRATUM_A008850 |
| 579 | bool |
| 580 | |
Ashish kumar | 3b52a23 | 2017-02-23 16:03:57 +0530 | [diff] [blame] | 581 | config SYS_FSL_ERRATUM_A009203 |
| 582 | bool |
| 583 | |
York Sun | 1dc61ca | 2016-12-28 08:43:41 -0800 | [diff] [blame] | 584 | config SYS_FSL_ERRATUM_A009635 |
| 585 | bool |
| 586 | |
| 587 | config SYS_FSL_ERRATUM_A009660 |
| 588 | bool |
| 589 | |
| 590 | config SYS_FSL_ERRATUM_A009929 |
| 591 | bool |
York Sun | 1a77075 | 2017-03-06 09:02:26 -0800 | [diff] [blame] | 592 | |
Laurentiu Tudor | 7ea2feb | 2019-10-18 09:01:56 +0000 | [diff] [blame] | 593 | config SYS_FSL_ERRATUM_A050382 |
| 594 | bool |
Ashish Kumar | ec455e2 | 2017-08-31 16:37:31 +0530 | [diff] [blame] | 595 | |
| 596 | config SYS_FSL_HAS_RGMII |
| 597 | bool |
| 598 | depends on SYS_FSL_EC1 || SYS_FSL_EC2 |
| 599 | |
Philipp Tomsich | 2d6a0cc | 2017-08-03 23:23:55 +0200 | [diff] [blame] | 600 | config SPL_LDSCRIPT |
| 601 | default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A |
Ran Wang | 5959f84 | 2017-10-23 10:09:21 +0800 | [diff] [blame] | 602 | |
| 603 | config HAS_FSL_XHCI_USB |
| 604 | bool |
| 605 | default y if ARCH_LS1043A || ARCH_LS1046A |
| 606 | help |
| 607 | For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use |
| 608 | pins, select it when the pins are assigned to USB. |