armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 650ac94..2b086da 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -170,6 +170,42 @@
imply DISTRO_DEFAULTS
imply PANIC_HANG
+config ARCH_LX2160A
+ bool
+ select ARMV8_SET_SMPEN
+ select FSL_LSCH3
+ select NXP_LSCH3_2
+ select SYS_HAS_SERDES
+ select SYS_FSL_SRDS_1
+ select SYS_FSL_SRDS_2
+ select SYS_NXP_SRDS_3
+ select SYS_FSL_DDR
+ select SYS_FSL_DDR_LE
+ select SYS_FSL_DDR_VER_50
+ select SYS_FSL_EC1
+ select SYS_FSL_EC2
+ select SYS_FSL_HAS_RGMII
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_HAS_CCN508
+ select SYS_FSL_HAS_DDR4
+ select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
+ select SYS_I2C_MXC
+ select SYS_I2C_MXC_I2C1
+ select SYS_I2C_MXC_I2C2
+ select SYS_I2C_MXC_I2C3
+ select SYS_I2C_MXC_I2C4
+ select SYS_I2C_MXC_I2C5
+ select SYS_I2C_MXC_I2C6
+ select SYS_I2C_MXC_I2C7
+ select SYS_I2C_MXC_I2C8
+ imply DISTRO_DEFAULTS
+ imply PANIC_HANG
+ imply SCSI
+ imply SCSI_AHCI
+
config FSL_LSCH2
bool
select SYS_FSL_HAS_CCI400
@@ -185,7 +221,7 @@
config FSL_MC_ENET
bool "Management Complex network"
- depends on ARCH_LS2080A || ARCH_LS1088A
+ depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
default y
select RESV_RAM
help
@@ -202,6 +238,7 @@
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
default "fsl,ls1088a-pcie" if ARCH_LS1088A
+ default "fsl,lx2160a-pcie" if ARCH_LX2160A
help
This compatible is used to find pci controller node in Kernel DT
to complete fixup.
@@ -300,6 +337,7 @@
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
default 8 if ARCH_LS1088A
+ default 16 if ARCH_LX2160A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
@@ -342,6 +380,9 @@
config SYS_FSL_HAS_CCN504
bool
+config SYS_FSL_HAS_CCN508
+ bool
+
config SYS_FSL_HAS_DP_DDR
bool
@@ -404,6 +445,7 @@
config SYS_FSL_DUART_CLK_DIV
int "DUART clock divider"
default 1 if ARCH_LS1043A
+ default 4 if ARCH_LX2160A
default 2
help
This is the divider that is used to derive DUART clock from Platform
@@ -464,13 +506,15 @@
config SYS_FSL_EC1
bool
help
- Ethernet controller 1, this is connected to MAC3.
+ Ethernet controller 1, this is connected to
+ MAC17 for LX2160A or to MAC3 for other SoCs
Provides DPAA2 capabilities
config SYS_FSL_EC2
bool
help
- Ethernet controller 2, this is connected to MAC4.
+ Ethernet controller 2, this is connected to
+ MAC18 for LX2160A or to MAC4 for other SoCs
Provides DPAA2 capabilities
config SYS_FSL_ERRATUM_A008336
@@ -506,7 +550,7 @@
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
- default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
+ default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.