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Simon Glass2cffe662015-08-30 16:55:38 -06001if ARCH_ROCKCHIP
2
Heiko Stuebnerfc367852019-07-16 22:18:21 +02003config ROCKCHIP_PX30
4 bool "Support Rockchip PX30"
5 select ARM64
6 select SUPPORT_SPL
7 select SUPPORT_TPL
8 select SPL
9 select TPL
10 select TPL_TINY_FRAMEWORK if TPL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020011 select TPL_NEEDS_SEPARATE_STACK if TPL
12 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -060013 select SPL_SERIAL
14 select TPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020015 select DEBUG_UART_BOARD_INIT
16 imply ROCKCHIP_COMMON_BOARD
17 imply SPL_ROCKCHIP_COMMON_BOARD
18 help
19 The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
20 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 and video codec support. Peripherals include Gigabit Ethernet,
22 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020024config ROCKCHIP_RK3036
25 bool "Support Rockchip RK3036"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053026 select CPU_V7A
Kever Yang0d3d7832016-07-19 21:16:59 +080027 select SUPPORT_SPL
28 select SPL
Eddie Caia79b78f2018-01-17 09:51:41 +080029 imply USB_FUNCTION_ROCKUSB
30 imply CMD_ROCKUSB
Kever Yang427cb672019-07-22 20:02:04 +080031 imply ROCKCHIP_COMMON_BOARD
Heiko Stübner5c91e2b2016-07-16 00:17:15 +020032 help
33 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
34 including NEON and GPU, Mali-400 graphics, several DDR3 options
35 and video codec support. Peripherals include Gigabit Ethernet,
36 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
37
Johan Jonkera289fc72022-04-16 17:09:47 +020038config ROCKCHIP_RK3066
39 bool "Support Rockchip RK3066"
40 select CPU_V7A
41 select SPL_BOARD_INIT if SPL
42 select SUPPORT_SPL
43 select SUPPORT_TPL
44 select SPL
45 select TPL
46 select TPL_ROCKCHIP_BACK_TO_BROM
47 select TPL_ROCKCHIP_EARLYRETURN_TO_BROM
48 imply ROCKCHIP_COMMON_BOARD
49 imply SPL_ROCKCHIP_COMMON_BOARD
50 imply SPL_SERIAL
51 imply TPL_ROCKCHIP_COMMON_BOARD
52 imply TPL_SERIAL
53 help
54 The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9
55 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
56 video interfaces, several memory options and video codec support.
57 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
58 UART, SPI, I2C and PWMs.
59
Kever Yangaa827752017-11-28 16:04:16 +080060config ROCKCHIP_RK3128
61 bool "Support Rockchip RK3128"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053062 select CPU_V7A
Kever Yang96362722019-07-22 20:02:05 +080063 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa827752017-11-28 16:04:16 +080064 help
65 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
66 including NEON and GPU, Mali-400 graphics, several DDR3 options
67 and video codec support. Peripherals include Gigabit Ethernet,
68 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
69
Heiko Stübneref6db5e2017-02-18 19:46:36 +010070config ROCKCHIP_RK3188
71 bool "Support Rockchip RK3188"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053072 select CPU_V7A
Ley Foon Tan48fcc4a2017-05-03 17:13:32 +080073 select SPL_BOARD_INIT if SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010074 select SUPPORT_SPL
Heiko Stübneref6db5e2017-02-18 19:46:36 +010075 select SPL
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020076 select SPL_CLK
Philipp Tomsich5aa3f9d2017-10-10 16:21:17 +020077 select SPL_REGMAP
78 select SPL_SYSCON
79 select SPL_RAM
Simon Glass284cb9c2021-07-10 21:14:31 -060080 select SPL_DRIVERS_MISC
Philipp Tomsich16c689c2017-10-10 16:21:15 +020081 select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
Kever Yangbd8532e2019-07-22 19:59:15 +080082 select SPL_ROCKCHIP_BACK_TO_BROM
Heiko Stübner015f69a2017-04-06 00:19:36 +020083 select BOARD_LATE_INIT
Kever Yangbfd3f872019-07-22 20:02:09 +080084 imply ROCKCHIP_COMMON_BOARD
Kever Yang3bd90402019-07-22 19:59:18 +080085 imply SPL_ROCKCHIP_COMMON_BOARD
Heiko Stübneref6db5e2017-02-18 19:46:36 +010086 help
87 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
88 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
89 video interfaces, several memory options and video codec support.
90 Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
91 UART, SPI, I2C and PWMs.
92
Kever Yang57d4dbf2017-06-23 17:17:52 +080093config ROCKCHIP_RK322X
94 bool "Support Rockchip RK3228/RK3229"
Lokesh Vutla81b1a672018-04-26 18:21:26 +053095 select CPU_V7A
Kever Yang57d4dbf2017-06-23 17:17:52 +080096 select SUPPORT_SPL
Kever Yangaff40c62019-04-02 20:41:24 +080097 select SUPPORT_TPL
Kever Yang57d4dbf2017-06-23 17:17:52 +080098 select SPL
Kever Yangaff40c62019-04-02 20:41:24 +080099 select SPL_DM
100 select SPL_OF_LIBFDT
101 select TPL
102 select TPL_DM
103 select TPL_OF_LIBFDT
Kever Yangaff40c62019-04-02 20:41:24 +0800104 select TPL_NEEDS_SEPARATE_STACK if TPL
Simon Glass284cb9c2021-07-10 21:14:31 -0600105 select SPL_DRIVERS_MISC
Kever Yang0b517732019-07-22 20:02:07 +0800106 imply ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600107 imply SPL_SERIAL
Kever Yangd877fd22019-07-22 19:59:20 +0800108 imply SPL_ROCKCHIP_COMMON_BOARD
Alex Bee4fe31122023-07-18 16:57:13 +0200109 select SPL_OPTEE_IMAGE if SPL_FIT
Simon Glassf4d60392021-08-08 12:20:12 -0600110 imply TPL_SERIAL
Kever Yang466f3fd2019-07-09 22:05:56 +0800111 imply TPL_ROCKCHIP_COMMON_BOARD
Kever Yangaff40c62019-04-02 20:41:24 +0800112 select TPL_LIBCOMMON_SUPPORT
113 select TPL_LIBGENERIC_SUPPORT
Kever Yang57d4dbf2017-06-23 17:17:52 +0800114 help
115 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
116 including NEON and GPU, Mali-400 graphics, several DDR3 options
117 and video codec support. Peripherals include Gigabit Ethernet,
118 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
119
Simon Glass2cffe662015-08-30 16:55:38 -0600120config ROCKCHIP_RK3288
121 bool "Support Rockchip RK3288"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530122 select CPU_V7A
John Keepingd5cb7712023-02-23 19:28:51 +0000123 select OF_SYSTEM_SETUP
Tom Rinie1e85442021-08-27 21:18:30 -0400124 select SKIP_LOWLEVEL_INIT_ONLY
Kever Yang0d3d7832016-07-19 21:16:59 +0800125 select SUPPORT_SPL
126 select SPL
Kever Yangf7c0a332019-07-02 11:43:05 +0800127 select SUPPORT_TPL
Johan Jonker9a26fb12023-12-27 13:06:47 +0100128 select FDT_64BIT
Jagan Teki7b7cc952020-01-23 19:42:19 +0530129 imply PRE_CONSOLE_BUFFER
Kever Yangba875012019-07-22 20:02:15 +0800130 imply ROCKCHIP_COMMON_BOARD
Kever Yangaa67deb2019-07-22 19:59:27 +0800131 imply SPL_ROCKCHIP_COMMON_BOARD
Kever Yangf7c0a332019-07-02 11:43:05 +0800132 imply TPL_CLK
133 imply TPL_DM
Simon Glass284cb9c2021-07-10 21:14:31 -0600134 imply TPL_DRIVERS_MISC
Kever Yangf7c0a332019-07-02 11:43:05 +0800135 imply TPL_LIBCOMMON_SUPPORT
136 imply TPL_LIBGENERIC_SUPPORT
Kever Yangb36e7092019-07-02 11:43:06 +0800137 imply TPL_NEEDS_SEPARATE_STACK
Kever Yangf7c0a332019-07-02 11:43:05 +0800138 imply TPL_OF_CONTROL
139 imply TPL_OF_PLATDATA
140 imply TPL_RAM
141 imply TPL_REGMAP
Kever Yange32f38e2019-07-09 22:05:57 +0800142 imply TPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600143 imply TPL_SERIAL
Kever Yangf7c0a332019-07-02 11:43:05 +0800144 imply TPL_SYSCON
Eddie Caib3501fe2017-12-15 08:17:13 +0800145 imply USB_FUNCTION_ROCKUSB
146 imply CMD_ROCKUSB
Simon Glass2cffe662015-08-30 16:55:38 -0600147 help
148 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
149 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
150 video interfaces supporting HDMI and eDP, several DDR3 options
151 and video codec support. Peripherals include Gigabit Ethernet,
Andreas Färber531e8e02016-11-02 18:03:01 +0100152 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
Simon Glass2cffe662015-08-30 16:55:38 -0600153
Andy Yanb5e16302019-11-14 11:21:12 +0800154config ROCKCHIP_RK3308
155 bool "Support Rockchip RK3308"
156 select ARM64
Andy Yanb5e16302019-11-14 11:21:12 +0800157 select SUPPORT_SPL
158 select SUPPORT_TPL
159 select SPL
160 select SPL_ATF
161 select SPL_ATF_NO_PLATFORM_PARAM
162 select SPL_LOAD_FIT
163 imply ROCKCHIP_COMMON_BOARD
164 imply SPL_ROCKCHIP_COMMON_BOARD
165 imply SPL_CLK
166 imply SPL_REGMAP
167 imply SPL_SYSCON
168 imply SPL_RAM
Simon Glassf4d60392021-08-08 12:20:12 -0600169 imply SPL_SERIAL
Andy Yanb5e16302019-11-14 11:21:12 +0800170 imply SPL_SEPARATE_BSS
171 help
172 The Rockchip RK3308 is a ARM-based Soc which embedded with quad
173 Cortex-A35 and highly integrated audio interfaces.
174
Kever Yangec02b3c2017-02-23 15:37:51 +0800175config ROCKCHIP_RK3328
176 bool "Support Rockchip RK3328"
177 select ARM64
Kever Yang07be6692019-06-09 00:27:15 +0300178 select SUPPORT_SPL
179 select SPL
Kever Yang69871852019-08-02 10:40:01 +0300180 select SUPPORT_TPL
181 select TPL
Kever Yang69871852019-08-02 10:40:01 +0300182 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang205e2cc2019-07-22 20:02:16 +0800183 imply ROCKCHIP_COMMON_BOARD
YouMin Chenb9f7df32019-11-15 11:04:44 +0800184 imply ROCKCHIP_SDRAM_COMMON
Kever Yangbb4c3252019-07-22 19:59:32 +0800185 imply SPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600186 imply SPL_SERIAL
187 imply TPL_SERIAL
Kever Yang07be6692019-06-09 00:27:15 +0300188 imply SPL_SEPARATE_BSS
189 select ENABLE_ARM_SOC_BOOT0_HOOK
190 select DEBUG_UART_BOARD_INIT
191 select SYS_NS16550
Chen-Yu Tsaibc261472024-02-12 21:51:04 +0800192 imply MISC
193 imply ROCKCHIP_EFUSE
194 imply MISC_INIT_R
Kever Yangec02b3c2017-02-23 15:37:51 +0800195 help
196 The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
197 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
198 video interfaces supporting HDMI and eDP, several DDR3 options
199 and video codec support. Peripherals include Gigabit Ethernet,
200 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
201
Andreas Färber9e3ad682017-05-15 17:51:18 +0800202config ROCKCHIP_RK3368
203 bool "Support Rockchip RK3368"
204 select ARM64
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200205 select SUPPORT_SPL
206 select SUPPORT_TPL
Philipp Tomsich01b219e2017-07-28 20:03:07 +0200207 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang35b401e2019-07-22 20:02:17 +0800208 imply ROCKCHIP_COMMON_BOARD
Kever Yang8bf7ed42019-07-22 19:59:34 +0800209 imply SPL_ROCKCHIP_COMMON_BOARD
Philipp Tomsich84af43e2017-06-11 23:46:25 +0200210 imply SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600211 imply SPL_SERIAL
212 imply TPL_SERIAL
Kever Yang48831b22019-07-09 22:05:58 +0800213 imply TPL_ROCKCHIP_COMMON_BOARD
Andreas Färber9e3ad682017-05-15 17:51:18 +0800214 help
Philipp Tomsich9f3deaf2017-06-10 00:47:53 +0200215 The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
216 into a big and little cluster with 4 cores each) Cortex-A53 including
217 AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
218 (for the little cluster), PowerVR G6110 based graphics, one video
219 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
220 video codec support.
221
222 On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
223 I2S, UARTs, SPI, I2C and PWMs.
Andreas Färber9e3ad682017-05-15 17:51:18 +0800224
Kever Yang0d3d7832016-07-19 21:16:59 +0800225config ROCKCHIP_RK3399
226 bool "Support Rockchip RK3399"
227 select ARM64
Kever Yang16efdfd2017-02-22 16:56:38 +0800228 select SUPPORT_SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800229 select SUPPORT_TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800230 select SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530231 select SPL_ATF
Jagan Tekice063b92019-06-21 00:25:03 +0530232 select SPL_BOARD_INIT if SPL
Jagan Tekicd433892019-05-08 11:11:43 +0530233 select SPL_LOAD_FIT
234 select SPL_CLK if SPL
235 select SPL_PINCTRL if SPL
236 select SPL_RAM if SPL
237 select SPL_REGMAP if SPL
238 select SPL_SYSCON if SPL
Kever Yangfca798d2018-11-09 11:18:15 +0800239 select TPL_NEEDS_SEPARATE_STACK if TPL
Kever Yang16efdfd2017-02-22 16:56:38 +0800240 select SPL_SEPARATE_BSS
Simon Glassf4d60392021-08-08 12:20:12 -0600241 select SPL_SERIAL
Simon Glass284cb9c2021-07-10 21:14:31 -0600242 select SPL_DRIVERS_MISC
Jagan Tekicd433892019-05-08 11:11:43 +0530243 select CLK
244 select FIT
245 select PINCTRL
246 select RAM
247 select REGMAP
248 select SYSCON
249 select DM_PMIC
250 select DM_REGULATOR_FIXED
Andy Yan70378cb2017-10-11 15:00:16 +0800251 select BOARD_LATE_INIT
Sughosh Ganuc1b8e8b2022-11-10 14:49:15 +0530252 imply PARTITION_TYPE_GUID
Jagan Teki9249d5c2020-04-02 17:11:23 +0530253 imply PRE_CONSOLE_BUFFER
Kever Yang9554a4e2019-07-22 20:02:19 +0800254 imply ROCKCHIP_COMMON_BOARD
YouMin Chen23ae72e2019-11-15 11:04:45 +0800255 imply ROCKCHIP_SDRAM_COMMON
Kever Yangff9afe42019-07-22 19:59:42 +0800256 imply SPL_ROCKCHIP_COMMON_BOARD
Simon Glassf4d60392021-08-08 12:20:12 -0600257 imply TPL_SERIAL
Kever Yangfca798d2018-11-09 11:18:15 +0800258 imply TPL_LIBCOMMON_SUPPORT
259 imply TPL_LIBGENERIC_SUPPORT
260 imply TPL_SYS_MALLOC_SIMPLE
Simon Glass284cb9c2021-07-10 21:14:31 -0600261 imply TPL_DRIVERS_MISC
Kever Yangfca798d2018-11-09 11:18:15 +0800262 imply TPL_OF_CONTROL
263 imply TPL_DM
264 imply TPL_REGMAP
265 imply TPL_SYSCON
266 imply TPL_RAM
267 imply TPL_CLK
268 imply TPL_TINY_MEMSET
Kever Yang3cfbb942019-07-09 22:06:01 +0800269 imply TPL_ROCKCHIP_COMMON_BOARD
Jagan Tekie7043012020-01-09 14:22:19 +0530270 imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
Shantur Rathorec0009892024-01-21 22:04:47 +0000271 imply BOOTSTD_FULL
Jagan Tekie7043012020-01-09 14:22:19 +0530272 imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
Chen-Yu Tsai3ccaa1d2024-02-12 21:51:05 +0800273 imply MISC
274 imply ROCKCHIP_EFUSE
275 imply MISC_INIT_R
Kever Yang0d3d7832016-07-19 21:16:59 +0800276 help
277 The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
278 and quad-core Cortex-A53.
279 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
280 video interfaces supporting HDMI and eDP, several DDR3 options
281 and video codec support. Peripherals include Gigabit Ethernet,
282 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
283
Joseph Chen72cd8792021-06-02 15:58:25 +0800284config ROCKCHIP_RK3568
285 bool "Support Rockchip RK3568"
286 select ARM64
Nico Cheng00ceeb02021-10-26 10:42:19 +0800287 select SUPPORT_SPL
288 select SPL
Joseph Chen72cd8792021-06-02 15:58:25 +0800289 select CLK
290 select PINCTRL
291 select RAM
292 select REGMAP
293 select SYSCON
294 select BOARD_LATE_INIT
Manoj Saib34b19c2023-02-17 17:28:44 +0530295 select DM_REGULATOR_FIXED
Jagan Tekice0bbac2023-02-17 17:28:34 +0530296 select DM_RESET
Jonas Karlman47af53c2023-04-17 19:07:15 +0000297 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Joseph Chen72cd8792021-06-02 15:58:25 +0800298 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmanf4d27e92023-04-17 19:07:17 +0000299 imply OF_LIBFDT_OVERLAY
Jonas Karlmanbe56bb52023-02-22 22:44:41 +0000300 imply ROCKCHIP_OTP
301 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000302 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
303 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Joseph Chen72cd8792021-06-02 15:58:25 +0800304 help
305 The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
306 including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
307 two video interfaces supporting HDMI and eDP, several DDR3 options
308 and video codec support. Peripherals include Gigabit Ethernet,
309 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
310
Jagan Teki8967dea2023-01-30 20:27:45 +0530311config ROCKCHIP_RK3588
312 bool "Support Rockchip RK3588"
313 select ARM64
314 select SUPPORT_SPL
315 select SPL
316 select CLK
317 select PINCTRL
318 select RAM
319 select REGMAP
320 select SYSCON
321 select BOARD_LATE_INIT
Jonas Karlman9bfd6512023-05-17 18:26:37 +0000322 select DM_REGULATOR_FIXED
323 select DM_RESET
Jonas Karlman47af53c2023-04-17 19:07:15 +0000324 imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Jagan Teki8967dea2023-01-30 20:27:45 +0530325 imply ROCKCHIP_COMMON_BOARD
Jonas Karlmanf4d27e92023-04-17 19:07:17 +0000326 imply OF_LIBFDT_OVERLAY
Jonas Karlmaneeb19172023-02-22 22:44:41 +0000327 imply ROCKCHIP_OTP
328 imply MISC_INIT_R
Jonas Karlman67bbb4e2024-02-04 20:53:06 +0000329 imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
330 imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000331 imply CLK_SCMI
332 imply SCMI_FIRMWARE
Shantur Rathorec0009892024-01-21 22:04:47 +0000333 imply BOOTSTD_FULL
Jagan Teki8967dea2023-01-30 20:27:45 +0530334 help
335 The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76 and
336 quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU, Mali-G610 MP4,
337 HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1,
338 SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,
339 SDIO3.0 I2C, UART, SPI, GPIO and PWM.
340
Andy Yan2d982da2017-06-01 18:00:55 +0800341config ROCKCHIP_RV1108
342 bool "Support Rockchip RV1108"
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530343 select CPU_V7A
Kever Yanga2b336e2019-07-22 20:02:21 +0800344 imply ROCKCHIP_COMMON_BOARD
Andy Yan2d982da2017-06-01 18:00:55 +0800345 help
346 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
347 and a DSP.
348
Jagan Teki249a2382022-12-14 23:21:05 +0530349config ROCKCHIP_RV1126
350 bool "Support Rockchip RV1126"
351 select CPU_V7A
352 select SKIP_LOWLEVEL_INIT_ONLY
353 select TPL
354 select SUPPORT_TPL
355 select TPL_NEEDS_SEPARATE_STACK
356 select TPL_ROCKCHIP_BACK_TO_BROM
357 select SPL
358 select SUPPORT_SPL
359 select SPL_STACK_R
360 select CLK
361 select FIT
362 select PINCTRL
363 select RAM
364 select ROCKCHIP_SDRAM_COMMON
365 select REGMAP
366 select SYSCON
367 select DM_PMIC
368 select DM_REGULATOR_FIXED
369 select DM_RESET
370 select REGULATOR_RK8XX
371 select PMIC_RK8XX
372 select BOARD_LATE_INIT
373 imply ROCKCHIP_COMMON_BOARD
Tim Lunnd0812b22024-01-24 14:26:01 +1100374 select SPL_OPTEE_IMAGE if SPL_FIT
Jagan Tekid679f622023-07-29 19:11:42 +0530375 imply OF_LIBFDT_OVERLAY
Tim Lunncbfee492023-10-31 13:07:15 +1100376 imply ROCKCHIP_OTP
377 imply MISC_INIT_R
Jagan Teki249a2382022-12-14 23:21:05 +0530378 imply TPL_DM
379 imply TPL_LIBCOMMON_SUPPORT
380 imply TPL_LIBGENERIC_SUPPORT
381 imply TPL_OF_CONTROL
382 imply TPL_OF_PLATDATA
383 imply TPL_RAM
384 imply TPL_ROCKCHIP_COMMON_BOARD
385 imply TPL_SERIAL
386 imply SPL_CLK
387 imply SPL_DM
388 imply SPL_DRIVERS_MISC
389 imply SPL_LIBCOMMON_SUPPORT
390 imply SPL_LIBGENERIC_SUPPORT
391 imply SPL_OF_CONTROL
392 imply SPL_RAM
393 imply SPL_REGMAP
394 imply SPL_ROCKCHIP_COMMON_BOARD
395 imply SPL_SERIAL
396 imply SPL_SYSCON
397
Heiko Stuebner9cc8feb2018-10-08 13:01:56 +0200398config ROCKCHIP_USB_UART
399 bool "Route uart output to usb pins"
400 help
401 Rockchip SoCs have the ability to route the signals of the debug
402 uart through the d+ and d- pins of a specific usb phy to enable
403 some form of closed-case debugging. With this option supported
404 SoCs will enable this routing as a debug measure.
405
Philipp Tomsich798370f2017-06-29 11:21:15 +0200406config SPL_ROCKCHIP_BACK_TO_BROM
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800407 bool "SPL returns to bootrom"
408 default y if ROCKCHIP_RK3036
Heiko Stübner355a8802017-02-18 19:46:25 +0100409 select ROCKCHIP_BROM_HELPER
Kever Yangbd8532e2019-07-22 19:59:15 +0800410 select SPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200411 depends on SPL
Xu Ziyuan5401eb82016-07-12 19:09:49 +0800412 help
413 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
414 SPL will return to the boot rom, which will then load the U-Boot
415 binary to keep going on.
416
Philipp Tomsich798370f2017-06-29 11:21:15 +0200417config TPL_ROCKCHIP_BACK_TO_BROM
418 bool "TPL returns to bootrom"
Kever Yangfca798d2018-11-09 11:18:15 +0800419 default y
Johan Jonkera768ff52023-10-27 20:35:37 +0200420 select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
Kever Yangbd8532e2019-07-22 19:59:15 +0800421 select TPL_BOOTROM_SUPPORT
Philipp Tomsich798370f2017-06-29 11:21:15 +0200422 depends on TPL
423 help
424 Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
425 SPL will return to the boot rom, which will then load the U-Boot
426 binary to keep going on.
427
Kever Yangbb337732019-07-22 20:02:01 +0800428config ROCKCHIP_COMMON_BOARD
429 bool "Rockchip common board file"
430 help
431 Rockchip SoCs have similar boot process, Common board file is mainly
432 in charge of common process of board_init() and board_late_init() for
433 U-Boot proper.
434
Kever Yang1d7cc72a2019-07-22 19:59:12 +0800435config SPL_ROCKCHIP_COMMON_BOARD
436 bool "Rockchip SPL common board file"
437 depends on SPL
438 help
439 Rockchip SoCs have similar boot process, SPL is mainly in charge of
440 load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
441 no TPL for the board.
442
Kever Yang34ead0f2019-07-09 22:05:55 +0800443config TPL_ROCKCHIP_COMMON_BOARD
Thomas Hebbcfbebf82019-12-20 18:05:22 -0800444 bool "Rockchip TPL common board file"
Kever Yang34ead0f2019-07-09 22:05:55 +0800445 depends on TPL
446 help
447 Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
448 init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
449 common board is a basic TPL board init which can be shared for most
Thomas Hebbfd37f242019-11-13 18:18:03 -0800450 of SoCs to avoid copy-paste for different SoCs.
Kever Yang34ead0f2019-07-09 22:05:55 +0800451
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000452config ROCKCHIP_EXTERNAL_TPL
453 bool "Use external TPL binary"
Massimo Pegorer8c20dfa2023-09-09 11:33:24 +0200454 default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
Jonas Karlman38ad6c92023-02-25 19:01:34 +0000455 help
456 Some Rockchip SoCs require an external TPL to initialize DRAM.
457 Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
458 include the external TPL in the image built by binman.
459
Andy Yan70378cb2017-10-11 15:00:16 +0800460config ROCKCHIP_BOOT_MODE_REG
461 hex "Rockchip boot mode flag register address"
Andy Yan70378cb2017-10-11 15:00:16 +0800462 help
Kever Yang9fbe17c2019-03-28 11:01:23 +0800463 The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
Andy Yan70378cb2017-10-11 15:00:16 +0800464 according to the value from this register.
465
Chris Morgan7c9de742022-05-27 13:18:20 -0500466config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON
467 bool "Disable device boot on power plug-in"
468 depends on PMIC_RK8XX
Chris Morgan7c9de742022-05-27 13:18:20 -0500469 ---help---
470 Say Y here to prevent the device from booting up because of a plug-in
471 event. When set, the device will boot briefly to determine why it was
472 powered on, and if it was determined because of a plug-in event
473 instead of a button press event it will shut back off.
474
Johan Jonkerf6fc8952022-04-09 18:55:02 +0200475config ROCKCHIP_STIMER
476 bool "Rockchip STIMER support"
477 default y
478 help
479 Enable Rockchip STIMER support.
480
481config ROCKCHIP_STIMER_BASE
482 hex
483 depends on ROCKCHIP_STIMER
484
Kever Yange484f772017-04-20 17:03:46 +0800485config ROCKCHIP_SPL_RESERVE_IRAM
486 hex "Size of IRAM reserved in SPL"
Tom Rinif18679c2023-08-02 11:09:43 -0400487 default 0x0
Kever Yange484f772017-04-20 17:03:46 +0800488 help
489 SPL may need reserve memory for firmware loaded by SPL, whose load
490 address is in IRAM and may overlay with SPL text area if not
491 reserved.
492
Heiko Stübner355a8802017-02-18 19:46:25 +0100493config ROCKCHIP_BROM_HELPER
494 bool
495
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200496config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
497 bool "SPL requires early-return (for RK3188-style BROM) to BROM"
498 depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
499 help
500 Some Rockchip BROM variants (e.g. on the RK3188) load the
501 first stage in segments and enter multiple times. E.g. on
502 the RK3188, the first 1KB of the first stage are loaded
503 first and entered; after returning to the BROM, the
504 remainder of the first stage is loaded, but the BROM
505 re-enters at the same address/to the same code as previously.
506
507 This enables support code in the BOOT0 hook for the SPL stage
508 to allow multiple entries.
509
Quentin Schulz95b568f2024-03-11 13:01:54 +0100510config ROCKCHIP_DISABLE_FORCE_JTAG
511 bool "Disable force_jtag feature"
512 default y
513 depends on SPL
514 help
515 Rockchip SoCs can automatically switch between jtag and sdmmc based
516 on the following rules:
517 - all the SDMMC pins including SDMMC_DET set as SDMMC function in
518 GRF,
519 - force_jtag bit in GRF is 1,
520 - SDMMC_DET is low (no card detected),
521
522 Some HW design may not route the SD card card detect to SDMMC_DET
523 pin, thus breaking the SD card support in some cases because JTAG
524 would be auto-enabled by mistake.
525
526 Also, enabling JTAG at runtime may be an undesired feature, e.g.
527 because it could be a security vulnerability.
528
529 This disables force_jtag feature, which you may want for debugging
530 purposes.
531
532 If unsure, say Y.
533
Philipp Tomsich9f1a4472017-10-10 16:21:10 +0200534config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
535 bool "TPL requires early-return (for RK3188-style BROM) to BROM"
536 depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
537 help
538 Some Rockchip BROM variants (e.g. on the RK3188) load the
539 first stage in segments and enter multiple times. E.g. on
540 the RK3188, the first 1KB of the first stage are loaded
541 first and entered; after returning to the BROM, the
542 remainder of the first stage is loaded, but the BROM
543 re-enters at the same address/to the same code as previously.
544
545 This enables support code in the BOOT0 hook for the TPL stage
546 to allow multiple entries.
547
Simon Glassb58bfe02021-08-08 12:20:09 -0600548config SPL_MMC
Philipp Tomsich798370f2017-06-29 11:21:15 +0200549 default y if !SPL_ROCKCHIP_BACK_TO_BROM
Sandy Pattersond70f0f32016-08-29 07:31:16 -0400550
Simon Glass88315f72020-07-19 13:55:57 -0600551config ROCKCHIP_SPI_IMAGE
552 bool "Build a SPI image for rockchip"
Simon Glass88315f72020-07-19 13:55:57 -0600553 help
554 Some Rockchip SoCs support booting from SPI flash. Enable this
Quentin Schulz12df9cf2022-09-02 15:10:54 +0200555 option to produce a SPI-flash image containing U-Boot. The image
556 is built by binman. U-Boot sits near the start of the image.
Simon Glass88315f72020-07-19 13:55:57 -0600557
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300558config LNX_KRNL_IMG_TEXT_OFFSET_BASE
Simon Glass72cc5382022-10-20 18:22:39 -0600559 default TEXT_BASE
Alper Nebi Yasakcf9159e2022-01-29 18:27:56 +0300560
Jonas Karlmane4453632024-03-02 19:16:11 +0000561config ROCKCHIP_COMMON_STACK_ADDR
562 bool
563 depends on SPL_SHARES_INIT_SP_ADDR
564 select HAS_CUSTOM_SYS_INIT_SP_ADDR
565 imply SPL_LIBCOMMON_SUPPORT if SPL
566 imply SPL_LIBGENERIC_SUPPORT if SPL
567 imply SPL_ROCKCHIP_COMMON_BOARD if SPL
568 imply SPL_SYS_MALLOC_F if SPL
569 imply SPL_SYS_MALLOC_SIMPLE if SPL
570 imply TPL_LIBCOMMON_SUPPORT if TPL
571 imply TPL_LIBGENERIC_SUPPORT if TPL
572 imply TPL_ROCKCHIP_COMMON_BOARD if TPL
573 imply TPL_SYS_MALLOC_F if TPL
574 imply TPL_SYS_MALLOC_SIMPLE if TPL
575
Heiko Stuebnerfc367852019-07-16 22:18:21 +0200576source "arch/arm/mach-rockchip/px30/Kconfig"
huang lin1115b642015-11-17 14:20:27 +0800577source "arch/arm/mach-rockchip/rk3036/Kconfig"
Johan Jonkera289fc72022-04-16 17:09:47 +0200578source "arch/arm/mach-rockchip/rk3066/Kconfig"
Kever Yangaa827752017-11-28 16:04:16 +0800579source "arch/arm/mach-rockchip/rk3128/Kconfig"
Heiko Stübneref6db5e2017-02-18 19:46:36 +0100580source "arch/arm/mach-rockchip/rk3188/Kconfig"
Kever Yanga4f460d2017-06-23 17:17:54 +0800581source "arch/arm/mach-rockchip/rk322x/Kconfig"
Heiko Stübner5c91e2b2016-07-16 00:17:15 +0200582source "arch/arm/mach-rockchip/rk3288/Kconfig"
Andy Yanb5e16302019-11-14 11:21:12 +0800583source "arch/arm/mach-rockchip/rk3308/Kconfig"
Kever Yangec02b3c2017-02-23 15:37:51 +0800584source "arch/arm/mach-rockchip/rk3328/Kconfig"
Andreas Färber9e3ad682017-05-15 17:51:18 +0800585source "arch/arm/mach-rockchip/rk3368/Kconfig"
Kever Yang0d3d7832016-07-19 21:16:59 +0800586source "arch/arm/mach-rockchip/rk3399/Kconfig"
Joseph Chen16899892021-06-02 16:13:46 +0800587source "arch/arm/mach-rockchip/rk3568/Kconfig"
Jagan Teki8967dea2023-01-30 20:27:45 +0530588source "arch/arm/mach-rockchip/rk3588/Kconfig"
Andy Yan2d982da2017-06-01 18:00:55 +0800589source "arch/arm/mach-rockchip/rv1108/Kconfig"
Jagan Teki249a2382022-12-14 23:21:05 +0530590source "arch/arm/mach-rockchip/rv1126/Kconfig"
Jonas Karlmane4453632024-03-02 19:16:11 +0000591
592if ROCKCHIP_COMMON_STACK_ADDR && SPL_SHARES_INIT_SP_ADDR
593
594config CUSTOM_SYS_INIT_SP_ADDR
595 default 0x3f00000
596
597config SYS_MALLOC_F_LEN
598 default 0x10000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
599
600config SPL_SYS_MALLOC_F_LEN
601 default 0x8000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
602
603config TPL_SYS_MALLOC_F_LEN
604 default 0x4000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
605
606config TEXT_BASE
607 default 0x00200000 if ARM64
608
609config SPL_TEXT_BASE
610 default 0x0 if ARM64
611
612config SPL_HAS_BSS_LINKER_SECTION
613 default y if ARM64
614
615config SPL_BSS_START_ADDR
616 default 0x3f80000
617
618config SPL_BSS_MAX_SIZE
619 default 0x8000 if SPL_BSS_START_ADDR = 0x3f80000
620
621config SPL_STACK_R
622 default y if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
623
624config SPL_STACK_R_ADDR
625 default 0x3e00000 if CUSTOM_SYS_INIT_SP_ADDR = 0x3f00000
626
627config SPL_STACK_R_MALLOC_SIMPLE_LEN
628 default 0x200000 if SPL_STACK_R_ADDR = 0x3e00000
629
630endif
Simon Glass2cffe662015-08-30 16:55:38 -0600631endif