blob: 5a75920400939a4294139a85518b96a32bfad489 [file] [log] [blame]
York Sunb3d71642016-09-26 08:09:26 -07001config ARCH_LS1012A
York Sunfcd0e742016-10-04 14:31:47 -07002 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +08003 select ARMV8_SET_SMPEN
York Sun4dd8c612016-10-04 14:31:48 -07004 select FSL_LSCH2
York Sunb6fffd82016-10-04 18:03:08 -07005 select SYS_FSL_DDR_BE
York Sunb3d71642016-09-26 08:09:26 -07006 select SYS_FSL_MMDC
York Sun149eb332016-09-26 08:09:27 -07007 select SYS_FSL_ERRATUM_A010315
Ran Wang02dc77b2017-11-13 16:14:48 +08008 select SYS_FSL_ERRATUM_A009798
9 select SYS_FSL_ERRATUM_A008997
10 select SYS_FSL_ERRATUM_A009007
11 select SYS_FSL_ERRATUM_A009008
Simon Glass62adede2017-01-23 13:31:19 -070012 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070013 select BOARD_EARLY_INIT_F
York Sun149eb332016-09-26 08:09:27 -070014
15config ARCH_LS1043A
York Sunfcd0e742016-10-04 14:31:47 -070016 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080017 select ARMV8_SET_SMPEN
York Sun4dd8c612016-10-04 14:31:48 -070018 select FSL_LSCH2
York Sund297d392016-12-28 08:43:40 -080019 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070020 select SYS_FSL_DDR_BE
21 select SYS_FSL_DDR_VER_50
York Sun1dc61ca2016-12-28 08:43:41 -080022 select SYS_FSL_ERRATUM_A008850
Ran Wange64f7472017-09-04 18:46:50 +080023 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +080024 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +080025 select SYS_FSL_ERRATUM_A009008
York Sun1dc61ca2016-12-28 08:43:41 -080026 select SYS_FSL_ERRATUM_A009660
27 select SYS_FSL_ERRATUM_A009663
Ran Wang9e8fabc2017-09-04 18:46:49 +080028 select SYS_FSL_ERRATUM_A009798
York Sun1dc61ca2016-12-28 08:43:41 -080029 select SYS_FSL_ERRATUM_A009929
30 select SYS_FSL_ERRATUM_A009942
York Sun149eb332016-09-26 08:09:27 -070031 select SYS_FSL_ERRATUM_A010315
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +080032 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -080033 select SYS_FSL_HAS_DDR3
34 select SYS_FSL_HAS_DDR4
Simon Glass62adede2017-01-23 13:31:19 -070035 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070036 select BOARD_EARLY_INIT_F
Simon Glass0e5faf02017-06-14 21:28:21 -060037 imply SCSI
Simon Glassc88a09a2017-08-04 16:34:34 -060038 imply CMD_PCI
York Sunb3d71642016-09-26 08:09:26 -070039
York Sunbad49842016-09-26 08:09:24 -070040config ARCH_LS1046A
York Sunfcd0e742016-10-04 14:31:47 -070041 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080042 select ARMV8_SET_SMPEN
York Sun4dd8c612016-10-04 14:31:48 -070043 select FSL_LSCH2
York Sund297d392016-12-28 08:43:40 -080044 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -070045 select SYS_FSL_DDR_BE
York Sunb6fffd82016-10-04 18:03:08 -070046 select SYS_FSL_DDR_VER_50
York Sunf195cf72017-01-27 09:57:31 -080047 select SYS_FSL_ERRATUM_A008336
York Sun1dc61ca2016-12-28 08:43:41 -080048 select SYS_FSL_ERRATUM_A008511
Shengzhou Liua7c37c62017-03-23 18:14:40 +080049 select SYS_FSL_ERRATUM_A008850
Ran Wange64f7472017-09-04 18:46:50 +080050 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +080051 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +080052 select SYS_FSL_ERRATUM_A009008
Ran Wang9e8fabc2017-09-04 18:46:49 +080053 select SYS_FSL_ERRATUM_A009798
York Sun1dc61ca2016-12-28 08:43:41 -080054 select SYS_FSL_ERRATUM_A009801
55 select SYS_FSL_ERRATUM_A009803
56 select SYS_FSL_ERRATUM_A009942
57 select SYS_FSL_ERRATUM_A010165
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +080058 select SYS_FSL_ERRATUM_A010539
York Sund297d392016-12-28 08:43:40 -080059 select SYS_FSL_HAS_DDR4
York Sun6b62ef02016-10-04 18:01:34 -070060 select SYS_FSL_SRDS_2
Simon Glass62adede2017-01-23 13:31:19 -070061 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -070062 select BOARD_EARLY_INIT_F
Simon Glass0e5faf02017-06-14 21:28:21 -060063 imply SCSI
York Sunb3d71642016-09-26 08:09:26 -070064
Ashish Kumarb25faa22017-08-31 16:12:53 +053065config ARCH_LS1088A
66 bool
67 select ARMV8_SET_SMPEN
68 select FSL_LSCH3
69 select SYS_FSL_DDR
70 select SYS_FSL_DDR_LE
71 select SYS_FSL_DDR_VER_50
Ashish Kumarec455e22017-08-31 16:37:31 +053072 select SYS_FSL_EC1
73 select SYS_FSL_EC2
Ashish Kumarb25faa22017-08-31 16:12:53 +053074 select SYS_FSL_ERRATUM_A009803
75 select SYS_FSL_ERRATUM_A009942
76 select SYS_FSL_ERRATUM_A010165
77 select SYS_FSL_ERRATUM_A008511
78 select SYS_FSL_ERRATUM_A008850
Ran Wangef277072017-09-22 15:21:34 +080079 select SYS_FSL_ERRATUM_A009007
Ashish Kumarb25faa22017-08-31 16:12:53 +053080 select SYS_FSL_HAS_CCI400
81 select SYS_FSL_HAS_DDR4
Ashish Kumarec455e22017-08-31 16:37:31 +053082 select SYS_FSL_HAS_RGMII
Ashish Kumarb25faa22017-08-31 16:12:53 +053083 select SYS_FSL_HAS_SEC
84 select SYS_FSL_SEC_COMPAT_5
85 select SYS_FSL_SEC_LE
86 select SYS_FSL_SRDS_1
87 select SYS_FSL_SRDS_2
88 select FSL_TZASC_1
89 select ARCH_EARLY_INIT_R
90 select BOARD_EARLY_INIT_F
Ashish Kumara179e562017-11-02 09:50:47 +053091 imply SCSI
Ashish Kumarb25faa22017-08-31 16:12:53 +053092
York Sunfcd0e742016-10-04 14:31:47 -070093config ARCH_LS2080A
94 bool
Hou Zhiqiang4d1525a2017-01-06 17:41:11 +080095 select ARMV8_SET_SMPEN
Tom Rinibacb52c2017-03-07 07:13:42 -050096 select ARM_ERRATA_826974
97 select ARM_ERRATA_828024
98 select ARM_ERRATA_829520
99 select ARM_ERRATA_833471
York Sun4dd8c612016-10-04 14:31:48 -0700100 select FSL_LSCH3
York Sund297d392016-12-28 08:43:40 -0800101 select SYS_FSL_DDR
York Sunb6fffd82016-10-04 18:03:08 -0700102 select SYS_FSL_DDR_LE
103 select SYS_FSL_DDR_VER_50
Ashish Kumar97393d62017-08-18 10:54:36 +0530104 select SYS_FSL_HAS_CCN504
York Sun6b62ef02016-10-04 18:01:34 -0700105 select SYS_FSL_HAS_DP_DDR
York Sun92c36e22016-12-28 08:43:30 -0800106 select SYS_FSL_HAS_SEC
York Sund297d392016-12-28 08:43:40 -0800107 select SYS_FSL_HAS_DDR4
York Sun92c36e22016-12-28 08:43:30 -0800108 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -0800109 select SYS_FSL_SEC_LE
York Sun6b62ef02016-10-04 18:01:34 -0700110 select SYS_FSL_SRDS_2
Ashish kumar76bd6ce2017-04-07 11:40:32 +0530111 select FSL_TZASC_1
112 select FSL_TZASC_2
York Sun1dc61ca2016-12-28 08:43:41 -0800113 select SYS_FSL_ERRATUM_A008336
114 select SYS_FSL_ERRATUM_A008511
115 select SYS_FSL_ERRATUM_A008514
116 select SYS_FSL_ERRATUM_A008585
Ran Wange64f7472017-09-04 18:46:50 +0800117 select SYS_FSL_ERRATUM_A008997
Ran Wang3ba69482017-09-04 18:46:51 +0800118 select SYS_FSL_ERRATUM_A009007
Ran Wangb358b7b2017-09-04 18:46:48 +0800119 select SYS_FSL_ERRATUM_A009008
York Sun1dc61ca2016-12-28 08:43:41 -0800120 select SYS_FSL_ERRATUM_A009635
121 select SYS_FSL_ERRATUM_A009663
Ran Wang9e8fabc2017-09-04 18:46:49 +0800122 select SYS_FSL_ERRATUM_A009798
York Sun1dc61ca2016-12-28 08:43:41 -0800123 select SYS_FSL_ERRATUM_A009801
124 select SYS_FSL_ERRATUM_A009803
125 select SYS_FSL_ERRATUM_A009942
126 select SYS_FSL_ERRATUM_A010165
Ashish kumar3b52a232017-02-23 16:03:57 +0530127 select SYS_FSL_ERRATUM_A009203
Simon Glass62adede2017-01-23 13:31:19 -0700128 select ARCH_EARLY_INIT_R
Simon Glass7a99a872017-01-23 13:31:20 -0700129 select BOARD_EARLY_INIT_F
York Sun4dd8c612016-10-04 14:31:48 -0700130
131config FSL_LSCH2
132 bool
Ashish Kumar11234062017-08-11 11:09:14 +0530133 select SYS_FSL_HAS_CCI400
York Sun92c36e22016-12-28 08:43:30 -0800134 select SYS_FSL_HAS_SEC
135 select SYS_FSL_SEC_COMPAT_5
York Sunfa4199422016-12-28 08:43:31 -0800136 select SYS_FSL_SEC_BE
York Sun6b62ef02016-10-04 18:01:34 -0700137 select SYS_FSL_SRDS_1
138 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -0700139
140config FSL_LSCH3
141 bool
York Sun6b62ef02016-10-04 18:01:34 -0700142 select SYS_FSL_SRDS_1
143 select SYS_HAS_SERDES
York Sun4dd8c612016-10-04 14:31:48 -0700144
York Sun6c089742017-03-06 09:02:25 -0800145config FSL_MC_ENET
146 bool "Management Complex network"
Ashish Kumarb25faa22017-08-31 16:12:53 +0530147 depends on ARCH_LS2080A || ARCH_LS1088A
York Sun6c089742017-03-06 09:02:25 -0800148 default y
149 select RESV_RAM
150 help
151 Enable Management Complex (MC) network
152
York Sun4dd8c612016-10-04 14:31:48 -0700153menu "Layerscape architecture"
154 depends on FSL_LSCH2 || FSL_LSCH3
York Sunfcd0e742016-10-04 14:31:47 -0700155
Hou Zhiqiangd553bf22016-12-13 14:54:24 +0800156config FSL_PCIE_COMPAT
157 string "PCIe compatible of Kernel DT"
158 depends on PCIE_LAYERSCAPE
159 default "fsl,ls1012a-pcie" if ARCH_LS1012A
160 default "fsl,ls1043a-pcie" if ARCH_LS1043A
161 default "fsl,ls1046a-pcie" if ARCH_LS1046A
162 default "fsl,ls2080a-pcie" if ARCH_LS2080A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530163 default "fsl,ls1088a-pcie" if ARCH_LS1088A
Hou Zhiqiangd553bf22016-12-13 14:54:24 +0800164 help
165 This compatible is used to find pci controller node in Kernel DT
166 to complete fixup.
167
Wenbin Songa8f57a92017-01-17 18:31:15 +0800168config HAS_FEATURE_GIC64K_ALIGN
169 bool
170 default y if ARCH_LS1043A
171
Wenbin Songc6bc7c02017-01-17 18:31:16 +0800172config HAS_FEATURE_ENHANCED_MSI
173 bool
174 default y if ARCH_LS1043A
Wenbin Songa8f57a92017-01-17 18:31:15 +0800175
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800176menu "Layerscape PPA"
177config FSL_LS_PPA
178 bool "FSL Layerscape PPA firmware support"
macro.wave.z@gmail.com01bd3342016-12-08 11:58:22 +0800179 depends on !ARMV8_PSCI
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800180 select ARMV8_SEC_FIRMWARE_SUPPORT
Hou Zhiqiang6be115d2017-01-16 17:31:48 +0800181 select SEC_FIRMWARE_ARMV8_PSCI
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800182 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800183 help
184 The FSL Primary Protected Application (PPA) is a software component
185 which is loaded during boot stage, and then remains resident in RAM
186 and runs in the TrustZone after boot.
187 Say y to enable it.
York Sunf2aaf842017-05-15 08:52:00 -0700188
189config SPL_FSL_LS_PPA
190 bool "FSL Layerscape PPA firmware support for SPL build"
191 depends on !ARMV8_PSCI
192 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
193 select SEC_FIRMWARE_ARMV8_PSCI
194 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
195 help
196 The FSL Primary Protected Application (PPA) is a software component
197 which is loaded during boot stage, and then remains resident in RAM
198 and runs in the TrustZone after boot. This is to load PPA during SPL
199 stage instead of the RAM version of U-Boot. Once PPA is initialized,
200 the rest of U-Boot (including RAM version) runs at EL2.
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800201choice
202 prompt "FSL Layerscape PPA firmware loading-media select"
203 depends on FSL_LS_PPA
Hou Zhiqiangbd6e2cd2017-03-17 16:12:33 +0800204 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
205 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800206 default SYS_LS_PPA_FW_IN_XIP
207
208config SYS_LS_PPA_FW_IN_XIP
209 bool "XIP"
210 help
211 Say Y here if the PPA firmware locate at XIP flash, such
212 as NOR or QSPI flash.
213
Hou Zhiqiangbd6e2cd2017-03-17 16:12:33 +0800214config SYS_LS_PPA_FW_IN_MMC
215 bool "eMMC or SD Card"
216 help
217 Say Y here if the PPA firmware locate at eMMC/SD card.
218
219config SYS_LS_PPA_FW_IN_NAND
220 bool "NAND"
221 help
222 Say Y here if the PPA firmware locate at NAND flash.
223
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800224endchoice
225
226config SYS_LS_PPA_FW_ADDR
227 hex "Address of PPA firmware loading from"
228 depends on FSL_LS_PPA
Priyanka Jain7d05b992017-04-28 10:41:35 +0530229 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
Alison Wangb5b8bfa2017-05-16 10:45:58 +0800230 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
Santan Kumar0f0173d2017-04-28 12:47:24 +0530231 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
Ashish Kumar227b4bc2017-08-31 16:12:54 +0530232 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
Alison Wangb5b8bfa2017-05-16 10:45:58 +0800233 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
234 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
235 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
Hou Zhiqiangbd6e2cd2017-03-17 16:12:33 +0800236
Hou Zhiqiangbff56d52017-01-16 17:31:49 +0800237 help
238 If the PPA firmware locate at XIP flash, such as NOR or
239 QSPI flash, this address is a directly memory-mapped.
240 If it is in a serial accessed flash, such as NAND and SD
241 card, it is a byte offset.
Vinitha Pillai-B57223a4b3ded2017-03-23 13:48:14 +0530242
243config SYS_LS_PPA_ESBC_ADDR
244 hex "hdr address of PPA firmware loading from"
245 depends on FSL_LS_PPA && CHAIN_OF_TRUST
Sumit Garg666bbd02017-08-16 07:13:28 -0400246 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
247 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
248 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
Udit Agarwalc83ea8a2017-08-16 07:13:29 -0400249 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
250 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
Udit Agarwal09fd5792017-11-22 09:01:26 +0530251 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
Sumit Garg666bbd02017-08-16 07:13:28 -0400252 default 0x680000 if SYS_LS_PPA_FW_IN_MMC
253 default 0x680000 if SYS_LS_PPA_FW_IN_NAND
Vinitha Pillai-B57223a4b3ded2017-03-23 13:48:14 +0530254 help
255 If the PPA header firmware locate at XIP flash, such as NOR or
256 QSPI flash, this address is a directly memory-mapped.
257 If it is in a serial accessed flash, such as NAND and SD
258 card, it is a byte offset.
259
Sumit Garg8fddf752017-04-20 05:09:11 +0530260config LS_PPA_ESBC_HDR_SIZE
261 hex "Length of PPA ESBC header"
262 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
263 default 0x2000
264 help
265 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
266 NAND to memory to validate PPA image.
267
macro.wave.z@gmail.comec2d7ed2016-12-08 11:58:21 +0800268endmenu
269
Ran Wange64f7472017-09-04 18:46:50 +0800270config SYS_FSL_ERRATUM_A008997
271 bool "Workaround for USB PHY erratum A008997"
272
Ran Wang3ba69482017-09-04 18:46:51 +0800273config SYS_FSL_ERRATUM_A009007
274 bool
275 help
276 Workaround for USB PHY erratum A009007
277
Ran Wangb358b7b2017-09-04 18:46:48 +0800278config SYS_FSL_ERRATUM_A009008
279 bool "Workaround for USB PHY erratum A009008"
280
Ran Wang9e8fabc2017-09-04 18:46:49 +0800281config SYS_FSL_ERRATUM_A009798
282 bool "Workaround for USB PHY erratum A009798"
283
York Sun149eb332016-09-26 08:09:27 -0700284config SYS_FSL_ERRATUM_A010315
285 bool "Workaround for PCIe erratum A010315"
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800286
287config SYS_FSL_ERRATUM_A010539
288 bool "Workaround for PIN MUX erratum A010539"
York Sun4dd8c612016-10-04 14:31:48 -0700289
York Sunf188d222016-10-04 14:45:01 -0700290config MAX_CPUS
291 int "Maximum number of CPUs permitted for Layerscape"
292 default 4 if ARCH_LS1043A
293 default 4 if ARCH_LS1046A
294 default 16 if ARCH_LS2080A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530295 default 8 if ARCH_LS1088A
York Sunf188d222016-10-04 14:45:01 -0700296 default 1
297 help
298 Set this number to the maximum number of possible CPUs in the SoC.
299 SoCs may have multiple clusters with each cluster may have multiple
300 ports. If some ports are reserved but higher ports are used for
301 cores, count the reserved ports. This will allocate enough memory
302 in spin table to properly handle all cores.
303
York Sun728e7002016-12-02 09:32:35 -0800304config SECURE_BOOT
York Sun8a3d8ed2017-01-04 10:32:08 -0800305 bool "Secure Boot"
York Sun728e7002016-12-02 09:32:35 -0800306 help
307 Enable Freescale Secure Boot feature
308
Yuan Yao52ae4fd2016-12-01 10:13:52 +0800309config QSPI_AHB_INIT
310 bool "Init the QSPI AHB bus"
311 help
312 The default setting for QSPI AHB bus just support 3bytes addressing.
313 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
314 bus for those flashes to support the full QSPI flash size.
315
Ashish Kumar11234062017-08-11 11:09:14 +0530316config SYS_CCI400_OFFSET
317 hex "Offset for CCI400 base"
318 depends on SYS_FSL_HAS_CCI400
319 default 0x3090000 if ARCH_LS1088A
320 default 0x180000 if FSL_LSCH2
321 help
322 Offset for CCI400 base
323 CCI400 base addr = CCSRBAR + CCI400_OFFSET
324
York Sune7310a32016-10-04 14:45:54 -0700325config SYS_FSL_IFC_BANK_COUNT
326 int "Maximum banks of Integrated flash controller"
Ashish Kumarb25faa22017-08-31 16:12:53 +0530327 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
York Sune7310a32016-10-04 14:45:54 -0700328 default 4 if ARCH_LS1043A
329 default 4 if ARCH_LS1046A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530330 default 8 if ARCH_LS2080A || ARCH_LS1088A
York Sune7310a32016-10-04 14:45:54 -0700331
Ashish Kumar11234062017-08-11 11:09:14 +0530332config SYS_FSL_HAS_CCI400
333 bool
334
Ashish Kumar97393d62017-08-18 10:54:36 +0530335config SYS_FSL_HAS_CCN504
336 bool
337
York Sun0dc9abb2016-10-04 14:46:50 -0700338config SYS_FSL_HAS_DP_DDR
339 bool
340
York Sun6b62ef02016-10-04 18:01:34 -0700341config SYS_FSL_SRDS_1
342 bool
343
344config SYS_FSL_SRDS_2
345 bool
346
347config SYS_HAS_SERDES
348 bool
349
Ashish kumar76bd6ce2017-04-07 11:40:32 +0530350config FSL_TZASC_1
351 bool
352
353config FSL_TZASC_2
354 bool
355
York Sun4dd8c612016-10-04 14:31:48 -0700356endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800357
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800358menu "Layerscape clock tree configuration"
359 depends on FSL_LSCH2 || FSL_LSCH3
360
361config SYS_FSL_CLK
362 bool "Enable clock tree initialization"
363 default y
364
365config CLUSTER_CLK_FREQ
366 int "Reference clock of core cluster"
367 depends on ARCH_LS1012A
368 default 100000000
369 help
370 This number is the reference clock frequency of core PLL.
371 For most platforms, the core PLL and Platform PLL have the same
372 reference clock, but for some platforms, LS1012A for instance,
373 they are provided sepatately.
374
375config SYS_FSL_PCLK_DIV
376 int "Platform clock divider"
377 default 1 if ARCH_LS1043A
378 default 1 if ARCH_LS1046A
Ashish Kumarb25faa22017-08-31 16:12:53 +0530379 default 1 if ARCH_LS1088A
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800380 default 2
381 help
382 This is the divider that is used to derive Platform clock from
383 Platform PLL, in another word:
384 Platform_clk = Platform_PLL_freq / this_divider
385
386config SYS_FSL_DSPI_CLK_DIV
387 int "DSPI clock divider"
388 default 1 if ARCH_LS1043A
389 default 2
390 help
391 This is the divider that is used to derive DSPI clock from Platform
Hou Zhiqiang0c8fcb62017-07-03 18:37:11 +0800392 clock, in another word DSPI_clk = Platform_clk / this_divider.
Hou Zhiqiang3f91cda2017-01-10 16:44:15 +0800393
394config SYS_FSL_DUART_CLK_DIV
395 int "DUART clock divider"
396 default 1 if ARCH_LS1043A
397 default 2
398 help
399 This is the divider that is used to derive DUART clock from Platform
400 clock, in another word DUART_clk = Platform_clk / this_divider.
401
402config SYS_FSL_I2C_CLK_DIV
403 int "I2C clock divider"
404 default 1 if ARCH_LS1043A
405 default 2
406 help
407 This is the divider that is used to derive I2C clock from Platform
408 clock, in another word I2C_clk = Platform_clk / this_divider.
409
410config SYS_FSL_IFC_CLK_DIV
411 int "IFC clock divider"
412 default 1 if ARCH_LS1043A
413 default 2
414 help
415 This is the divider that is used to derive IFC clock from Platform
416 clock, in another word IFC_clk = Platform_clk / this_divider.
417
418config SYS_FSL_LPUART_CLK_DIV
419 int "LPUART clock divider"
420 default 1 if ARCH_LS1043A
421 default 2
422 help
423 This is the divider that is used to derive LPUART clock from Platform
424 clock, in another word LPUART_clk = Platform_clk / this_divider.
425
426config SYS_FSL_SDHC_CLK_DIV
427 int "SDHC clock divider"
428 default 1 if ARCH_LS1043A
429 default 1 if ARCH_LS1012A
430 default 2
431 help
432 This is the divider that is used to derive SDHC clock from Platform
433 clock, in another word SDHC_clk = Platform_clk / this_divider.
434endmenu
435
York Sund6964b32017-03-06 09:02:24 -0800436config RESV_RAM
437 bool
438 help
439 Reserve memory from the top, tracked by gd->arch.resv_ram. This
440 reserved RAM can be used by special driver that resides in memory
441 after U-Boot exits. It's up to implementation to allocate and allow
442 access to this reserved memory. For example, the reserved RAM can
443 be at the high end of physical memory. The reserve RAM may be
444 excluded from memory bank(s) passed to OS, or marked as reserved.
445
Ashish Kumarec455e22017-08-31 16:37:31 +0530446config SYS_FSL_EC1
447 bool
448 help
449 Ethernet controller 1, this is connected to MAC3.
450 Provides DPAA2 capabilities
451
452config SYS_FSL_EC2
453 bool
454 help
455 Ethernet controller 2, this is connected to MAC4.
456 Provides DPAA2 capabilities
457
York Sun1dc61ca2016-12-28 08:43:41 -0800458config SYS_FSL_ERRATUM_A008336
459 bool
460
461config SYS_FSL_ERRATUM_A008514
462 bool
463
464config SYS_FSL_ERRATUM_A008585
465 bool
466
467config SYS_FSL_ERRATUM_A008850
468 bool
469
Ashish kumar3b52a232017-02-23 16:03:57 +0530470config SYS_FSL_ERRATUM_A009203
471 bool
472
York Sun1dc61ca2016-12-28 08:43:41 -0800473config SYS_FSL_ERRATUM_A009635
474 bool
475
476config SYS_FSL_ERRATUM_A009660
477 bool
478
479config SYS_FSL_ERRATUM_A009929
480 bool
York Sun1a770752017-03-06 09:02:26 -0800481
Ashish Kumarec455e22017-08-31 16:37:31 +0530482
483config SYS_FSL_HAS_RGMII
484 bool
485 depends on SYS_FSL_EC1 || SYS_FSL_EC2
486
487
York Sun1a770752017-03-06 09:02:26 -0800488config SYS_MC_RSV_MEM_ALIGN
489 hex "Management Complex reserved memory alignment"
490 depends on RESV_RAM
Ashish Kumarb25faa22017-08-31 16:12:53 +0530491 default 0x20000000 if ARCH_LS2080A
492 default 0x70000000 if ARCH_LS1088A
York Sun1a770752017-03-06 09:02:26 -0800493 help
494 Reserved memory needs to be aligned for MC to use. Default value
495 is 512MB.
Philipp Tomsich2d6a0cc2017-08-03 23:23:55 +0200496
497config SPL_LDSCRIPT
498 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
Ran Wang5959f842017-10-23 10:09:21 +0800499
500config HAS_FSL_XHCI_USB
501 bool
502 default y if ARCH_LS1043A || ARCH_LS1046A
503 help
504 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
505 pins, select it when the pins are assigned to USB.