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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
17implementation of variables and functions to fulfill the optional requirements.
18These implementations are all weakly defined; they are provided to ease the
19porting effort. Each platform port can override them with its own implementation
20if the default implementation is inadequate.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022Some modifications are common to all Boot Loader (BL) stages. Section 2
23discusses these in detail. The subsequent sections discuss the remaining
24modifications for each BL stage in detail.
25
Sandrine Bailleuxdad35612022-11-08 13:36:42 +010026Please refer to the :ref:`Platform Ports Policy` for the policy regarding
27compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010028
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000029Only Arm development platforms (such as FVP and Juno) may use the
30functions/definitions in ``include/plat/arm/common/`` and the corresponding
31source files in ``plat/arm/common/``. This is done so that there are no
32dependencies between platforms maintained by different people/companies. If you
33want to use any of the functionality present in ``plat/arm`` files, please
34create a pull request that moves the code to ``plat/common`` so that it can be
35discussed.
36
Douglas Raillardd7c21b72017-06-28 15:23:03 +010037Common modifications
38--------------------
39
40This section covers the modifications that should be made by the platform for
41each BL stage to correctly port the firmware stack. They are categorized as
42either mandatory or optional.
43
44Common mandatory modifications
45------------------------------
46
47A platform port must enable the Memory Management Unit (MMU) as well as the
48instruction and data caches for each BL stage. Setting up the translation
49tables is the responsibility of the platform port because memory maps differ
50across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010051provided to help in this setup.
52
53Note that although this library supports non-identity mappings, this is intended
54only for re-mapping peripheral physical addresses and allows platforms with high
55I/O addresses to reduce their virtual address space. All other addresses
56corresponding to code and data must currently use an identity mapping.
57
Dan Handley610e7e12018-03-01 18:44:00 +000058Also, the only translation granule size supported in TF-A is 4KB, as various
59parts of the code assume that is the case. It is not possible to switch to
6016 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010061
Dan Handley610e7e12018-03-01 18:44:00 +000062In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
64an identity mapping for all addresses.
65
66If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
67block of identity mapped secure memory with Device-nGnRE attributes aligned to
68page boundary (4K) for each BL stage. All sections which allocate coherent
69memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
70section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
71possible for the firmware to place variables in it using the following C code
72directive:
73
74::
75
76 __section("bakery_lock")
77
78Or alternatively the following assembler code directive:
79
80::
81
82 .section bakery_lock
83
84The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
85used to allocate any data structures that are accessed both when a CPU is
86executing with its MMU and caches enabled, and when it's running with its MMU
87and caches disabled. Examples are given below.
88
89The following variables, functions and constants must be defined by the platform
90for the firmware to work correctly.
91
Javier Almansa Sobrino37bf69c2022-04-07 18:26:49 +010092.. _platform_def_mandatory:
93
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +010094File : platform_def.h [mandatory]
95~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +010096
97Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000098include path with the following constants defined. This will require updating
99the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100
Paul Beesleyf8640672019-04-12 14:19:42 +0100101Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100102which provides typical values for some of the constants below. These values are
103likely to be suitable for all platform ports.
104
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100105- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100106
107 Defines the linker format used by the platform, for example
108 ``elf64-littleaarch64``.
109
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100110- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100111
112 Defines the processor architecture for the linker by the platform, for
113 example ``aarch64``.
114
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100115- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100116
117 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100118 by ``plat/common/aarch64/platform_mp_stack.S`` and
119 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
David Horstmann051fd6d2020-11-12 15:19:04 +0000121- **#define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100122
Max Yufa0b4e82022-09-08 23:21:21 +0000123 Defines the size in bytes of the largest cache line across all the cache
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100124 levels in the platform.
125
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100126- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127
128 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
129 function.
130
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100131- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132
133 Defines the total number of CPUs implemented by the platform across all
134 clusters in the system.
135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100136- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137
138 Defines the total number of nodes in the power domain topology
139 tree at all the power domain levels used by the platform.
140 This macro is used by the PSCI implementation to allocate
141 data structures to represent power domain topology.
142
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100143- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100144
145 Defines the maximum power domain level that the power management operations
146 should apply to. More often, but not always, the power domain level
147 corresponds to affinity level. This macro allows the PSCI implementation
148 to know the highest power domain level that it should consider for power
149 management operations in the system that the platform implements. For
150 example, the Base AEM FVP implements two clusters with a configurable
151 number of CPUs and it reports the maximum power domain level as 1.
152
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100153- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100154
155 Defines the local power state corresponding to the deepest power down
156 possible at every power domain level in the platform. The local power
157 states for each level may be sparsely allocated between 0 and this value
158 with 0 being reserved for the RUN state. The PSCI implementation uses this
159 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100162- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100163
164 Defines the local power state corresponding to the deepest retention state
165 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100166 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100168 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100170- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100171
172 Defines the maximum number of local power states per power domain level
173 that the platform supports. The default value of this macro is 2 since
174 most platforms just support a maximum of two local power states at each
175 power domain level (power-down and retention). If the platform needs to
176 account for more local power states, then it must redefine this macro.
177
178 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100179 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100181- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100182
183 Defines the base address in secure ROM where BL1 originally lives. Must be
184 aligned on a page-size boundary.
185
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100186- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100187
188 Defines the maximum address in secure ROM that BL1's actual content (i.e.
189 excluding any data section allocated at runtime) can occupy.
190
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100191- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100192
193 Defines the base address in secure RAM where BL1's read-write data will live
194 at runtime. Must be aligned on a page-size boundary.
195
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100196- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100197
198 Defines the maximum address in secure RAM that BL1's read-write data can
199 occupy at runtime.
200
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100201- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100202
203 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000204 Must be aligned on a page-size boundary. This constant is not applicable
205 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100207- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100208
209 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000210 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
211
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100212- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000213
214 Defines the base address in secure XIP memory where BL2 RO section originally
215 lives. Must be aligned on a page-size boundary. This constant is only needed
216 when BL2_IN_XIP_MEM is set to '1'.
217
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100218- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000219
220 Defines the maximum address in secure XIP memory that BL2's actual content
221 (i.e. excluding any data section allocated at runtime) can occupy. This
222 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
223
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100224- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000225
226 Defines the base address in secure RAM where BL2's read-write data will live
227 at runtime. Must be aligned on a page-size boundary. This constant is only
228 needed when BL2_IN_XIP_MEM is set to '1'.
229
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100230- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000231
232 Defines the maximum address in secure RAM that BL2's read-write data can
233 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
234 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100236- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100237
238 Defines the base address in secure RAM where BL2 loads the BL31 binary
239 image. Must be aligned on a page-size boundary.
240
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100241- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243 Defines the maximum address in secure RAM that the BL31 image can occupy.
244
Tamas Ban1d3354e2022-09-16 14:09:30 +0200245- **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE**
246
247 Defines the maximum message size between AP and RSS. Need to define if
248 platform supports RSS.
249
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100250For every image, the platform must define individual identifiers that will be
251used by BL1 or BL2 to load the corresponding image into memory from non-volatile
252storage. For the sake of performance, integer numbers will be used as
253identifiers. The platform will use those identifiers to return the relevant
254information about the image to be loaded (file handler, load address,
255authentication information, etc.). The following image identifiers are
256mandatory:
257
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100258- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100259
260 BL2 image identifier, used by BL1 to load BL2.
261
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100262- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100263
264 BL31 image identifier, used by BL2 to load BL31.
265
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100266- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100267
268 BL33 image identifier, used by BL2 to load BL33.
269
270If Trusted Board Boot is enabled, the following certificate identifiers must
271also be defined:
272
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100273- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100274
275 BL2 content certificate identifier, used by BL1 to load the BL2 content
276 certificate.
277
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100278- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
280 Trusted key certificate identifier, used by BL2 to load the trusted key
281 certificate.
282
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100283- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100284
285 BL31 key certificate identifier, used by BL2 to load the BL31 key
286 certificate.
287
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100288- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100289
290 BL31 content certificate identifier, used by BL2 to load the BL31 content
291 certificate.
292
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100293- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100294
295 BL33 key certificate identifier, used by BL2 to load the BL33 key
296 certificate.
297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100298- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299
300 BL33 content certificate identifier, used by BL2 to load the BL33 content
301 certificate.
302
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100303- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100305 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306 FWU content certificate.
307
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100308- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100309
Dan Handley610e7e12018-03-01 18:44:00 +0000310 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100311 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000312 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100313 set.
314
315If the AP Firmware Updater Configuration image, BL2U is used, the following
316must also be defined:
317
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100318- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100319
320 Defines the base address in secure memory where BL1 copies the BL2U binary
321 image. Must be aligned on a page-size boundary.
322
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100323- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100324
325 Defines the maximum address in secure memory that the BL2U image can occupy.
326
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100327- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100328
329 BL2U image identifier, used by BL1 to fetch an image descriptor
330 corresponding to BL2U.
331
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100332If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100333must also be defined:
334
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100335- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100336
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100337 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
338 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000339
340 .. note::
341 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100342
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100343If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100344also be defined:
345
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100346- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100347
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100348 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100349 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000350
351 .. note::
352 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100354- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100355
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100356 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
357 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100358
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100359If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360be defined:
361
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100362- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100363
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100364 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100365 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000366
367 .. note::
368 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100369
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100370- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100371
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100372 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
373 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374
375For the the Firmware update capability of TRUSTED BOARD BOOT, the following
376macros may also be defined:
377
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100378- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100379
380 Total number of images that can be loaded simultaneously. If the platform
381 doesn't specify any value, it defaults to 10.
382
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100383If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100384also be defined:
385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100386- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100388 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000389 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100390
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100391- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100393 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394 certificate (mandatory when Trusted Board Boot is enabled).
395
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100396- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100397
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100398 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100399 content certificate (mandatory when Trusted Board Boot is enabled).
400
401If a BL32 image is supported by the platform, the following constants must
402also be defined:
403
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100404- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100405
406 BL32 image identifier, used by BL2 to load BL32.
407
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100408- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100409
410 BL32 key certificate identifier, used by BL2 to load the BL32 key
411 certificate (mandatory when Trusted Board Boot is enabled).
412
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100413- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100414
415 BL32 content certificate identifier, used by BL2 to load the BL32 content
416 certificate (mandatory when Trusted Board Boot is enabled).
417
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100418- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100419
420 Defines the base address in secure memory where BL2 loads the BL32 binary
421 image. Must be aligned on a page-size boundary.
422
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100423- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100424
425 Defines the maximum address that the BL32 image can occupy.
426
427If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
428platform, the following constants must also be defined:
429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100430- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100431
432 Defines the base address of the secure memory used by the TSP image on the
433 platform. This must be at the same address or below ``BL32_BASE``.
434
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100435- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
437 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000438 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
439 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
440 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100441
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100442- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100443
444 Defines the ID of the secure physical generic timer interrupt used by the
445 TSP's interrupt handling code.
446
447If the platform port uses the translation table library code, the following
448constants must also be defined:
449
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100450- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100451
452 Optional flag that can be set per-image to enable the dynamic allocation of
453 regions even when the MMU is enabled. If not defined, only static
454 functionality will be available, if defined and set to 1 it will also
455 include the dynamic functionality.
456
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100457- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100458
459 Defines the maximum number of translation tables that are allocated by the
460 translation table library code. To minimize the amount of runtime memory
461 used, choose the smallest value needed to map the required virtual addresses
462 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
463 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
464 as well.
465
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100466- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100467
468 Defines the maximum number of regions that are allocated by the translation
469 table library code. A region consists of physical base address, virtual base
470 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
471 defined in the ``mmap_region_t`` structure. The platform defines the regions
472 that should be mapped. Then, the translation table library will create the
473 corresponding tables and descriptors at runtime. To minimize the amount of
474 runtime memory used, choose the smallest value needed to register the
475 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
476 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
477 the dynamic regions as well.
478
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100479- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100480
481 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000482 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100483
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100484- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100485
486 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000487 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100488
489If the platform port uses the IO storage framework, the following constants
490must also be defined:
491
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100492- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100493
494 Defines the maximum number of registered IO devices. Attempting to register
495 more devices than this value using ``io_register_device()`` will fail with
496 -ENOMEM.
497
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100498- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100499
500 Defines the maximum number of open IO handles. Attempting to open more IO
501 entities than this value using ``io_open()`` will fail with -ENOMEM.
502
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100503- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100504
505 Defines the maximum number of registered IO block devices. Attempting to
506 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100507 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100508 With this macro, multiple block devices could be supported at the same
509 time.
510
511If the platform needs to allocate data within the per-cpu data framework in
512BL31, it should define the following macro. Currently this is only required if
513the platform decides not to use the coherent memory section by undefining the
514``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
515required memory within the the per-cpu data to minimize wastage.
516
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100517- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100518
519 Defines the memory (in bytes) to be reserved within the per-cpu data
520 structure for use by the platform layer.
521
522The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000523memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100524
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100525- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100526
527 Defines the maximum address in secure RAM that the BL31's progbits sections
528 can occupy.
529
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100530- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100531
532 Defines the maximum address that the TSP's progbits sections can occupy.
533
534If the platform port uses the PL061 GPIO driver, the following constant may
535optionally be defined:
536
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100537- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100538 Maximum number of GPIOs required by the platform. This allows control how
539 much memory is allocated for PL061 GPIO controllers. The default value is
540
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100541 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100542
543If the platform port uses the partition driver, the following constant may
544optionally be defined:
545
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100546- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100547 Maximum number of partition entries required by the platform. This allows
548 control how much memory is allocated for partition entries. The default
549 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100550 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100551 PLAT_PARTITION_MAX_ENTRIES := 12
552 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100553
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800554- **PLAT_PARTITION_BLOCK_SIZE**
555 The size of partition block. It could be either 512 bytes or 4096 bytes.
556 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000557 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800558 PLAT_PARTITION_BLOCK_SIZE := 4096
559 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
560
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100561The following constant is optional. It should be defined to override the default
562behaviour of the ``assert()`` function (for example, to save memory).
563
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100564- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100565 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
566 ``assert()`` prints the name of the file, the line number and the asserted
567 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
568 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
569 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
570 defined, it defaults to ``LOG_LEVEL``.
571
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100572If the platform port uses the DRTM feature, the following constants must be
573defined:
574
575- **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE**
576
577 Maximum Event Log size used by the platform. Platform can decide the maximum
578 size of the Event Log buffer, depending upon the highest hash algorithm
579 chosen and the number of components selected to measure during the DRTM
580 execution flow.
581
582- **#define : PLAT_DRTM_MMAP_ENTRIES**
583
584 Number of the MMAP entries used by the DRTM implementation to calculate the
585 size of address map region of the platform.
586
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100587File : plat_macros.S [mandatory]
588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100589
590Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000591the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100592found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
593
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100594- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100595
596 This macro allows the crash reporting routine to print relevant platform
597 registers in case of an unhandled exception in BL31. This aids in debugging
598 and this macro can be defined to be empty in case register reporting is not
599 desired.
600
601 For instance, GIC or interconnect registers may be helpful for
602 troubleshooting.
603
604Handling Reset
605--------------
606
607BL1 by default implements the reset vector where execution starts from a cold
608or warm boot. BL31 can be optionally set as a reset vector using the
609``RESET_TO_BL31`` make variable.
610
611For each CPU, the reset vector code is responsible for the following tasks:
612
613#. Distinguishing between a cold boot and a warm boot.
614
615#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
616 the CPU is placed in a platform-specific state until the primary CPU
617 performs the necessary steps to remove it from this state.
618
619#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
620 specific address in the BL31 image in the same processor mode as it was
621 when released from reset.
622
623The following functions need to be implemented by the platform port to enable
624reset vector code to perform the above tasks.
625
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100626Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
627~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100628
629::
630
631 Argument : void
632 Return : uintptr_t
633
634This function is called with the MMU and caches disabled
635(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
636distinguishing between a warm and cold reset for the current CPU using
637platform-specific means. If it's a warm reset, then it returns the warm
638reset entrypoint point provided to ``plat_setup_psci_ops()`` during
639BL31 initialization. If it's a cold reset then this function must return zero.
640
641This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000642Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100643not assume that callee saved registers are preserved across a call to this
644function.
645
646This function fulfills requirement 1 and 3 listed above.
647
648Note that for platforms that support programming the reset address, it is
649expected that a CPU will start executing code directly at the right address,
650both on a cold and warm reset. In this case, there is no need to identify the
651type of reset nor to query the warm reset entrypoint. Therefore, implementing
652this function is not required on such platforms.
653
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100654Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
655~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100656
657::
658
659 Argument : void
660
661This function is called with the MMU and data caches disabled. It is responsible
662for placing the executing secondary CPU in a platform-specific state until the
663primary CPU performs the necessary actions to bring it out of that state and
664allow entry into the OS. This function must not return.
665
Dan Handley610e7e12018-03-01 18:44:00 +0000666In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100667itself off. The primary CPU is responsible for powering up the secondary CPUs
668when normal world software requires them. When booting an EL3 payload instead,
669they stay powered on and are put in a holding pen until their mailbox gets
670populated.
671
672This function fulfills requirement 2 above.
673
674Note that for platforms that can't release secondary CPUs out of reset, only the
675primary CPU will execute the cold boot code. Therefore, implementing this
676function is not required on such platforms.
677
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100678Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
679~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100680
681::
682
683 Argument : void
684 Return : unsigned int
685
686This function identifies whether the current CPU is the primary CPU or a
687secondary CPU. A return value of zero indicates that the CPU is not the
688primary CPU, while a non-zero return value indicates that the CPU is the
689primary CPU.
690
691Note that for platforms that can't release secondary CPUs out of reset, only the
692primary CPU will execute the cold boot code. Therefore, there is no need to
693distinguish between primary and secondary CPUs and implementing this function is
694not required.
695
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100696Function : platform_mem_init() [mandatory]
697~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100698
699::
700
701 Argument : void
702 Return : void
703
704This function is called before any access to data is made by the firmware, in
705order to carry out any essential memory initialization.
706
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100707Function: plat_get_rotpk_info()
708~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100709
710::
711
712 Argument : void *, void **, unsigned int *, unsigned int *
713 Return : int
714
715This function is mandatory when Trusted Board Boot is enabled. It returns a
716pointer to the ROTPK stored in the platform (or a hash of it) and its length.
717The ROTPK must be encoded in DER format according to the following ASN.1
718structure:
719
720::
721
722 AlgorithmIdentifier ::= SEQUENCE {
723 algorithm OBJECT IDENTIFIER,
724 parameters ANY DEFINED BY algorithm OPTIONAL
725 }
726
727 SubjectPublicKeyInfo ::= SEQUENCE {
728 algorithm AlgorithmIdentifier,
729 subjectPublicKey BIT STRING
730 }
731
732In case the function returns a hash of the key:
733
734::
735
736 DigestInfo ::= SEQUENCE {
737 digestAlgorithm AlgorithmIdentifier,
738 digest OCTET STRING
739 }
740
741The function returns 0 on success. Any other value is treated as error by the
742Trusted Board Boot. The function also reports extra information related
743to the ROTPK in the flags parameter:
744
745::
746
747 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
748 hash.
749 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
750 verification while the platform ROTPK is not deployed.
751 When this flag is set, the function does not need to
752 return a platform ROTPK, and the authentication
753 framework uses the ROTPK in the certificate without
754 verifying it against the platform value. This flag
755 must not be used in a deployed production environment.
756
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100757Function: plat_get_nv_ctr()
758~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100759
760::
761
762 Argument : void *, unsigned int *
763 Return : int
764
765This function is mandatory when Trusted Board Boot is enabled. It returns the
766non-volatile counter value stored in the platform in the second argument. The
767cookie in the first argument may be used to select the counter in case the
768platform provides more than one (for example, on platforms that use the default
769TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100770TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100771
772The function returns 0 on success. Any other value means the counter value could
773not be retrieved from the platform.
774
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100775Function: plat_set_nv_ctr()
776~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100777
778::
779
780 Argument : void *, unsigned int
781 Return : int
782
783This function is mandatory when Trusted Board Boot is enabled. It sets a new
784counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100785select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100786the updated counter value to be written to the NV counter.
787
788The function returns 0 on success. Any other value means the counter value could
789not be updated.
790
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100791Function: plat_set_nv_ctr2()
792~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100793
794::
795
796 Argument : void *, const auth_img_desc_t *, unsigned int
797 Return : int
798
799This function is optional when Trusted Board Boot is enabled. If this
800interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
801first argument passed is a cookie and is typically used to
802differentiate between a Non Trusted NV Counter and a Trusted NV
803Counter. The second argument is a pointer to an authentication image
804descriptor and may be used to decide if the counter is allowed to be
805updated or not. The third argument is the updated counter value to
806be written to the NV counter.
807
808The function returns 0 on success. Any other value means the counter value
809either could not be updated or the authentication image descriptor indicates
810that it is not allowed to be updated.
811
Nicolas Toromanoff7f95ac82020-11-09 12:14:52 +0100812Function: plat_convert_pk()
813~~~~~~~~~~~~~~~~~~~~~~~~~~~
814
815::
816
817 Argument : void *, unsigned int, void **, unsigned int *
818 Return : int
819
820This function is optional when Trusted Board Boot is enabled, and only
821used if the platform saves a hash of the ROTPK.
822First argument is the Distinguished Encoding Rules (DER) ROTPK.
823Second argument is its size.
824Third argument is used to return a pointer to a buffer, which hash should
825be the one saved in OTP.
826Fourth argument is a pointer to return its size.
827
828Most platforms save the hash of the ROTPK, but some may save slightly different
829information - e.g the hash of the ROTPK plus some related information.
830Defining this function allows to transform the ROTPK used to verify
831the signature to the buffer (a platform specific public key) which
832hash is saved in OTP.
833
834The default implementation copies the input key and length to the output without
835modification.
836
837The function returns 0 on success. Any other value means the expected
838public key buffer cannot be extracted.
839
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +0100840Dynamic Root of Trust for Measurement support (in BL31)
841-------------------------------------------------------
842
843The functions mentioned in this section are mandatory, when platform enables
844DRTM_SUPPORT build flag.
845
846Function : plat_get_addr_mmap()
847~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
848
849::
850
851 Argument : void
852 Return : const mmap_region_t *
853
854This function is used to return the address of the platform *address-map* table,
855which describes the regions of normal memory, memory mapped I/O
856and non-volatile memory.
857
858Function : plat_has_non_host_platforms()
859~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
860
861::
862
863 Argument : void
864 Return : bool
865
866This function returns *true* if the platform has any trusted devices capable of
867DMA, otherwise returns *false*.
868
869Function : plat_has_unmanaged_dma_peripherals()
870~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
871
872::
873
874 Argument : void
875 Return : bool
876
877This function returns *true* if platform uses peripherals whose DMA is not
878managed by an SMMU, otherwise returns *false*.
879
880Note -
881If the platform has peripherals that are not managed by the SMMU, then the
882platform should investigate such peripherals to determine whether they can
883be trusted, and such peripherals should be moved under "Non-host platforms"
884if they can be trusted.
885
886Function : plat_get_total_num_smmus()
887~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
888
889::
890
891 Argument : void
892 Return : unsigned int
893
894This function returns the total number of SMMUs in the platform.
895
896Function : plat_enumerate_smmus()
897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
898::
899
900
901 Argument : void
902 Return : const uintptr_t *, size_t
903
904This function returns an array of SMMU addresses and the actual number of SMMUs
905reported by the platform.
906
907Function : plat_drtm_get_dma_prot_features()
908~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
909
910::
911
912 Argument : void
913 Return : const plat_drtm_dma_prot_features_t*
914
915This function returns the address of plat_drtm_dma_prot_features_t structure
916containing the maximum number of protected regions and bitmap with the types
917of DMA protection supported by the platform.
918For more details see section 3.3 Table 6 of `DRTM`_ specification.
919
920Function : plat_drtm_dma_prot_get_max_table_bytes()
921~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
922
923::
924
925 Argument : void
926 Return : uint64_t
927
928This function returns the maximum size of DMA protected regions table in
929bytes.
930
931Function : plat_drtm_get_tpm_features()
932~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
933
934::
935
936 Argument : void
937 Return : const plat_drtm_tpm_features_t*
938
939This function returns the address of *plat_drtm_tpm_features_t* structure
940containing PCR usage schema, TPM-based hash, and firmware hash algorithm
941supported by the platform.
942
943Function : plat_drtm_get_min_size_normal_world_dce()
944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
945
946::
947
948 Argument : void
949 Return : uint64_t
950
951This function returns the size normal-world DCE of the platform.
952
953Function : plat_drtm_get_imp_def_dlme_region_size()
954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
955
956::
957
958 Argument : void
959 Return : uint64_t
960
961This function returns the size of implementation defined DLME region
962of the platform.
963
964Function : plat_drtm_get_tcb_hash_table_size()
965~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
966
967::
968
969 Argument : void
970 Return : uint64_t
971
972This function returns the size of TCB hash table of the platform.
973
974Function : plat_drtm_get_tcb_hash_features()
975~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
976
977::
978
979 Argument : void
980 Return : uint64_t
981
982This function returns the Maximum number of TCB hashes recorded by the
983platform.
984For more details see section 3.3 Table 6 of `DRTM`_ specification.
985
986Function : plat_drtm_validate_ns_region()
987~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
988
989::
990
991 Argument : uintptr_t, uintptr_t
992 Return : int
993
994This function validates that given region is within the Non-Secure region
995of DRAM. This function takes a region start address and size an input
996arguments, and returns 0 on success and -1 on failure.
997
998Function : plat_set_drtm_error()
999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1000
1001::
1002
1003 Argument : uint64_t
1004 Return : int
1005
1006This function writes a 64 bit error code received as input into
1007non-volatile storage and returns 0 on success and -1 on failure.
1008
1009Function : plat_get_drtm_error()
1010~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1011
1012::
1013
1014 Argument : uint64_t*
1015 Return : int
1016
1017This function reads a 64 bit error code from the non-volatile storage
1018into the received address, and returns 0 on success and -1 on failure.
1019
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001020Common mandatory function modifications
1021---------------------------------------
1022
1023The following functions are mandatory functions which need to be implemented
1024by the platform port.
1025
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001026Function : plat_my_core_pos()
1027~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001028
1029::
1030
1031 Argument : void
1032 Return : unsigned int
1033
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001034This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001035CPU-specific linear index into blocks of memory (for example while allocating
1036per-CPU stacks). This function will be invoked very early in the
1037initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001038implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001039runtime environment. This function can clobber x0 - x8 and must preserve
1040x9 - x29.
1041
1042This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +01001043PSCI and details of this can be found in
1044:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001045
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001046Function : plat_core_pos_by_mpidr()
1047~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001048
1049::
1050
1051 Argument : u_register_t
1052 Return : int
1053
1054This function validates the ``MPIDR`` of a CPU and converts it to an index,
1055which can be used as a CPU-specific linear index into blocks of memory. In
1056case the ``MPIDR`` is invalid, this function returns -1. This function will only
1057be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +00001058utilize the C runtime environment. For further details about how TF-A
1059represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +01001060index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001061
Ambroise Vincentd207f562019-04-10 12:50:27 +01001062Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
1063~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1064
1065::
1066
1067 Arguments : void **heap_addr, size_t *heap_size
1068 Return : int
1069
1070This function is invoked during Mbed TLS library initialisation to get a heap,
1071by means of a starting address and a size. This heap will then be used
1072internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
1073must be able to provide a heap to it.
1074
1075A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
1076which a heap is statically reserved during compile time inside every image
1077(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
1078the function simply returns the address and size of this "pre-allocated" heap.
1079For a platform to use this default implementation, only a call to the helper
1080from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
1081
1082However, by writting their own implementation, platforms have the potential to
1083optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
1084shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
1085twice.
1086
1087On success the function should return 0 and a negative error code otherwise.
1088
Sumit Gargc0c369c2019-11-15 18:47:53 +05301089Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
1090~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1091
1092::
1093
1094 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
1095 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
1096 size_t img_id_len
1097 Return : int
1098
1099This function provides a symmetric key (either SSK or BSSK depending on
1100fw_enc_status) which is invoked during runtime decryption of encrypted
1101firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
1102implementation for testing purposes which must be overridden by the platform
1103trying to implement a real world firmware encryption use-case.
1104
1105It also allows the platform to pass symmetric key identifier rather than
1106actual symmetric key which is useful in cases where the crypto backend provides
1107secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
1108flag must be set in ``flags``.
1109
1110In addition to above a platform may also choose to provide an image specific
1111symmetric key/identifier using img_id.
1112
1113On success the function should return 0 and a negative error code otherwise.
1114
Manish Pandey34a305e2021-10-21 21:53:49 +01001115Note that this API depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +05301116
Manish V Badarkheda87af12021-06-20 21:14:46 +01001117Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
1118~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1119
1120::
1121
Sughosh Ganuf40154f2021-11-17 17:08:10 +05301122 Argument : const struct fwu_metadata *metadata
Manish V Badarkheda87af12021-06-20 21:14:46 +01001123 Return : void
1124
1125This function is mandatory when PSA_FWU_SUPPORT is enabled.
1126It provides a means to retrieve image specification (offset in
1127non-volatile storage and length) of active/updated images using the passed
1128FWU metadata, and update I/O policies of active/updated images using retrieved
1129image specification information.
1130Further I/O layer operations such as I/O open, I/O read, etc. on these
1131images rely on this function call.
1132
1133In Arm platforms, this function is used to set an I/O policy of the FIP image,
1134container of all active/updated secure and non-secure images.
1135
1136Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
1137~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1138
1139::
1140
1141 Argument : unsigned int image_id, uintptr_t *dev_handle,
1142 uintptr_t *image_spec
1143 Return : int
1144
1145This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
1146responsible for setting up the platform I/O policy of the requested metadata
1147image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
1148be used to load this image from the platform's non-volatile storage.
1149
1150FWU metadata can not be always stored as a raw image in non-volatile storage
1151to define its image specification (offset in non-volatile storage and length)
1152statically in I/O policy.
1153For example, the FWU metadata image is stored as a partition inside the GUID
1154partition table image. Its specification is defined in the partition table
1155that needs to be parsed dynamically.
1156This function provides a means to retrieve such dynamic information to set
1157the I/O policy of the FWU metadata image.
1158Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
1159image relies on this function call.
1160
1161It returns '0' on success, otherwise a negative error value on error.
1162Alongside, returns device handle and image specification from the I/O policy
1163of the requested FWU metadata image.
1164
Sughosh Ganu4e336a62021-12-01 15:53:32 +05301165Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1]
1166~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1167
1168::
1169
1170 Argument : void
1171 Return : uint32_t
1172
1173This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the
1174means to retrieve the boot index value from the platform. The boot index is the
1175bank from which the platform has booted the firmware images.
1176
1177By default, the platform will read the metadata structure and try to boot from
1178the active bank. If the platform fails to boot from the active bank due to
1179reasons like an Authentication failure, or on crossing a set number of watchdog
1180resets while booting from the active bank, the platform can then switch to boot
1181from a different bank. This function then returns the bank that the platform
1182should boot its images from.
1183
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001184Common optional modifications
1185-----------------------------
1186
1187The following are helper functions implemented by the firmware that perform
1188common platform-specific tasks. A platform may choose to override these
1189definitions.
1190
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001191Function : plat_set_my_stack()
1192~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001193
1194::
1195
1196 Argument : void
1197 Return : void
1198
1199This function sets the current stack pointer to the normal memory stack that
1200has been allocated for the current CPU. For BL images that only require a
1201stack for the primary CPU, the UP version of the function is used. The size
1202of the stack allocated to each CPU is specified by the platform defined
1203constant ``PLATFORM_STACK_SIZE``.
1204
1205Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001206provided in ``plat/common/aarch64/platform_up_stack.S`` and
1207``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001208
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001209Function : plat_get_my_stack()
1210~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001211
1212::
1213
1214 Argument : void
1215 Return : uintptr_t
1216
1217This function returns the base address of the normal memory stack that
1218has been allocated for the current CPU. For BL images that only require a
1219stack for the primary CPU, the UP version of the function is used. The size
1220of the stack allocated to each CPU is specified by the platform defined
1221constant ``PLATFORM_STACK_SIZE``.
1222
1223Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +01001224provided in ``plat/common/aarch64/platform_up_stack.S`` and
1225``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001226
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001227Function : plat_report_exception()
1228~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001229
1230::
1231
1232 Argument : unsigned int
1233 Return : void
1234
1235A platform may need to report various information about its status when an
1236exception is taken, for example the current exception level, the CPU security
1237state (secure/non-secure), the exception type, and so on. This function is
1238called in the following circumstances:
1239
1240- In BL1, whenever an exception is taken.
1241- In BL2, whenever an exception is taken.
1242
1243The default implementation doesn't do anything, to avoid making assumptions
1244about the way the platform displays its status information.
1245
1246For AArch64, this function receives the exception type as its argument.
1247Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001248``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +00001249related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001250
1251For AArch32, this function receives the exception mode as its argument.
1252Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001253``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001254
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001255Function : plat_reset_handler()
1256~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001257
1258::
1259
1260 Argument : void
1261 Return : void
1262
1263A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001264allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001265specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001266preserve the values of callee saved registers x19 to x29.
1267
1268The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +01001269the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001270guidelines.
1271
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001272Function : plat_disable_acp()
1273~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001274
1275::
1276
1277 Argument : void
1278 Return : void
1279
John Tsichritzis6dda9762018-07-23 09:18:04 +01001280This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001281present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001282doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001283it has restrictions for stack usage and it can use the registers x0 - x17 as
1284scratch registers. It should preserve the value in x18 register as it is used
1285by the caller to store the return address.
1286
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001287Function : plat_error_handler()
1288~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001289
1290::
1291
1292 Argument : int
1293 Return : void
1294
1295This API is called when the generic code encounters an error situation from
1296which it cannot continue. It allows the platform to perform error reporting or
1297recovery actions (for example, reset the system). This function must not return.
1298
1299The parameter indicates the type of error using standard codes from ``errno.h``.
1300Possible errors reported by the generic code are:
1301
1302- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1303 Board Boot is enabled)
1304- ``-ENOENT``: the requested image or certificate could not be found or an IO
1305 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001306- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1307 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001308
1309The default implementation simply spins.
1310
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001311Function : plat_panic_handler()
1312~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001313
1314::
1315
1316 Argument : void
1317 Return : void
1318
1319This API is called when the generic code encounters an unexpected error
1320situation from which it cannot recover. This function must not return,
1321and must be implemented in assembly because it may be called before the C
1322environment is initialized.
1323
Paul Beesleyba3ed402019-03-13 16:20:44 +00001324.. note::
1325 The address from where it was called is stored in x30 (Link Register).
1326 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001327
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01001328Function : plat_system_reset()
1329~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1330
1331::
1332
1333 Argument : void
1334 Return : void
1335
1336This function is used by the platform to resets the system. It can be used
1337in any specific use-case where system needs to be resetted. For example,
1338in case of DRTM implementation this function reset the system after
1339writing the DRTM error code in the non-volatile storage. This function
1340never returns. Failure in reset results in panic.
1341
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001342Function : plat_get_bl_image_load_info()
1343~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001344
1345::
1346
1347 Argument : void
1348 Return : bl_load_info_t *
1349
1350This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001351populated to load. This function is invoked in BL2 to load the
1352BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001353
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001354Function : plat_get_next_bl_params()
1355~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001356
1357::
1358
1359 Argument : void
1360 Return : bl_params_t *
1361
1362This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001363kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001364function is invoked in BL2 to pass this information to the next BL
1365image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001366
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001367Function : plat_get_stack_protector_canary()
1368~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001369
1370::
1371
1372 Argument : void
1373 Return : u_register_t
1374
1375This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001376when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001377value will weaken the protection as the attacker could easily write the right
1378value as part of the attack most of the time. Therefore, it should return a
1379true random number.
1380
Paul Beesleyba3ed402019-03-13 16:20:44 +00001381.. warning::
1382 For the protection to be effective, the global data need to be placed at
1383 a lower address than the stack bases. Failure to do so would allow an
1384 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001386Function : plat_flush_next_bl_params()
1387~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001388
1389::
1390
1391 Argument : void
1392 Return : void
1393
1394This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001395next image. This function is invoked in BL2 to flush this information
1396to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001397
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001398Function : plat_log_get_prefix()
1399~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001400
1401::
1402
1403 Argument : unsigned int
1404 Return : const char *
1405
1406This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001407prepended to all the log output from TF-A. The `log_level` (argument) will
1408correspond to one of the standard log levels defined in debug.h. The platform
1409can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001410the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001411increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001412
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001413Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001414~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001415
1416::
1417
1418 Argument : void
1419 Return : int32_t
1420
1421This function returns soc version which mainly consist of below fields
1422
1423::
1424
1425 soc_version[30:24] = JEP-106 continuation code for the SiP
1426 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001427 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001428
1429Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001430~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001431
1432::
1433
1434 Argument : void
1435 Return : int32_t
1436
1437This function returns soc revision in below format
1438
1439::
1440
1441 soc_revision[0:30] = SOC revision of specific SOC
1442
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001443Function : plat_is_smccc_feature_available()
1444~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1445
1446::
1447
1448 Argument : u_register_t
1449 Return : int32_t
1450
1451This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1452the SMCCC function specified in the argument; otherwise returns
1453SMC_ARCH_CALL_NOT_SUPPORTED.
1454
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001455Function : plat_mboot_measure_image()
1456~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1457
1458::
1459
1460 Argument : unsigned int, image_info_t *
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001461 Return : int
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001462
1463When the MEASURED_BOOT flag is enabled:
1464
1465- This function measures the given image and records its measurement using
1466 the measured boot backend driver.
1467- On the Arm FVP port, this function measures the given image using its
1468 passed id and information and then records that measurement in the
1469 Event Log buffer.
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001470- This function must return 0 on success, a signed integer error code
1471 otherwise.
1472
1473When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1474
1475Function : plat_mboot_measure_critical_data()
1476~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1477
1478::
1479
1480 Argument : unsigned int, const void *, size_t
1481 Return : int
1482
1483When the MEASURED_BOOT flag is enabled:
1484
1485- This function measures the given critical data structure and records its
1486 measurement using the measured boot backend driver.
1487- This function must return 0 on success, a signed integer error code
1488 otherwise.
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001489
1490When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1491
Okash Khawaja037b56e2022-11-04 12:38:01 +00001492Function : plat_can_cmo()
1493~~~~~~~~~~~~~~~~~~~~~~~~~
1494
1495::
1496
1497 Argument : void
1498 Return : uint64_t
1499
1500When CONDITIONAL_CMO flag is enabled:
1501
1502- This function indicates whether cache management operations should be
1503 performed. It returns 0 if CMOs should be skipped and non-zero
1504 otherwise.
Okash Khawaja94532202022-11-14 12:50:30 +00001505- The function must not clobber x1, x2 and x3. It's also not safe to rely on
1506 stack. Otherwise obey AAPCS.
Okash Khawaja037b56e2022-11-04 12:38:01 +00001507
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001508Modifications specific to a Boot Loader stage
1509---------------------------------------------
1510
1511Boot Loader Stage 1 (BL1)
1512-------------------------
1513
1514BL1 implements the reset vector where execution starts from after a cold or
1515warm boot. For each CPU, BL1 is responsible for the following tasks:
1516
1517#. Handling the reset as described in section 2.2
1518
1519#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1520 only this CPU executes the remaining BL1 code, including loading and passing
1521 control to the BL2 stage.
1522
1523#. Identifying and starting the Firmware Update process (if required).
1524
1525#. Loading the BL2 image from non-volatile storage into secure memory at the
1526 address specified by the platform defined constant ``BL2_BASE``.
1527
1528#. Populating a ``meminfo`` structure with the following information in memory,
1529 accessible by BL2 immediately upon entry.
1530
1531 ::
1532
1533 meminfo.total_base = Base address of secure RAM visible to BL2
1534 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001535
Soby Mathew97b1bff2018-09-27 16:46:41 +01001536 By default, BL1 places this ``meminfo`` structure at the end of secure
1537 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001538
Soby Mathewb1bf0442018-02-16 14:52:52 +00001539 It is possible for the platform to decide where it wants to place the
1540 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1541 BL2 by overriding the weak default implementation of
1542 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001543
1544The following functions need to be implemented by the platform port to enable
1545BL1 to perform the above tasks.
1546
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001547Function : bl1_early_platform_setup() [mandatory]
1548~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001549
1550::
1551
1552 Argument : void
1553 Return : void
1554
1555This function executes with the MMU and data caches disabled. It is only called
1556by the primary CPU.
1557
Dan Handley610e7e12018-03-01 18:44:00 +00001558On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001559
1560- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1561
1562- Initializes a UART (PL011 console), which enables access to the ``printf``
1563 family of functions in BL1.
1564
1565- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1566 the CCI slave interface corresponding to the cluster that includes the
1567 primary CPU.
1568
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001569Function : bl1_plat_arch_setup() [mandatory]
1570~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001571
1572::
1573
1574 Argument : void
1575 Return : void
1576
1577This function performs any platform-specific and architectural setup that the
1578platform requires. Platform-specific setup might include configuration of
1579memory controllers and the interconnect.
1580
Dan Handley610e7e12018-03-01 18:44:00 +00001581In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001582
1583This function helps fulfill requirement 2 above.
1584
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001585Function : bl1_platform_setup() [mandatory]
1586~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001587
1588::
1589
1590 Argument : void
1591 Return : void
1592
1593This function executes with the MMU and data caches enabled. It is responsible
1594for performing any remaining platform-specific setup that can occur after the
1595MMU and data cache have been enabled.
1596
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001597if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001598sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001599
Dan Handley610e7e12018-03-01 18:44:00 +00001600In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001601layer used to load the next bootloader image.
1602
1603This function helps fulfill requirement 4 above.
1604
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001605Function : bl1_plat_sec_mem_layout() [mandatory]
1606~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001607
1608::
1609
1610 Argument : void
1611 Return : meminfo *
1612
1613This function should only be called on the cold boot path. It executes with the
1614MMU and data caches enabled. The pointer returned by this function must point to
1615a ``meminfo`` structure containing the extents and availability of secure RAM for
1616the BL1 stage.
1617
1618::
1619
1620 meminfo.total_base = Base address of secure RAM visible to BL1
1621 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001622
1623This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1624populates a similar structure to tell BL2 the extents of memory available for
1625its own use.
1626
1627This function helps fulfill requirements 4 and 5 above.
1628
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001629Function : bl1_plat_prepare_exit() [optional]
1630~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001631
1632::
1633
1634 Argument : entry_point_info_t *
1635 Return : void
1636
1637This function is called prior to exiting BL1 in response to the
1638``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1639platform specific clean up or bookkeeping operations before transferring
1640control to the next image. It receives the address of the ``entry_point_info_t``
1641structure passed from BL2. This function runs with MMU disabled.
1642
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001643Function : bl1_plat_set_ep_info() [optional]
1644~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001645
1646::
1647
1648 Argument : unsigned int image_id, entry_point_info_t *ep_info
1649 Return : void
1650
1651This function allows platforms to override ``ep_info`` for the given ``image_id``.
1652
1653The default implementation just returns.
1654
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001655Function : bl1_plat_get_next_image_id() [optional]
1656~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001657
1658::
1659
1660 Argument : void
1661 Return : unsigned int
1662
1663This and the following function must be overridden to enable the FWU feature.
1664
1665BL1 calls this function after platform setup to identify the next image to be
1666loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1667with the normal boot sequence, which loads and executes BL2. If the platform
1668returns a different image id, BL1 assumes that Firmware Update is required.
1669
Dan Handley610e7e12018-03-01 18:44:00 +00001670The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001671platforms override this function to detect if firmware update is required, and
1672if so, return the first image in the firmware update process.
1673
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001674Function : bl1_plat_get_image_desc() [optional]
1675~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001676
1677::
1678
1679 Argument : unsigned int image_id
1680 Return : image_desc_t *
1681
1682BL1 calls this function to get the image descriptor information ``image_desc_t``
1683for the provided ``image_id`` from the platform.
1684
Dan Handley610e7e12018-03-01 18:44:00 +00001685The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001686standard platforms return an image descriptor corresponding to BL2 or one of
1687the firmware update images defined in the Trusted Board Boot Requirements
1688specification.
1689
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001690Function : bl1_plat_handle_pre_image_load() [optional]
1691~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001692
1693::
1694
Soby Mathew2f38ce32018-02-08 17:45:12 +00001695 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001696 Return : int
1697
1698This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001699corresponding to ``image_id``. This function is invoked in BL1, both in cold
1700boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001701
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001702Function : bl1_plat_handle_post_image_load() [optional]
1703~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001704
1705::
1706
Soby Mathew2f38ce32018-02-08 17:45:12 +00001707 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001708 Return : int
1709
1710This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001711corresponding to ``image_id``. This function is invoked in BL1, both in cold
1712boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001713
Soby Mathewb1bf0442018-02-16 14:52:52 +00001714The default weak implementation of this function calculates the amount of
1715Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1716structure at the beginning of this free memory and populates it. The address
1717of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1718information to BL2.
1719
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001720Function : bl1_plat_fwu_done() [optional]
1721~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001722
1723::
1724
1725 Argument : unsigned int image_id, uintptr_t image_src,
1726 unsigned int image_size
1727 Return : void
1728
1729BL1 calls this function when the FWU process is complete. It must not return.
1730The platform may override this function to take platform specific action, for
1731example to initiate the normal boot flow.
1732
1733The default implementation spins forever.
1734
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001735Function : bl1_plat_mem_check() [mandatory]
1736~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001737
1738::
1739
1740 Argument : uintptr_t mem_base, unsigned int mem_size,
1741 unsigned int flags
1742 Return : int
1743
1744BL1 calls this function while handling FWU related SMCs, more specifically when
1745copying or authenticating an image. Its responsibility is to ensure that the
1746region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1747that this memory corresponds to either a secure or non-secure memory region as
1748indicated by the security state of the ``flags`` argument.
1749
1750This function can safely assume that the value resulting from the addition of
1751``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1752overflow.
1753
1754This function must return 0 on success, a non-null error code otherwise.
1755
1756The default implementation of this function asserts therefore platforms must
1757override it when using the FWU feature.
1758
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001759Function : bl1_plat_mboot_init() [optional]
1760~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1761
1762::
1763
1764 Argument : void
1765 Return : void
1766
1767When the MEASURED_BOOT flag is enabled:
1768
1769- This function is used to initialize the backend driver(s) of measured boot.
1770- On the Arm FVP port, this function is used to initialize the Event Log
1771 backend driver, and also to write header information in the Event Log buffer.
1772
1773When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1774
1775Function : bl1_plat_mboot_finish() [optional]
1776~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1777
1778::
1779
1780 Argument : void
1781 Return : void
1782
1783When the MEASURED_BOOT flag is enabled:
1784
1785- This function is used to finalize the measured boot backend driver(s),
1786 and also, set the information for the next bootloader component to
1787 extend the measurement if needed.
1788- On the Arm FVP port, this function is used to pass the base address of
1789 the Event Log buffer and its size to BL2 via tb_fw_config to extend the
1790 Event Log buffer with the measurement of various images loaded by BL2.
1791 It results in panic on error.
1792
1793When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1794
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001795Boot Loader Stage 2 (BL2)
1796-------------------------
1797
1798The BL2 stage is executed only by the primary CPU, which is determined in BL1
1799using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001800``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1801``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1802non-volatile storage to secure/non-secure RAM. After all the images are loaded
1803then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1804images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001805
1806The following functions must be implemented by the platform port to enable BL2
1807to perform the above tasks.
1808
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001809Function : bl2_early_platform_setup2() [mandatory]
1810~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001811
1812::
1813
Soby Mathew97b1bff2018-09-27 16:46:41 +01001814 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001815 Return : void
1816
1817This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001818by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1819are platform specific.
1820
1821On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001822
Manish V Badarkhe81414512020-06-24 15:58:38 +01001823 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001824
1825 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1826 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001827
Dan Handley610e7e12018-03-01 18:44:00 +00001828On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001829
1830- Initializes a UART (PL011 console), which enables access to the ``printf``
1831 family of functions in BL2.
1832
1833- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001834 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1835 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001836
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001837Function : bl2_plat_arch_setup() [mandatory]
1838~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001839
1840::
1841
1842 Argument : void
1843 Return : void
1844
1845This function executes with the MMU and data caches disabled. It is only called
1846by the primary CPU.
1847
1848The purpose of this function is to perform any architectural initialization
1849that varies across platforms.
1850
Dan Handley610e7e12018-03-01 18:44:00 +00001851On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001852
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001853Function : bl2_platform_setup() [mandatory]
1854~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001855
1856::
1857
1858 Argument : void
1859 Return : void
1860
1861This function may execute with the MMU and data caches enabled if the platform
1862port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1863called by the primary CPU.
1864
1865The purpose of this function is to perform any platform initialization
1866specific to BL2.
1867
Dan Handley610e7e12018-03-01 18:44:00 +00001868In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001869configuration of the TrustZone controller to allow non-secure masters access
1870to most of DRAM. Part of DRAM is reserved for secure world use.
1871
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001872Function : bl2_plat_handle_pre_image_load() [optional]
1873~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001874
1875::
1876
1877 Argument : unsigned int
1878 Return : int
1879
1880This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001881for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001882loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001883
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001884Function : bl2_plat_handle_post_image_load() [optional]
1885~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001886
1887::
1888
1889 Argument : unsigned int
1890 Return : int
1891
1892This function can be used by the platforms to update/use image information
1893for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001894loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001895
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001896Function : bl2_plat_preload_setup [optional]
1897~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001898
1899::
John Tsichritzisee10e792018-06-06 09:38:10 +01001900
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001901 Argument : void
1902 Return : void
1903
1904This optional function performs any BL2 platform initialization
1905required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001906bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001907boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001908plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001909
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001910Function : plat_try_next_boot_source() [optional]
1911~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001912
1913::
John Tsichritzisee10e792018-06-06 09:38:10 +01001914
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001915 Argument : void
1916 Return : int
1917
1918This optional function passes to the next boot source in the redundancy
1919sequence.
1920
1921This function moves the current boot redundancy source to the next
1922element in the boot sequence. If there are no more boot sources then it
1923must return 0, otherwise it must return 1. The default implementation
1924of this always returns 0.
1925
Sandrine Bailleuxeb5fadc2022-07-13 10:07:54 +02001926Function : bl2_plat_mboot_init() [optional]
1927~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1928
1929::
1930
1931 Argument : void
1932 Return : void
1933
1934When the MEASURED_BOOT flag is enabled:
1935
1936- This function is used to initialize the backend driver(s) of measured boot.
1937- On the Arm FVP port, this function is used to initialize the Event Log
1938 backend driver with the Event Log buffer information (base address and
1939 size) received from BL1. It results in panic on error.
1940
1941When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1942
1943Function : bl2_plat_mboot_finish() [optional]
1944~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1945
1946::
1947
1948 Argument : void
1949 Return : void
1950
1951When the MEASURED_BOOT flag is enabled:
1952
1953- This function is used to finalize the measured boot backend driver(s),
1954 and also, set the information for the next bootloader component to extend
1955 the measurement if needed.
1956- On the Arm FVP port, this function is used to pass the Event Log buffer
1957 information (base address and size) to non-secure(BL33) and trusted OS(BL32)
1958 via nt_fw and tos_fw config respectively. It results in panic on error.
1959
1960When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1961
Roberto Vargasb1584272017-11-20 13:36:10 +00001962Boot Loader Stage 2 (BL2) at EL3
1963--------------------------------
1964
Dan Handley610e7e12018-03-01 18:44:00 +00001965When the platform has a non-TF-A Boot ROM it is desirable to jump
1966directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01001967execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
1968document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00001969
1970All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001971bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1972their work is done now by bl2_el3_early_platform_setup and
1973bl2_el3_plat_arch_setup. These functions should generally implement
1974the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001975
1976
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001977Function : bl2_el3_early_platform_setup() [mandatory]
1978~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001979
1980::
John Tsichritzisee10e792018-06-06 09:38:10 +01001981
Roberto Vargasb1584272017-11-20 13:36:10 +00001982 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1983 Return : void
1984
1985This function executes with the MMU and data caches disabled. It is only called
1986by the primary CPU. This function receives four parameters which can be used
1987by the platform to pass any needed information from the Boot ROM to BL2.
1988
Dan Handley610e7e12018-03-01 18:44:00 +00001989On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001990
1991- Initializes a UART (PL011 console), which enables access to the ``printf``
1992 family of functions in BL2.
1993
1994- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001995 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1996 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001997
1998- Initializes the private variables that define the memory layout used.
1999
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002000Function : bl2_el3_plat_arch_setup() [mandatory]
2001~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00002002
2003::
John Tsichritzisee10e792018-06-06 09:38:10 +01002004
Roberto Vargasb1584272017-11-20 13:36:10 +00002005 Argument : void
2006 Return : void
2007
2008This function executes with the MMU and data caches disabled. It is only called
2009by the primary CPU.
2010
2011The purpose of this function is to perform any architectural initialization
2012that varies across platforms.
2013
Dan Handley610e7e12018-03-01 18:44:00 +00002014On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00002015
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002016Function : bl2_el3_plat_prepare_exit() [optional]
2017~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00002018
2019::
John Tsichritzisee10e792018-06-06 09:38:10 +01002020
Roberto Vargasb1584272017-11-20 13:36:10 +00002021 Argument : void
2022 Return : void
2023
2024This function is called prior to exiting BL2 and run the next image.
2025It should be used to perform platform specific clean up or bookkeeping
2026operations before transferring control to the next image. This function
2027runs with MMU disabled.
2028
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002029FWU Boot Loader Stage 2 (BL2U)
2030------------------------------
2031
2032The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
2033process and is executed only by the primary CPU. BL1 passes control to BL2U at
2034``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
2035
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002036#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
2037 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
2038 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
2039 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002040 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
2041 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
2042
2043#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00002044 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002045 normal world can access DDR memory.
2046
2047The following functions must be implemented by the platform port to enable
2048BL2U to perform the tasks mentioned above.
2049
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002050Function : bl2u_early_platform_setup() [mandatory]
2051~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002052
2053::
2054
2055 Argument : meminfo *mem_info, void *plat_info
2056 Return : void
2057
2058This function executes with the MMU and data caches disabled. It is only
2059called by the primary CPU. The arguments to this function is the address
2060of the ``meminfo`` structure and platform specific info provided by BL1.
2061
2062The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
2063private storage as the original memory may be subsequently overwritten by BL2U.
2064
Dan Handley610e7e12018-03-01 18:44:00 +00002065On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002066to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002067variable.
2068
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002069Function : bl2u_plat_arch_setup() [mandatory]
2070~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002071
2072::
2073
2074 Argument : void
2075 Return : void
2076
2077This function executes with the MMU and data caches disabled. It is only
2078called by the primary CPU.
2079
2080The purpose of this function is to perform any architectural initialization
2081that varies across platforms, for example enabling the MMU (since the memory
2082map differs across platforms).
2083
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002084Function : bl2u_platform_setup() [mandatory]
2085~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002086
2087::
2088
2089 Argument : void
2090 Return : void
2091
2092This function may execute with the MMU and data caches enabled if the platform
2093port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
2094called by the primary CPU.
2095
2096The purpose of this function is to perform any platform initialization
2097specific to BL2U.
2098
Dan Handley610e7e12018-03-01 18:44:00 +00002099In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002100configuration of the TrustZone controller to allow non-secure masters access
2101to most of DRAM. Part of DRAM is reserved for secure world use.
2102
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002103Function : bl2u_plat_handle_scp_bl2u() [optional]
2104~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002105
2106::
2107
2108 Argument : void
2109 Return : int
2110
2111This function is used to perform any platform-specific actions required to
2112handle the SCP firmware. Typically it transfers the image into SCP memory using
2113a platform-specific protocol and waits until SCP executes it and signals to the
2114Application Processor (AP) for BL2U execution to continue.
2115
2116This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002117This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002118
2119Boot Loader Stage 3-1 (BL31)
2120----------------------------
2121
2122During cold boot, the BL31 stage is executed only by the primary CPU. This is
2123determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
2124control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
2125CPUs. BL31 executes at EL3 and is responsible for:
2126
2127#. Re-initializing all architectural and platform state. Although BL1 performs
2128 some of this initialization, BL31 remains resident in EL3 and must ensure
2129 that EL3 architectural and platform state is completely initialized. It
2130 should make no assumptions about the system state when it receives control.
2131
2132#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01002133 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
2134 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002135
2136#. Providing runtime firmware services. Currently, BL31 only implements a
2137 subset of the Power State Coordination Interface (PSCI) API as a runtime
Boyan Karatotev907d38b2022-11-22 12:01:09 +00002138 service. See :ref:`psci_in_bl31` below for details of porting the PSCI
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002139 implementation.
2140
2141#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002142 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002143 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01002144 executed and run the corresponding image. On ARM platforms, BL31 uses the
2145 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002146
2147If BL31 is a reset vector, It also needs to handle the reset as specified in
2148section 2.2 before the tasks described above.
2149
2150The following functions must be implemented by the platform port to enable BL31
2151to perform the above tasks.
2152
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002153Function : bl31_early_platform_setup2() [mandatory]
2154~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002155
2156::
2157
Soby Mathew97b1bff2018-09-27 16:46:41 +01002158 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002159 Return : void
2160
2161This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01002162by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
2163platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002164
Soby Mathew97b1bff2018-09-27 16:46:41 +01002165In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002166
Soby Mathew97b1bff2018-09-27 16:46:41 +01002167 arg0 - The pointer to the head of `bl_params_t` list
2168 which is list of executable images following BL31,
2169
2170 arg1 - Points to load address of SOC_FW_CONFIG if present
Mikael Olsson0232da22021-02-12 17:30:16 +01002171 except in case of Arm FVP and Juno platform.
Manish V Badarkhe81414512020-06-24 15:58:38 +01002172
Mikael Olsson0232da22021-02-12 17:30:16 +01002173 In case of Arm FVP and Juno platform, points to load address
Manish V Badarkhe81414512020-06-24 15:58:38 +01002174 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01002175
2176 arg2 - Points to load address of HW_CONFIG if present
2177
2178 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
2179 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002180
Soby Mathew97b1bff2018-09-27 16:46:41 +01002181The function runs through the `bl_param_t` list and extracts the entry point
2182information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002183
2184- Initialize a UART (PL011 console), which enables access to the ``printf``
2185 family of functions in BL31.
2186
2187- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
2188 CCI slave interface corresponding to the cluster that includes the primary
2189 CPU.
2190
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002191Function : bl31_plat_arch_setup() [mandatory]
2192~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002193
2194::
2195
2196 Argument : void
2197 Return : void
2198
2199This function executes with the MMU and data caches disabled. It is only called
2200by the primary CPU.
2201
2202The purpose of this function is to perform any architectural initialization
2203that varies across platforms.
2204
Dan Handley610e7e12018-03-01 18:44:00 +00002205On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002206
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002207Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002208~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2209
2210::
2211
2212 Argument : void
2213 Return : void
2214
2215This function may execute with the MMU and data caches enabled if the platform
2216port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
2217called by the primary CPU.
2218
2219The purpose of this function is to complete platform initialization so that both
2220BL31 runtime services and normal world software can function correctly.
2221
Dan Handley610e7e12018-03-01 18:44:00 +00002222On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002223
2224- Initialize the generic interrupt controller.
2225
2226 Depending on the GIC driver selected by the platform, the appropriate GICv2
2227 or GICv3 initialization will be done, which mainly consists of:
2228
2229 - Enable secure interrupts in the GIC CPU interface.
2230 - Disable the legacy interrupt bypass mechanism.
2231 - Configure the priority mask register to allow interrupts of all priorities
2232 to be signaled to the CPU interface.
2233 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
2234 - Target all secure SPIs to CPU0.
2235 - Enable these secure interrupts in the GIC distributor.
2236 - Configure all other interrupts as non-secure.
2237 - Enable signaling of secure interrupts in the GIC distributor.
2238
2239- Enable system-level implementation of the generic timer counter through the
2240 memory mapped interface.
2241
2242- Grant access to the system counter timer module
2243
2244- Initialize the power controller device.
2245
2246 In particular, initialise the locks that prevent concurrent accesses to the
2247 power controller device.
2248
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002249Function : bl31_plat_runtime_setup() [optional]
2250~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002251
2252::
2253
2254 Argument : void
2255 Return : void
2256
2257The purpose of this function is allow the platform to perform any BL31 runtime
2258setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07002259implementation of this function will invoke ``console_switch_state()`` to switch
2260console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002261
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002262Function : bl31_plat_get_next_image_ep_info() [mandatory]
2263~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002264
2265::
2266
Sandrine Bailleux842117d2018-05-14 14:25:47 +02002267 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002268 Return : entry_point_info *
2269
2270This function may execute with the MMU and data caches enabled if the platform
2271port does the necessary initializations in ``bl31_plat_arch_setup()``.
2272
2273This function is called by ``bl31_main()`` to retrieve information provided by
2274BL2 for the next image in the security state specified by the argument. BL31
2275uses this information to pass control to that image in the specified security
2276state. This function must return a pointer to the ``entry_point_info`` structure
2277(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
2278should return NULL otherwise.
2279
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002280Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1]
Soby Mathew294e1cf2022-03-22 16:19:39 +00002281~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2282
2283::
2284
2285 Argument : uintptr_t, size_t *, uintptr_t, size_t
2286 Return : int
2287
2288This function returns the Platform attestation token.
2289
2290The parameters of the function are:
2291
2292 arg0 - A pointer to the buffer where the Platform token should be copied by
2293 this function. The buffer must be big enough to hold the Platform
2294 token.
2295
2296 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2297 function returns the platform token length in this parameter.
2298
2299 arg2 - A pointer to the buffer where the challenge object is stored.
2300
2301 arg3 - The length of the challenge object in bytes. Possible values are 32,
2302 48 and 64.
2303
2304The function returns 0 on success, -EINVAL on failure.
2305
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002306Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
2307~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewf05d93a2022-03-22 16:21:19 +00002308
2309::
2310
2311 Argument : uintptr_t, size_t *, unsigned int
2312 Return : int
2313
2314This function returns the delegated realm attestation key which will be used to
2315sign Realm attestation token. The API currently only supports P-384 ECC curve
2316key.
2317
2318The parameters of the function are:
2319
2320 arg0 - A pointer to the buffer where the attestation key should be copied
2321 by this function. The buffer must be big enough to hold the
2322 attestation key.
2323
2324 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2325 function returns the attestation key length in this parameter.
2326
2327 arg2 - The type of the elliptic curve to which the requested attestation key
2328 belongs.
2329
2330The function returns 0 on success, -EINVAL on failure.
2331
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002332Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1]
2333~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2334
2335::
2336
2337 Argument : uintptr_t *
2338 Return : size_t
2339
2340This function returns the size of the shared area between EL3 and RMM (or 0 on
2341failure). A pointer to the shared area (or a NULL pointer on failure) is stored
2342in the pointer passed as argument.
2343
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +01002344Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1]
2345~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2346
2347::
2348
2349 Arguments : rmm_manifest_t *manifest
2350 Return : int
2351
2352When ENABLE_RME is enabled, this function populates a boot manifest for the
2353RMM image and stores it in the area specified by manifest.
2354
2355When ENABLE_RME is disabled, this function is not used.
2356
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002357Function : bl31_plat_enable_mmu [optional]
2358~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2359
2360::
2361
2362 Argument : uint32_t
2363 Return : void
2364
2365This function enables the MMU. The boot code calls this function with MMU and
2366caches disabled. This function should program necessary registers to enable
2367translation, and upon return, the MMU on the calling PE must be enabled.
2368
2369The function must honor flags passed in the first argument. These flags are
2370defined by the translation library, and can be found in the file
2371``include/lib/xlat_tables/xlat_mmu_helpers.h``.
2372
2373On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002374is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002375
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002376Function : plat_init_apkey [optional]
2377~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002378
2379::
2380
2381 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002382 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002383
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002384This function returns the 128-bit value which can be used to program ARMv8.3
2385pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002386
2387The value should be obtained from a reliable source of randomness.
2388
2389This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002390Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002391
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002392Function : plat_get_syscnt_freq2() [mandatory]
2393~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002394
2395::
2396
2397 Argument : void
2398 Return : unsigned int
2399
2400This function is used by the architecture setup code to retrieve the counter
2401frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00002402``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002403of the system counter, which is retrieved from the first entry in the frequency
2404modes table.
2405
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002406#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
2407~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002408
2409When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
2410bytes) aligned to the cache line boundary that should be allocated per-cpu to
2411accommodate all the bakery locks.
2412
2413If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
2414calculates the size of the ``bakery_lock`` input section, aligns it to the
2415nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
2416and stores the result in a linker symbol. This constant prevents a platform
2417from relying on the linker and provide a more efficient mechanism for
2418accessing per-cpu bakery lock information.
2419
2420If this constant is defined and its value is not equal to the value
2421calculated by the linker then a link time assertion is raised. A compile time
2422assertion is raised if the value of the constant is not aligned to the cache
2423line boundary.
2424
Paul Beesleyf8640672019-04-12 14:19:42 +01002425.. _porting_guide_sdei_requirements:
2426
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002427SDEI porting requirements
2428~~~~~~~~~~~~~~~~~~~~~~~~~
2429
Paul Beesley606d8072019-03-13 13:58:02 +00002430The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002431and functions, of which some are optional, and some others mandatory.
2432
2433Macros
2434......
2435
2436Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
2437^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2438
2439This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002440Normal |SDEI| events on the platform. This must have a higher value
2441(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002442
2443Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
2444^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2445
2446This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002447Critical |SDEI| events on the platform. This must have a lower value
2448(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002449
Paul Beesley606d8072019-03-13 13:58:02 +00002450**Note**: |SDEI| exception priorities must be the lowest among Secure
2451priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2452be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002453
2454Functions
2455.........
2456
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002457Function: int plat_sdei_validate_entry_point() [optional]
2458^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002459
2460::
2461
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002462 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002463 Return: int
2464
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002465This function validates the entry point address of the event handler provided by
2466the client for both event registration and *Complete and Resume* |SDEI| calls.
2467The function ensures that the address is valid in the client translation regime.
2468
2469The second argument is the exception level that the client is executing in. It
2470can be Non-Secure EL1 or Non-Secure EL2.
2471
2472The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002473
Dan Handley610e7e12018-03-01 18:44:00 +00002474The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002475translates the entry point address within the client translation regime and
2476further ensures that the resulting physical address is located in Non-secure
2477DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002478
2479Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
2480^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2481
2482::
2483
2484 Argument: uint64_t
2485 Argument: unsigned int
2486 Return: void
2487
Paul Beesley606d8072019-03-13 13:58:02 +00002488|SDEI| specification requires that a PE comes out of reset with the events
2489masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2490|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2491time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002492
Paul Beesley606d8072019-03-13 13:58:02 +00002493Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002494events are masked on the PE, the dispatcher implementation invokes the function
2495``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2496interrupt and the interrupt ID are passed as parameters.
2497
2498The default implementation only prints out a warning message.
2499
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002500.. _porting_guide_trng_requirements:
2501
2502TRNG porting requirements
2503~~~~~~~~~~~~~~~~~~~~~~~~~
2504
2505The |TRNG| backend requires the platform to provide the following values
2506and mandatory functions.
2507
2508Values
2509......
2510
2511value: uuid_t plat_trng_uuid [mandatory]
2512^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2513
2514This value must be defined to the UUID of the TRNG backend that is specific to
Jayanth Dodderi Chidanand7c7faff2022-10-11 17:16:07 +01002515the hardware after ``plat_entropy_setup`` function is called. This value must
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002516conform to the SMCCC calling convention; The most significant 32 bits of the
2517UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
2518w0 indicates failure to get a TRNG source.
2519
2520Functions
2521.........
2522
2523Function: void plat_entropy_setup(void) [mandatory]
2524^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2525
2526::
2527
2528 Argument: none
2529 Return: none
2530
2531This function is expected to do platform-specific initialization of any TRNG
2532hardware. This may include generating a UUID from a hardware-specific seed.
2533
2534Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
2535^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2536
2537::
2538
2539 Argument: uint64_t *
2540 Return: bool
2541 Out : when the return value is true, the entropy has been written into the
2542 storage pointed to
2543
2544This function writes entropy into storage provided by the caller. If no entropy
2545is available, it must return false and the storage must not be written.
2546
Boyan Karatotev907d38b2022-11-22 12:01:09 +00002547.. _psci_in_bl31:
2548
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002549Power State Coordination Interface (in BL31)
2550--------------------------------------------
2551
Dan Handley610e7e12018-03-01 18:44:00 +00002552The TF-A implementation of the PSCI API is based around the concept of a
2553*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2554share some state on which power management operations can be performed as
2555specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2556a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2557*power domains* are arranged in a hierarchical tree structure and each
2558*power domain* can be identified in a system by the cpu index of any CPU that
2559is part of that domain and a *power domain level*. A processing element (for
2560example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2561logical grouping of CPUs that share some state, then level 1 is that group of
2562CPUs (for example, a cluster), and level 2 is a group of clusters (for
2563example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002564organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002565
2566BL31's platform initialization code exports a pointer to the platform-specific
2567power management operations required for the PSCI implementation to function
2568correctly. This information is populated in the ``plat_psci_ops`` structure. The
2569PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2570power management operations on the power domains. For example, the target
2571CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2572handler (if present) is called for the CPU power domain.
2573
2574The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2575describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002576defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002577array of local power states where each index corresponds to a power domain
2578level. Each entry contains the local power state the power domain at that power
2579level could enter. It depends on the ``validate_power_state()`` handler to
2580convert the power-state parameter (possibly encoding a composite power state)
2581passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2582
2583The following functions form part of platform port of PSCI functionality.
2584
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002585Function : plat_psci_stat_accounting_start() [optional]
2586~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002587
2588::
2589
2590 Argument : const psci_power_state_t *
2591 Return : void
2592
2593This is an optional hook that platforms can implement for residency statistics
2594accounting before entering a low power state. The ``pwr_domain_state`` field of
2595``state_info`` (first argument) can be inspected if stat accounting is done
2596differently at CPU level versus higher levels. As an example, if the element at
2597index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2598state, special hardware logic may be programmed in order to keep track of the
2599residency statistics. For higher levels (array indices > 0), the residency
2600statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2601default implementation will use PMF to capture timestamps.
2602
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002603Function : plat_psci_stat_accounting_stop() [optional]
2604~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002605
2606::
2607
2608 Argument : const psci_power_state_t *
2609 Return : void
2610
2611This is an optional hook that platforms can implement for residency statistics
2612accounting after exiting from a low power state. The ``pwr_domain_state`` field
2613of ``state_info`` (first argument) can be inspected if stat accounting is done
2614differently at CPU level versus higher levels. As an example, if the element at
2615index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2616state, special hardware logic may be programmed in order to keep track of the
2617residency statistics. For higher levels (array indices > 0), the residency
2618statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2619default implementation will use PMF to capture timestamps.
2620
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002621Function : plat_psci_stat_get_residency() [optional]
2622~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002623
2624::
2625
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002626 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002627 Return : u_register_t
2628
2629This is an optional interface that is is invoked after resuming from a low power
2630state and provides the time spent resident in that low power state by the power
2631domain at a particular power domain level. When a CPU wakes up from suspend,
2632all its parent power domain levels are also woken up. The generic PSCI code
2633invokes this function for each parent power domain that is resumed and it
2634identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2635argument) describes the low power state that the power domain has resumed from.
2636The current CPU is the first CPU in the power domain to resume from the low
2637power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2638CPU in the power domain to suspend and may be needed to calculate the residency
2639for that power domain.
2640
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002641Function : plat_get_target_pwr_state() [optional]
2642~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002643
2644::
2645
2646 Argument : unsigned int, const plat_local_state_t *, unsigned int
2647 Return : plat_local_state_t
2648
2649The PSCI generic code uses this function to let the platform participate in
2650state coordination during a power management operation. The function is passed
2651a pointer to an array of platform specific local power state ``states`` (second
2652argument) which contains the requested power state for each CPU at a particular
2653power domain level ``lvl`` (first argument) within the power domain. The function
2654is expected to traverse this array of upto ``ncpus`` (third argument) and return
2655a coordinated target power state by the comparing all the requested power
2656states. The target power state should not be deeper than any of the requested
2657power states.
2658
2659A weak definition of this API is provided by default wherein it assumes
2660that the platform assigns a local state value in order of increasing depth
2661of the power state i.e. for two power states X & Y, if X < Y
2662then X represents a shallower power state than Y. As a result, the
2663coordinated target local power state for a power domain will be the minimum
2664of the requested local power state values.
2665
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002666Function : plat_get_power_domain_tree_desc() [mandatory]
2667~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002668
2669::
2670
2671 Argument : void
2672 Return : const unsigned char *
2673
2674This function returns a pointer to the byte array containing the power domain
2675topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002676described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2677initialization code requires this array to be described by the platform, either
2678statically or dynamically, to initialize the power domain topology tree. In case
2679the array is populated dynamically, then plat_core_pos_by_mpidr() and
2680plat_my_core_pos() should also be implemented suitably so that the topology tree
2681description matches the CPU indices returned by these APIs. These APIs together
2682form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002683
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002684Function : plat_setup_psci_ops() [mandatory]
2685~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002686
2687::
2688
2689 Argument : uintptr_t, const plat_psci_ops **
2690 Return : int
2691
2692This function may execute with the MMU and data caches enabled if the platform
2693port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2694called by the primary CPU.
2695
2696This function is called by PSCI initialization code. Its purpose is to let
2697the platform layer know about the warm boot entrypoint through the
2698``sec_entrypoint`` (first argument) and to export handler routines for
2699platform-specific psci power management actions by populating the passed
2700pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2701
2702A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002703the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002704``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002705platform wants to support, the associated operation or operations in this
2706structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002707:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002708function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002709structure instead of providing an empty implementation.
2710
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002711plat_psci_ops.cpu_standby()
2712...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002713
2714Perform the platform-specific actions to enter the standby state for a cpu
2715indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002716wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002717For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2718the suspend state type specified in the ``power-state`` parameter should be
2719STANDBY and the target power domain level specified should be the CPU. The
2720handler should put the CPU into a low power retention state (usually by
2721issuing a wfi instruction) and ensure that it can be woken up from that
2722state by a normal interrupt. The generic code expects the handler to succeed.
2723
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002724plat_psci_ops.pwr_domain_on()
2725.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002726
2727Perform the platform specific actions to power on a CPU, specified
2728by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002729return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002730
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002731plat_psci_ops.pwr_domain_off()
2732..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002733
2734Perform the platform specific actions to prepare to power off the calling CPU
2735and its higher parent power domain levels as indicated by the ``target_state``
2736(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2737
2738The ``target_state`` encodes the platform coordinated target local power states
2739for the CPU power domain and its parent power domain levels. The handler
2740needs to perform power management operation corresponding to the local state
2741at each power level.
2742
2743For this handler, the local power state for the CPU power domain will be a
2744power down state where as it could be either power down, retention or run state
2745for the higher power domain levels depending on the result of state
2746coordination. The generic code expects the handler to succeed.
2747
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002748plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2749...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002750
2751This optional function may be used as a performance optimization to replace
2752or complement pwr_domain_suspend() on some platforms. Its calling semantics
2753are identical to pwr_domain_suspend(), except the PSCI implementation only
2754calls this function when suspending to a power down state, and it guarantees
2755that data caches are enabled.
2756
2757When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2758before calling pwr_domain_suspend(). If the target_state corresponds to a
2759power down state and it is safe to perform some or all of the platform
2760specific actions in that function with data caches enabled, it may be more
2761efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2762= 1, data caches remain enabled throughout, and so there is no advantage to
2763moving platform specific actions to this function.
2764
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002765plat_psci_ops.pwr_domain_suspend()
2766..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002767
2768Perform the platform specific actions to prepare to suspend the calling
2769CPU and its higher parent power domain levels as indicated by the
2770``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2771API implementation.
2772
2773The ``target_state`` has a similar meaning as described in
2774the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2775target local power states for the CPU power domain and its parent
2776power domain levels. The handler needs to perform power management operation
2777corresponding to the local state at each power level. The generic code
2778expects the handler to succeed.
2779
Douglas Raillarda84996b2017-08-02 16:57:32 +01002780The difference between turning a power domain off versus suspending it is that
2781in the former case, the power domain is expected to re-initialize its state
2782when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2783case, the power domain is expected to save enough state so that it can resume
2784execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002785``pwr_domain_suspend_finish()``).
2786
Douglas Raillarda84996b2017-08-02 16:57:32 +01002787When suspending a core, the platform can also choose to power off the GICv3
2788Redistributor and ITS through an implementation-defined sequence. To achieve
2789this safely, the ITS context must be saved first. The architectural part is
2790implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2791sequence is implementation defined and it is therefore the responsibility of
2792the platform code to implement the necessary sequence. Then the GIC
2793Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2794Powering off the Redistributor requires the implementation to support it and it
2795is the responsibility of the platform code to execute the right implementation
2796defined sequence.
2797
2798When a system suspend is requested, the platform can also make use of the
2799``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2800it has saved the context of the Redistributors and ITS of all the cores in the
2801system. The context of the Distributor can be large and may require it to be
2802allocated in a special area if it cannot fit in the platform's global static
2803data, for example in DRAM. The Distributor can then be powered down using an
2804implementation-defined sequence.
2805
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002806plat_psci_ops.pwr_domain_pwr_down_wfi()
2807.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002808
2809This is an optional function and, if implemented, is expected to perform
2810platform specific actions including the ``wfi`` invocation which allows the
2811CPU to powerdown. Since this function is invoked outside the PSCI locks,
2812the actions performed in this hook must be local to the CPU or the platform
2813must ensure that races between multiple CPUs cannot occur.
2814
2815The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2816operation and it encodes the platform coordinated target local power states for
2817the CPU power domain and its parent power domain levels. This function must
Boyan Karatotev43771f32022-10-05 13:41:56 +01002818not return back to the caller (by calling wfi in an infinite loop to ensure
2819some CPUs power down mitigations work properly).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002820
2821If this function is not implemented by the platform, PSCI generic
2822implementation invokes ``psci_power_down_wfi()`` for power down.
2823
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002824plat_psci_ops.pwr_domain_on_finish()
2825....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002826
2827This function is called by the PSCI implementation after the calling CPU is
2828powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2829It performs the platform-specific setup required to initialize enough state for
2830this CPU to enter the normal world and also provide secure runtime firmware
2831services.
2832
2833The ``target_state`` (first argument) is the prior state of the power domains
2834immediately before the CPU was turned on. It indicates which power domains
2835above the CPU might require initialization due to having previously been in
2836low power states. The generic code expects the handler to succeed.
2837
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002838plat_psci_ops.pwr_domain_on_finish_late() [optional]
2839...........................................................
2840
2841This optional function is called by the PSCI implementation after the calling
2842CPU is fully powered on with respective data caches enabled. The calling CPU and
2843the associated cluster are guaranteed to be participating in coherency. This
2844function gives the flexibility to perform any platform-specific actions safely,
2845such as initialization or modification of shared data structures, without the
2846overhead of explicit cache maintainace operations.
2847
2848The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2849operation. The generic code expects the handler to succeed.
2850
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002851plat_psci_ops.pwr_domain_suspend_finish()
2852.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002853
2854This function is called by the PSCI implementation after the calling CPU is
2855powered on and released from reset in response to an asynchronous wakeup
2856event, for example a timer interrupt that was programmed by the CPU during the
2857``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2858setup required to restore the saved state for this CPU to resume execution
2859in the normal world and also provide secure runtime firmware services.
2860
2861The ``target_state`` (first argument) has a similar meaning as described in
2862the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2863to succeed.
2864
Douglas Raillarda84996b2017-08-02 16:57:32 +01002865If the Distributor, Redistributors or ITS have been powered off as part of a
2866suspend, their context must be restored in this function in the reverse order
2867to how they were saved during suspend sequence.
2868
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002869plat_psci_ops.system_off()
2870..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002871
2872This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2873call. It performs the platform-specific system poweroff sequence after
2874notifying the Secure Payload Dispatcher.
2875
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002876plat_psci_ops.system_reset()
2877............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002878
2879This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2880call. It performs the platform-specific system reset sequence after
2881notifying the Secure Payload Dispatcher.
2882
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002883plat_psci_ops.validate_power_state()
2884....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002885
2886This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2887call to validate the ``power_state`` parameter of the PSCI API and if valid,
2888populate it in ``req_state`` (second argument) array as power domain level
2889specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002890return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002891normal world PSCI client.
2892
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002893plat_psci_ops.validate_ns_entrypoint()
2894......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002895
2896This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2897``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2898parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002899the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002900propagated back to the normal world PSCI client.
2901
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002902plat_psci_ops.get_sys_suspend_power_state()
2903...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002904
2905This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2906call to get the ``req_state`` parameter from platform which encodes the power
2907domain level specific local states to suspend to system affinity level. The
2908``req_state`` will be utilized to do the PSCI state coordination and
2909``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2910enter system suspend.
2911
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002912plat_psci_ops.get_pwr_lvl_state_idx()
2913.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002914
2915This is an optional function and, if implemented, is invoked by the PSCI
2916implementation to convert the ``local_state`` (first argument) at a specified
2917``pwr_lvl`` (second argument) to an index between 0 and
2918``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2919supports more than two local power states at each power domain level, that is
2920``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2921local power states.
2922
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002923plat_psci_ops.translate_power_state_by_mpidr()
2924..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002925
2926This is an optional function and, if implemented, verifies the ``power_state``
2927(second argument) parameter of the PSCI API corresponding to a target power
2928domain. The target power domain is identified by using both ``MPIDR`` (first
2929argument) and the power domain level encoded in ``power_state``. The power domain
2930level specific local states are to be extracted from ``power_state`` and be
2931populated in the ``output_state`` (third argument) array. The functionality
2932is similar to the ``validate_power_state`` function described above and is
2933envisaged to be used in case the validity of ``power_state`` depend on the
2934targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002935domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002936function is not implemented, then the generic implementation relies on
2937``validate_power_state`` function to translate the ``power_state``.
2938
2939This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002940power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002941APIs as described in Section 5.18 of `PSCI`_.
2942
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002943plat_psci_ops.get_node_hw_state()
2944.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002945
2946This is an optional function. If implemented this function is intended to return
2947the power state of a node (identified by the first parameter, the ``MPIDR``) in
2948the power domain topology (identified by the second parameter, ``power_level``),
2949as retrieved from a power controller or equivalent component on the platform.
2950Upon successful completion, the implementation must map and return the final
2951status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2952must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2953appropriate.
2954
2955Implementations are not expected to handle ``power_levels`` greater than
2956``PLAT_MAX_PWR_LVL``.
2957
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002958plat_psci_ops.system_reset2()
2959.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002960
2961This is an optional function. If implemented this function is
2962called during the ``SYSTEM_RESET2`` call to perform a reset
2963based on the first parameter ``reset_type`` as specified in
2964`PSCI`_. The parameter ``cookie`` can be used to pass additional
2965reset information. If the ``reset_type`` is not supported, the
2966function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2967resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2968and vendor reset can return other PSCI error codes as defined
2969in `PSCI`_. On success this function will not return.
2970
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002971plat_psci_ops.write_mem_protect()
2972.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002973
2974This is an optional function. If implemented it enables or disables the
2975``MEM_PROTECT`` functionality based on the value of ``val``.
2976A non-zero value enables ``MEM_PROTECT`` and a value of zero
2977disables it. Upon encountering failures it must return a negative value
2978and on success it must return 0.
2979
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002980plat_psci_ops.read_mem_protect()
2981................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002982
2983This is an optional function. If implemented it returns the current
2984state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2985failures it must return a negative value and on success it must
2986return 0.
2987
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002988plat_psci_ops.mem_protect_chk()
2989...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002990
2991This is an optional function. If implemented it checks if a memory
2992region defined by a base address ``base`` and with a size of ``length``
2993bytes is protected by ``MEM_PROTECT``. If the region is protected
2994then it must return 0, otherwise it must return a negative number.
2995
Paul Beesleyf8640672019-04-12 14:19:42 +01002996.. _porting_guide_imf_in_bl31:
2997
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002998Interrupt Management framework (in BL31)
2999----------------------------------------
3000
3001BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
3002generated in either security state and targeted to EL1 or EL2 in the non-secure
3003state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01003004described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003005
3006A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00003007text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003008platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00003009present in the platform. Arm standard platform layer supports both
3010`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
3011and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
3012FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003013``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
3014details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003015
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05003016See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`.
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01003017
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003018Function : plat_interrupt_type_to_line() [mandatory]
3019~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003020
3021::
3022
3023 Argument : uint32_t, uint32_t
3024 Return : uint32_t
3025
Dan Handley610e7e12018-03-01 18:44:00 +00003026The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003027interrupt line. The specific line that is signaled depends on how the interrupt
3028controller (IC) reports different interrupt types from an execution context in
3029either security state. The IMF uses this API to determine which interrupt line
3030the platform IC uses to signal each type of interrupt supported by the framework
3031from a given security state. This API must be invoked at EL3.
3032
3033The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01003034:ref:`Interrupt Management Framework`) indicating the target type of the
3035interrupt, the second parameter is the security state of the originating
3036execution context. The return result is the bit position in the ``SCR_EL3``
3037register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003038
Dan Handley610e7e12018-03-01 18:44:00 +00003039In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003040configured as FIQs and Non-secure interrupts as IRQs from either security
3041state.
3042
Dan Handley610e7e12018-03-01 18:44:00 +00003043In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003044configured depends on the security state of the execution context when the
3045interrupt is signalled and are as follows:
3046
3047- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
3048 NS-EL0/1/2 context.
3049- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
3050 in the NS-EL0/1/2 context.
3051- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
3052 context.
3053
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003054Function : plat_ic_get_pending_interrupt_type() [mandatory]
3055~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003056
3057::
3058
3059 Argument : void
3060 Return : uint32_t
3061
3062This API returns the type of the highest priority pending interrupt at the
3063platform IC. The IMF uses the interrupt type to retrieve the corresponding
3064handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
3065pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
3066``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
3067
Dan Handley610e7e12018-03-01 18:44:00 +00003068In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003069Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
3070the pending interrupt. The type of interrupt depends upon the id value as
3071follows.
3072
3073#. id < 1022 is reported as a S-EL1 interrupt
3074#. id = 1022 is reported as a Non-secure interrupt.
3075#. id = 1023 is reported as an invalid interrupt type.
3076
Dan Handley610e7e12018-03-01 18:44:00 +00003077In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003078``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
3079is read to determine the id of the pending interrupt. The type of interrupt
3080depends upon the id value as follows.
3081
3082#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
3083#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
3084#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
3085#. All other interrupt id's are reported as EL3 interrupt.
3086
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003087Function : plat_ic_get_pending_interrupt_id() [mandatory]
3088~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003089
3090::
3091
3092 Argument : void
3093 Return : uint32_t
3094
3095This API returns the id of the highest priority pending interrupt at the
3096platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
3097pending.
3098
Dan Handley610e7e12018-03-01 18:44:00 +00003099In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003100Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
3101pending interrupt. The id that is returned by API depends upon the value of
3102the id read from the interrupt controller as follows.
3103
3104#. id < 1022. id is returned as is.
3105#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
3106 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
3107 This id is returned by the API.
3108#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
3109
Dan Handley610e7e12018-03-01 18:44:00 +00003110In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003111EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
3112group 0 Register*, is read to determine the id of the pending interrupt. The id
3113that is returned by API depends upon the value of the id read from the
3114interrupt controller as follows.
3115
3116#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
3117#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
3118 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
3119 Register* is read to determine the id of the group 1 interrupt. This id
3120 is returned by the API as long as it is a valid interrupt id
3121#. If the id is any of the special interrupt identifiers,
3122 ``INTR_ID_UNAVAILABLE`` is returned.
3123
3124When the API invoked from S-EL1 for GICv3 systems, the id read from system
3125register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003126Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003127``INTR_ID_UNAVAILABLE`` is returned.
3128
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003129Function : plat_ic_acknowledge_interrupt() [mandatory]
3130~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003131
3132::
3133
3134 Argument : void
3135 Return : uint32_t
3136
3137This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003138the highest pending interrupt has begun. It should return the raw, unmodified
3139value obtained from the interrupt controller when acknowledging an interrupt.
3140The actual interrupt number shall be extracted from this raw value using the API
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05003141`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003142
Dan Handley610e7e12018-03-01 18:44:00 +00003143This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003144Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
3145priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003146It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003147
Dan Handley610e7e12018-03-01 18:44:00 +00003148In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003149from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
3150Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
3151reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
3152group 1*. The read changes the state of the highest pending interrupt from
3153pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01003154unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003155
3156The TSP uses this API to start processing of the secure physical timer
3157interrupt.
3158
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003159Function : plat_ic_end_of_interrupt() [mandatory]
3160~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003161
3162::
3163
3164 Argument : uint32_t
3165 Return : void
3166
3167This API is used by the CPU to indicate to the platform IC that processing of
3168the interrupt corresponding to the id (passed as the parameter) has
3169finished. The id should be the same as the id returned by the
3170``plat_ic_acknowledge_interrupt()`` API.
3171
Dan Handley610e7e12018-03-01 18:44:00 +00003172Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003173(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
3174system register in case of GICv3 depending on where the API is invoked from,
3175EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
3176controller.
3177
3178The TSP uses this API to finish processing of the secure physical timer
3179interrupt.
3180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003181Function : plat_ic_get_interrupt_type() [mandatory]
3182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003183
3184::
3185
3186 Argument : uint32_t
3187 Return : uint32_t
3188
3189This API returns the type of the interrupt id passed as the parameter.
3190``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
3191interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
3192returned depending upon how the interrupt has been configured by the platform
3193IC. This API must be invoked at EL3.
3194
Dan Handley610e7e12018-03-01 18:44:00 +00003195Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003196and Non-secure interrupts as Group1 interrupts. It reads the group value
3197corresponding to the interrupt id from the relevant *Interrupt Group Register*
3198(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
3199
Dan Handley610e7e12018-03-01 18:44:00 +00003200In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003201Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
3202(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
3203as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
3204
Manish Pandey3161fa52022-11-02 16:30:09 +00003205Common helper functions
3206-----------------------
3207
3208Function : do_panic()
3209~~~~~~~~~~~~~~~~~~~~~
3210
3211::
3212
3213 Argument : void
3214 Return : void
3215
3216This API is called from assembly files when encountering a critical failure that
3217cannot be recovered from. It also invokes elx_panic() which allows to report a
3218crash from lower exception level. This function assumes that it is invoked from
3219a C runtime environment i.e. valid stack exists. This call **must not** return.
3220
3221Function : panic()
3222~~~~~~~~~~~~~~~~~~
3223
3224::
3225
3226 Argument : void
3227 Return : void
3228
3229This API called from C files when encountering a critical failure that cannot
3230be recovered from. This function in turn prints backtrace (if enabled) and calls
3231do_panic(). This call **must not** return.
3232
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003233Crash Reporting mechanism (in BL31)
3234-----------------------------------
3235
3236BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003237of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00003238on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003239``plat_crash_console_putc`` and ``plat_crash_console_flush``.
3240
3241The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
3242implementation of all of them. Platforms may include this file to their
3243makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003244output to be routed over the normal console infrastructure and get printed on
3245consoles configured to output in crash state. ``console_set_scope()`` can be
3246used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00003247
3248.. note::
3249 Platforms are responsible for making sure that they only mark consoles for
3250 use in the crash scope that are able to support this, i.e. that are written
3251 in assembly and conform with the register clobber rules for putc()
3252 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003253
Julius Werneraae9bb12017-09-18 16:49:48 -07003254In some cases (such as debugging very early crashes that happen before the
3255normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08003256more explicitly. These platforms may instead provide custom implementations for
3257these. They are executed outside of a C environment and without a stack. Many
3258console drivers provide functions named ``console_xxx_core_init/putc/flush``
3259that are designed to be used by these functions. See Arm platforms (like juno)
3260for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01003261
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003262Function : plat_crash_console_init [mandatory]
3263~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003264
3265::
3266
3267 Argument : void
3268 Return : int
3269
3270This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07003271console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003272initialization and returns 1 on success.
3273
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003274Function : plat_crash_console_putc [mandatory]
3275~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003276
3277::
3278
3279 Argument : int
3280 Return : int
3281
3282This API is used by the crash reporting mechanism to print a character on the
3283designated crash console. It must only use general purpose registers x1 and
3284x2 to do its work. The parameter and the return value are in general purpose
3285register x0.
3286
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003287Function : plat_crash_console_flush [mandatory]
3288~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003289
3290::
3291
3292 Argument : void
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003293 Return : void
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003294
3295This API is used by the crash reporting mechanism to force write of all buffered
3296data on the designated crash console. It should only use general purpose
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003297registers x0 through x5 to do its work.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003298
Manish Pandey9c9f38a2020-06-30 00:46:08 +01003299.. _External Abort handling and RAS Support:
3300
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01003301External Abort handling and RAS Support
3302---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003303
3304Function : plat_ea_handler
3305~~~~~~~~~~~~~~~~~~~~~~~~~~
3306
3307::
3308
3309 Argument : int
3310 Argument : uint64_t
3311 Argument : void *
3312 Argument : void *
3313 Argument : uint64_t
3314 Return : void
3315
3316This function is invoked by the RAS framework for the platform to handle an
3317External Abort received at EL3. The intention of the function is to attempt to
3318resolve the cause of External Abort and return; if that's not possible, to
3319initiate orderly shutdown of the system.
3320
3321The first parameter (``int ea_reason``) indicates the reason for External Abort.
3322Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
3323
3324The second parameter (``uint64_t syndrome``) is the respective syndrome
3325presented to EL3 after having received the External Abort. Depending on the
3326nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
3327can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
3328
3329The third parameter (``void *cookie``) is unused for now. The fourth parameter
3330(``void *handle``) is a pointer to the preempted context. The fifth parameter
3331(``uint64_t flags``) indicates the preempted security state. These parameters
3332are received from the top-level exception handler.
3333
3334If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
3335function iterates through RAS handlers registered by the platform. If any of the
3336RAS handlers resolve the External Abort, no further action is taken.
3337
3338If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
3339could resolve the External Abort, the default implementation prints an error
3340message, and panics.
3341
3342Function : plat_handle_uncontainable_ea
3343~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3344
3345::
3346
3347 Argument : int
3348 Argument : uint64_t
3349 Return : void
3350
3351This function is invoked by the RAS framework when an External Abort of
3352Uncontainable type is received at EL3. Due to the critical nature of
3353Uncontainable errors, the intention of this function is to initiate orderly
3354shutdown of the system, and is not expected to return.
3355
3356This function must be implemented in assembly.
3357
3358The first and second parameters are the same as that of ``plat_ea_handler``.
3359
3360The default implementation of this function calls
3361``report_unhandled_exception``.
3362
3363Function : plat_handle_double_fault
3364~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3365
3366::
3367
3368 Argument : int
3369 Argument : uint64_t
3370 Return : void
3371
3372This function is invoked by the RAS framework when another External Abort is
3373received at EL3 while one is already being handled. I.e., a call to
3374``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
3375this function is to initiate orderly shutdown of the system, and is not expected
3376recover or return.
3377
3378This function must be implemented in assembly.
3379
3380The first and second parameters are the same as that of ``plat_ea_handler``.
3381
3382The default implementation of this function calls
3383``report_unhandled_exception``.
3384
3385Function : plat_handle_el3_ea
3386~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3387
3388::
3389
3390 Return : void
3391
3392This function is invoked when an External Abort is received while executing in
3393EL3. Due to its critical nature, the intention of this function is to initiate
3394orderly shutdown of the system, and is not expected recover or return.
3395
3396This function must be implemented in assembly.
3397
3398The default implementation of this function calls
3399``report_unhandled_exception``.
3400
Andre Przywarabdc76f12022-11-21 17:07:25 +00003401Function : plat_handle_rng_trap
3402~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3403
3404::
3405
3406 Argument : uint64_t
3407 Argument : cpu_context_t *
3408 Return : int
3409
3410This function is invoked by BL31's exception handler when there is a synchronous
3411system register trap caused by access to the RNDR or RNDRRS registers. It allows
3412platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to
3413emulate those system registers by returing back some entropy to the lower EL.
3414
3415The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3
3416syndrome register, which encodes the instruction that was trapped. The interesting
3417information in there is the target register (``get_sysreg_iss_rt()``).
3418
3419The second parameter (``cpu_context_t *ctx``) represents the CPU state in the
3420lower exception level, at the time when the execution of the ``mrs`` instruction
3421was trapped. Its content can be changed, to put the entropy into the target
3422register.
3423
3424The return value indicates how to proceed:
3425
3426- When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic.
3427- When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return
3428 to the same instruction, so its execution will be repeated.
3429- When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return
3430 to the next instruction.
3431
3432This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP.
3433
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003434Build flags
3435-----------
3436
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003437There are some build flags which can be defined by the platform to control
3438inclusion or exclusion of certain BL stages from the FIP image. These flags
3439need to be defined in the platform makefile which will get included by the
3440build system.
3441
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003442- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003443 By default, this flag is defined ``yes`` by the build system and ``BL33``
3444 build option should be supplied as a build option. The platform has the
3445 option of excluding the BL33 image in the ``fip`` image by defining this flag
3446 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
3447 are used, this flag will be set to ``no`` automatically.
3448
Paul Beesley07f0a312019-05-16 13:33:18 +01003449Platform include paths
3450----------------------
3451
3452Platforms are allowed to add more include paths to be passed to the compiler.
3453The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
3454particular for the file ``platform_def.h``.
3455
3456Example:
3457
3458.. code:: c
3459
3460 PLAT_INCLUDES += -Iinclude/plat/myplat/include
3461
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003462C Library
3463---------
3464
3465To avoid subtle toolchain behavioral dependencies, the header files provided
3466by the compiler are not used. The software is built with the ``-nostdinc`` flag
3467to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00003468required headers are included in the TF-A source tree. The library only
3469contains those C library definitions required by the local implementation. If
3470more functionality is required, the needed library functions will need to be
3471added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003472
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003473Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00003474been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003475from `FreeBSD`_, others have been written specifically for TF-A as well. The
3476files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003477
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01003478SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
3479can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003480
3481Storage abstraction layer
3482-------------------------
3483
Louis Mayencourtb5469002019-07-15 13:56:03 +01003484In order to improve platform independence and portability a storage abstraction
3485layer is used to load data from non-volatile platform storage. Currently
3486storage access is only required by BL1 and BL2 phases and performed inside the
3487``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003488
Louis Mayencourtb5469002019-07-15 13:56:03 +01003489.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003490
Dan Handley610e7e12018-03-01 18:44:00 +00003491It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003492development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003493the default means to load data from storage (see :ref:`firmware_design_fip`).
3494The storage layer is described in the header file
3495``include/drivers/io/io_storage.h``. The implementation of the common library is
3496in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003497``drivers/io/``.
3498
Louis Mayencourtb5469002019-07-15 13:56:03 +01003499.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
3500
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003501Each IO driver must provide ``io_dev_*`` structures, as described in
3502``drivers/io/io_driver.h``. These are returned via a mandatory registration
3503function that is called on platform initialization. The semi-hosting driver
3504implementation in ``io_semihosting.c`` can be used as an example.
3505
Louis Mayencourtb5469002019-07-15 13:56:03 +01003506Each platform should register devices and their drivers via the storage
3507abstraction layer. These drivers then need to be initialized by bootloader
3508phases as required in their respective ``blx_platform_setup()`` functions.
3509
3510.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
3511
3512The storage abstraction layer provides mechanisms (``io_dev_init()``) to
3513initialize storage devices before IO operations are called.
3514
3515.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
3516
3517The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003518include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
3519Drivers do not have to implement all operations, but each platform must
3520provide at least one driver for a device capable of supporting generic
3521operations such as loading a bootloader image.
3522
3523The current implementation only allows for known images to be loaded by the
3524firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00003525``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003526there). The platform layer (``plat_get_image_source()``) then returns a reference
3527to a device and a driver-specific ``spec`` which will be understood by the driver
3528to allow access to the image data.
3529
3530The layer is designed in such a way that is it possible to chain drivers with
3531other drivers. For example, file-system drivers may be implemented on top of
3532physical block devices, both represented by IO devices with corresponding
3533drivers. In such a case, the file-system "binding" with the block device may
3534be deferred until the file-system device is initialised.
3535
3536The abstraction currently depends on structures being statically allocated
3537by the drivers and callers, as the system does not yet provide a means of
3538dynamically allocating memory. This may also have the affect of limiting the
3539amount of open resources per driver.
3540
3541--------------
3542
Soby Mathewf05d93a2022-03-22 16:21:19 +00003543*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003544
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003545.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00003546.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003547.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00003548.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003549.. _SCC: http://www.simple-cc.org/
Lucian Paul-Trifub93037a2022-06-22 18:45:36 +01003550.. _DRTM: https://developer.arm.com/documentation/den0113/a