Paul Beesley | fc9ee36 | 2019-03-07 15:47:15 +0000 | [diff] [blame] | 1 | Porting Guide |
| 2 | ============= |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 4 | Introduction |
| 5 | ------------ |
| 6 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 7 | Porting Trusted Firmware-A (TF-A) to a new platform involves making some |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 8 | mandatory and optional modifications for both the cold and warm boot paths. |
| 9 | Modifications consist of: |
| 10 | |
| 11 | - Implementing a platform-specific function or variable, |
| 12 | - Setting up the execution context in a certain way, or |
| 13 | - Defining certain constants (for example #defines). |
| 14 | |
| 15 | The platform-specific functions and variables are declared in |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 16 | ``include/plat/common/platform.h``. The firmware provides a default |
| 17 | implementation of variables and functions to fulfill the optional requirements. |
| 18 | These implementations are all weakly defined; they are provided to ease the |
| 19 | porting effort. Each platform port can override them with its own implementation |
| 20 | if the default implementation is inadequate. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 21 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 22 | Some modifications are common to all Boot Loader (BL) stages. Section 2 |
| 23 | discusses these in detail. The subsequent sections discuss the remaining |
| 24 | modifications for each BL stage in detail. |
| 25 | |
Sandrine Bailleux | dad3561 | 2022-11-08 13:36:42 +0100 | [diff] [blame] | 26 | Please refer to the :ref:`Platform Ports Policy` for the policy regarding |
| 27 | compatibility and deprecation of these porting interfaces. |
Soby Mathew | 02bdbb9 | 2018-09-26 11:17:23 +0100 | [diff] [blame] | 28 | |
Antonio Nino Diaz | 645feb4 | 2019-02-13 14:07:38 +0000 | [diff] [blame] | 29 | Only Arm development platforms (such as FVP and Juno) may use the |
| 30 | functions/definitions in ``include/plat/arm/common/`` and the corresponding |
| 31 | source files in ``plat/arm/common/``. This is done so that there are no |
| 32 | dependencies between platforms maintained by different people/companies. If you |
| 33 | want to use any of the functionality present in ``plat/arm`` files, please |
| 34 | create a pull request that moves the code to ``plat/common`` so that it can be |
| 35 | discussed. |
| 36 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 37 | Common modifications |
| 38 | -------------------- |
| 39 | |
| 40 | This section covers the modifications that should be made by the platform for |
| 41 | each BL stage to correctly port the firmware stack. They are categorized as |
| 42 | either mandatory or optional. |
| 43 | |
| 44 | Common mandatory modifications |
| 45 | ------------------------------ |
| 46 | |
| 47 | A platform port must enable the Memory Management Unit (MMU) as well as the |
| 48 | instruction and data caches for each BL stage. Setting up the translation |
| 49 | tables is the responsibility of the platform port because memory maps differ |
| 50 | across platforms. A memory translation library (see ``lib/xlat_tables/``) is |
Sandrine Bailleux | 1861b7a | 2017-07-20 16:11:01 +0100 | [diff] [blame] | 51 | provided to help in this setup. |
| 52 | |
| 53 | Note that although this library supports non-identity mappings, this is intended |
| 54 | only for re-mapping peripheral physical addresses and allows platforms with high |
| 55 | I/O addresses to reduce their virtual address space. All other addresses |
| 56 | corresponding to code and data must currently use an identity mapping. |
| 57 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 58 | Also, the only translation granule size supported in TF-A is 4KB, as various |
| 59 | parts of the code assume that is the case. It is not possible to switch to |
| 60 | 16 KB or 64 KB granule sizes at the moment. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 61 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 62 | In Arm standard platforms, each BL stage configures the MMU in the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 63 | platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses |
| 64 | an identity mapping for all addresses. |
| 65 | |
| 66 | If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a |
| 67 | block of identity mapped secure memory with Device-nGnRE attributes aligned to |
| 68 | page boundary (4K) for each BL stage. All sections which allocate coherent |
Chris Kay | 33bfc5e | 2023-02-14 11:30:04 +0000 | [diff] [blame] | 69 | memory are grouped under ``.coherent_ram``. For ex: Bakery locks are placed in a |
| 70 | section identified by name ``.bakery_lock`` inside ``.coherent_ram`` so that its |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 71 | possible for the firmware to place variables in it using the following C code |
| 72 | directive: |
| 73 | |
| 74 | :: |
| 75 | |
Chris Kay | 33bfc5e | 2023-02-14 11:30:04 +0000 | [diff] [blame] | 76 | __section(".bakery_lock") |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 77 | |
| 78 | Or alternatively the following assembler code directive: |
| 79 | |
| 80 | :: |
| 81 | |
Chris Kay | 33bfc5e | 2023-02-14 11:30:04 +0000 | [diff] [blame] | 82 | .section .bakery_lock |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 83 | |
Chris Kay | 33bfc5e | 2023-02-14 11:30:04 +0000 | [diff] [blame] | 84 | The ``.coherent_ram`` section is a sum of all sections like ``.bakery_lock`` which are |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 85 | used to allocate any data structures that are accessed both when a CPU is |
| 86 | executing with its MMU and caches enabled, and when it's running with its MMU |
| 87 | and caches disabled. Examples are given below. |
| 88 | |
| 89 | The following variables, functions and constants must be defined by the platform |
| 90 | for the firmware to work correctly. |
| 91 | |
Javier Almansa Sobrino | 37bf69c | 2022-04-07 18:26:49 +0100 | [diff] [blame] | 92 | .. _platform_def_mandatory: |
| 93 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 94 | File : platform_def.h [mandatory] |
| 95 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 96 | |
| 97 | Each platform must ensure that a header file of this name is in the system |
Antonio Nino Diaz | 50a4d1a | 2019-02-01 12:22:22 +0000 | [diff] [blame] | 98 | include path with the following constants defined. This will require updating |
| 99 | the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 100 | |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 101 | Platform ports may optionally use the file ``include/plat/common/common_def.h``, |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 102 | which provides typical values for some of the constants below. These values are |
| 103 | likely to be suitable for all platform ports. |
| 104 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 105 | - **#define : PLATFORM_LINKER_FORMAT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 106 | |
| 107 | Defines the linker format used by the platform, for example |
| 108 | ``elf64-littleaarch64``. |
| 109 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 110 | - **#define : PLATFORM_LINKER_ARCH** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 111 | |
| 112 | Defines the processor architecture for the linker by the platform, for |
| 113 | example ``aarch64``. |
| 114 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 115 | - **#define : PLATFORM_STACK_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 116 | |
| 117 | Defines the normal stack memory available to each CPU. This constant is used |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 118 | by ``plat/common/aarch64/platform_mp_stack.S`` and |
| 119 | ``plat/common/aarch64/platform_up_stack.S``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 120 | |
David Horstmann | 051fd6d | 2020-11-12 15:19:04 +0000 | [diff] [blame] | 121 | - **#define : CACHE_WRITEBACK_GRANULE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 122 | |
Max Yu | fa0b4e8 | 2022-09-08 23:21:21 +0000 | [diff] [blame] | 123 | Defines the size in bytes of the largest cache line across all the cache |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 124 | levels in the platform. |
| 125 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 126 | - **#define : FIRMWARE_WELCOME_STR** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 127 | |
| 128 | Defines the character string printed by BL1 upon entry into the ``bl1_main()`` |
| 129 | function. |
| 130 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 131 | - **#define : PLATFORM_CORE_COUNT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 132 | |
| 133 | Defines the total number of CPUs implemented by the platform across all |
| 134 | clusters in the system. |
| 135 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 136 | - **#define : PLAT_NUM_PWR_DOMAINS** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 137 | |
| 138 | Defines the total number of nodes in the power domain topology |
| 139 | tree at all the power domain levels used by the platform. |
| 140 | This macro is used by the PSCI implementation to allocate |
| 141 | data structures to represent power domain topology. |
| 142 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 143 | - **#define : PLAT_MAX_PWR_LVL** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 144 | |
| 145 | Defines the maximum power domain level that the power management operations |
| 146 | should apply to. More often, but not always, the power domain level |
| 147 | corresponds to affinity level. This macro allows the PSCI implementation |
| 148 | to know the highest power domain level that it should consider for power |
| 149 | management operations in the system that the platform implements. For |
| 150 | example, the Base AEM FVP implements two clusters with a configurable |
| 151 | number of CPUs and it reports the maximum power domain level as 1. |
| 152 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 153 | - **#define : PLAT_MAX_OFF_STATE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 154 | |
| 155 | Defines the local power state corresponding to the deepest power down |
| 156 | possible at every power domain level in the platform. The local power |
| 157 | states for each level may be sparsely allocated between 0 and this value |
| 158 | with 0 being reserved for the RUN state. The PSCI implementation uses this |
| 159 | value to initialize the local power states of the power domain nodes and |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 160 | to specify the requested power state for a PSCI_CPU_OFF call. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 161 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 162 | - **#define : PLAT_MAX_RET_STATE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 163 | |
| 164 | Defines the local power state corresponding to the deepest retention state |
| 165 | possible at every power domain level in the platform. This macro should be |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 166 | a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 167 | PSCI implementation to distinguish between retention and power down local |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 168 | power states within PSCI_CPU_SUSPEND call. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 169 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 170 | - **#define : PLAT_MAX_PWR_LVL_STATES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 171 | |
| 172 | Defines the maximum number of local power states per power domain level |
| 173 | that the platform supports. The default value of this macro is 2 since |
| 174 | most platforms just support a maximum of two local power states at each |
| 175 | power domain level (power-down and retention). If the platform needs to |
| 176 | account for more local power states, then it must redefine this macro. |
| 177 | |
| 178 | Currently, this macro is used by the Generic PSCI implementation to size |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 179 | the array used for PSCI_STAT_COUNT/RESIDENCY accounting. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 180 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 181 | - **#define : BL1_RO_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 182 | |
| 183 | Defines the base address in secure ROM where BL1 originally lives. Must be |
| 184 | aligned on a page-size boundary. |
| 185 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 186 | - **#define : BL1_RO_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 187 | |
| 188 | Defines the maximum address in secure ROM that BL1's actual content (i.e. |
| 189 | excluding any data section allocated at runtime) can occupy. |
| 190 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 191 | - **#define : BL1_RW_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 192 | |
| 193 | Defines the base address in secure RAM where BL1's read-write data will live |
| 194 | at runtime. Must be aligned on a page-size boundary. |
| 195 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 196 | - **#define : BL1_RW_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 197 | |
| 198 | Defines the maximum address in secure RAM that BL1's read-write data can |
| 199 | occupy at runtime. |
| 200 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 201 | - **#define : BL2_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 202 | |
| 203 | Defines the base address in secure RAM where BL1 loads the BL2 binary image. |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 204 | Must be aligned on a page-size boundary. This constant is not applicable |
| 205 | when BL2_IN_XIP_MEM is set to '1'. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 206 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 207 | - **#define : BL2_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 208 | |
| 209 | Defines the maximum address in secure RAM that the BL2 image can occupy. |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 210 | This constant is not applicable when BL2_IN_XIP_MEM is set to '1'. |
| 211 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 212 | - **#define : BL2_RO_BASE** |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 213 | |
| 214 | Defines the base address in secure XIP memory where BL2 RO section originally |
| 215 | lives. Must be aligned on a page-size boundary. This constant is only needed |
| 216 | when BL2_IN_XIP_MEM is set to '1'. |
| 217 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 218 | - **#define : BL2_RO_LIMIT** |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 219 | |
| 220 | Defines the maximum address in secure XIP memory that BL2's actual content |
| 221 | (i.e. excluding any data section allocated at runtime) can occupy. This |
| 222 | constant is only needed when BL2_IN_XIP_MEM is set to '1'. |
| 223 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 224 | - **#define : BL2_RW_BASE** |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 225 | |
| 226 | Defines the base address in secure RAM where BL2's read-write data will live |
| 227 | at runtime. Must be aligned on a page-size boundary. This constant is only |
| 228 | needed when BL2_IN_XIP_MEM is set to '1'. |
| 229 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 230 | - **#define : BL2_RW_LIMIT** |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 231 | |
| 232 | Defines the maximum address in secure RAM that BL2's read-write data can |
| 233 | occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set |
| 234 | to '1'. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 235 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 236 | - **#define : BL31_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 237 | |
| 238 | Defines the base address in secure RAM where BL2 loads the BL31 binary |
| 239 | image. Must be aligned on a page-size boundary. |
| 240 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 241 | - **#define : BL31_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 242 | |
| 243 | Defines the maximum address in secure RAM that the BL31 image can occupy. |
| 244 | |
Tamas Ban | 1d3354e | 2022-09-16 14:09:30 +0200 | [diff] [blame] | 245 | - **#define : PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE** |
| 246 | |
| 247 | Defines the maximum message size between AP and RSS. Need to define if |
| 248 | platform supports RSS. |
| 249 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 250 | For every image, the platform must define individual identifiers that will be |
| 251 | used by BL1 or BL2 to load the corresponding image into memory from non-volatile |
| 252 | storage. For the sake of performance, integer numbers will be used as |
| 253 | identifiers. The platform will use those identifiers to return the relevant |
| 254 | information about the image to be loaded (file handler, load address, |
| 255 | authentication information, etc.). The following image identifiers are |
| 256 | mandatory: |
| 257 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 258 | - **#define : BL2_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 259 | |
| 260 | BL2 image identifier, used by BL1 to load BL2. |
| 261 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 262 | - **#define : BL31_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 263 | |
| 264 | BL31 image identifier, used by BL2 to load BL31. |
| 265 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 266 | - **#define : BL33_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 267 | |
| 268 | BL33 image identifier, used by BL2 to load BL33. |
| 269 | |
| 270 | If Trusted Board Boot is enabled, the following certificate identifiers must |
| 271 | also be defined: |
| 272 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 273 | - **#define : TRUSTED_BOOT_FW_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 274 | |
| 275 | BL2 content certificate identifier, used by BL1 to load the BL2 content |
| 276 | certificate. |
| 277 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 278 | - **#define : TRUSTED_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 279 | |
| 280 | Trusted key certificate identifier, used by BL2 to load the trusted key |
| 281 | certificate. |
| 282 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 283 | - **#define : SOC_FW_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 284 | |
| 285 | BL31 key certificate identifier, used by BL2 to load the BL31 key |
| 286 | certificate. |
| 287 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 288 | - **#define : SOC_FW_CONTENT_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 289 | |
| 290 | BL31 content certificate identifier, used by BL2 to load the BL31 content |
| 291 | certificate. |
| 292 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 293 | - **#define : NON_TRUSTED_FW_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 294 | |
| 295 | BL33 key certificate identifier, used by BL2 to load the BL33 key |
| 296 | certificate. |
| 297 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 298 | - **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 299 | |
| 300 | BL33 content certificate identifier, used by BL2 to load the BL33 content |
| 301 | certificate. |
| 302 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 303 | - **#define : FWU_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 304 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 305 | Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 306 | FWU content certificate. |
| 307 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 308 | - **#define : PLAT_CRYPTOCELL_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 309 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 310 | This defines the base address of Arm® TrustZone® CryptoCell and must be |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 311 | defined if CryptoCell crypto driver is used for Trusted Board Boot. For |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 312 | capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 313 | set. |
| 314 | |
| 315 | If the AP Firmware Updater Configuration image, BL2U is used, the following |
| 316 | must also be defined: |
| 317 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 318 | - **#define : BL2U_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 319 | |
| 320 | Defines the base address in secure memory where BL1 copies the BL2U binary |
| 321 | image. Must be aligned on a page-size boundary. |
| 322 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 323 | - **#define : BL2U_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 324 | |
| 325 | Defines the maximum address in secure memory that the BL2U image can occupy. |
| 326 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 327 | - **#define : BL2U_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 328 | |
| 329 | BL2U image identifier, used by BL1 to fetch an image descriptor |
| 330 | corresponding to BL2U. |
| 331 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 332 | If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 333 | must also be defined: |
| 334 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 335 | - **#define : SCP_BL2U_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 336 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 337 | SCP_BL2U image identifier, used by BL1 to fetch an image descriptor |
| 338 | corresponding to SCP_BL2U. |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 339 | |
| 340 | .. note:: |
| 341 | TF-A does not provide source code for this image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 342 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 343 | If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 344 | also be defined: |
| 345 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 346 | - **#define : NS_BL1U_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 347 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 348 | Defines the base address in non-secure ROM where NS_BL1U executes. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 349 | Must be aligned on a page-size boundary. |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 350 | |
| 351 | .. note:: |
| 352 | TF-A does not provide source code for this image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 353 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 354 | - **#define : NS_BL1U_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 355 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 356 | NS_BL1U image identifier, used by BL1 to fetch an image descriptor |
| 357 | corresponding to NS_BL1U. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 358 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 359 | If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 360 | be defined: |
| 361 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 362 | - **#define : NS_BL2U_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 363 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 364 | Defines the base address in non-secure memory where NS_BL2U executes. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 365 | Must be aligned on a page-size boundary. |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 366 | |
| 367 | .. note:: |
| 368 | TF-A does not provide source code for this image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 369 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 370 | - **#define : NS_BL2U_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 371 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 372 | NS_BL2U image identifier, used by BL1 to fetch an image descriptor |
| 373 | corresponding to NS_BL2U. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 374 | |
| 375 | For the the Firmware update capability of TRUSTED BOARD BOOT, the following |
| 376 | macros may also be defined: |
| 377 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 378 | - **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 379 | |
| 380 | Total number of images that can be loaded simultaneously. If the platform |
| 381 | doesn't specify any value, it defaults to 10. |
| 382 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 383 | If a SCP_BL2 image is supported by the platform, the following constants must |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 384 | also be defined: |
| 385 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 386 | - **#define : SCP_BL2_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 387 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 388 | SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 389 | from platform storage before being transferred to the SCP. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 390 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 391 | - **#define : SCP_FW_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 392 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 393 | SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 394 | certificate (mandatory when Trusted Board Boot is enabled). |
| 395 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 396 | - **#define : SCP_FW_CONTENT_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 397 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 398 | SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 399 | content certificate (mandatory when Trusted Board Boot is enabled). |
| 400 | |
| 401 | If a BL32 image is supported by the platform, the following constants must |
| 402 | also be defined: |
| 403 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 404 | - **#define : BL32_IMAGE_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 405 | |
| 406 | BL32 image identifier, used by BL2 to load BL32. |
| 407 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 408 | - **#define : TRUSTED_OS_FW_KEY_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 409 | |
| 410 | BL32 key certificate identifier, used by BL2 to load the BL32 key |
| 411 | certificate (mandatory when Trusted Board Boot is enabled). |
| 412 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 413 | - **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 414 | |
| 415 | BL32 content certificate identifier, used by BL2 to load the BL32 content |
| 416 | certificate (mandatory when Trusted Board Boot is enabled). |
| 417 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 418 | - **#define : BL32_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 419 | |
| 420 | Defines the base address in secure memory where BL2 loads the BL32 binary |
| 421 | image. Must be aligned on a page-size boundary. |
| 422 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 423 | - **#define : BL32_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 424 | |
| 425 | Defines the maximum address that the BL32 image can occupy. |
| 426 | |
| 427 | If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the |
| 428 | platform, the following constants must also be defined: |
| 429 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 430 | - **#define : TSP_SEC_MEM_BASE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 431 | |
| 432 | Defines the base address of the secure memory used by the TSP image on the |
| 433 | platform. This must be at the same address or below ``BL32_BASE``. |
| 434 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 435 | - **#define : TSP_SEC_MEM_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 436 | |
| 437 | Defines the size of the secure memory used by the BL32 image on the |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 438 | platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully |
| 439 | accommodate the memory required by the BL32 image, defined by ``BL32_BASE`` |
| 440 | and ``BL32_LIMIT``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 441 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 442 | - **#define : TSP_IRQ_SEC_PHY_TIMER** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 443 | |
| 444 | Defines the ID of the secure physical generic timer interrupt used by the |
| 445 | TSP's interrupt handling code. |
| 446 | |
| 447 | If the platform port uses the translation table library code, the following |
| 448 | constants must also be defined: |
| 449 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 450 | - **#define : PLAT_XLAT_TABLES_DYNAMIC** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 451 | |
| 452 | Optional flag that can be set per-image to enable the dynamic allocation of |
| 453 | regions even when the MMU is enabled. If not defined, only static |
| 454 | functionality will be available, if defined and set to 1 it will also |
| 455 | include the dynamic functionality. |
| 456 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 457 | - **#define : MAX_XLAT_TABLES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 458 | |
| 459 | Defines the maximum number of translation tables that are allocated by the |
| 460 | translation table library code. To minimize the amount of runtime memory |
| 461 | used, choose the smallest value needed to map the required virtual addresses |
| 462 | for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL |
| 463 | image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions |
| 464 | as well. |
| 465 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 466 | - **#define : MAX_MMAP_REGIONS** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 467 | |
| 468 | Defines the maximum number of regions that are allocated by the translation |
| 469 | table library code. A region consists of physical base address, virtual base |
| 470 | address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as |
| 471 | defined in the ``mmap_region_t`` structure. The platform defines the regions |
| 472 | that should be mapped. Then, the translation table library will create the |
| 473 | corresponding tables and descriptors at runtime. To minimize the amount of |
| 474 | runtime memory used, choose the smallest value needed to register the |
| 475 | required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is |
| 476 | enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate |
| 477 | the dynamic regions as well. |
| 478 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 479 | - **#define : PLAT_VIRT_ADDR_SPACE_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 480 | |
| 481 | Defines the total size of the virtual address space in bytes. For example, |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 482 | for a 32 bit virtual address space, this value should be ``(1ULL << 32)``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 483 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 484 | - **#define : PLAT_PHY_ADDR_SPACE_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 485 | |
| 486 | Defines the total size of the physical address space in bytes. For example, |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 487 | for a 32 bit physical address space, this value should be ``(1ULL << 32)``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 488 | |
| 489 | If the platform port uses the IO storage framework, the following constants |
| 490 | must also be defined: |
| 491 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 492 | - **#define : MAX_IO_DEVICES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 493 | |
| 494 | Defines the maximum number of registered IO devices. Attempting to register |
| 495 | more devices than this value using ``io_register_device()`` will fail with |
| 496 | -ENOMEM. |
| 497 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 498 | - **#define : MAX_IO_HANDLES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 499 | |
| 500 | Defines the maximum number of open IO handles. Attempting to open more IO |
| 501 | entities than this value using ``io_open()`` will fail with -ENOMEM. |
| 502 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 503 | - **#define : MAX_IO_BLOCK_DEVICES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 504 | |
| 505 | Defines the maximum number of registered IO block devices. Attempting to |
| 506 | register more devices this value using ``io_dev_open()`` will fail |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 507 | with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 508 | With this macro, multiple block devices could be supported at the same |
| 509 | time. |
| 510 | |
| 511 | If the platform needs to allocate data within the per-cpu data framework in |
| 512 | BL31, it should define the following macro. Currently this is only required if |
| 513 | the platform decides not to use the coherent memory section by undefining the |
| 514 | ``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the |
| 515 | required memory within the the per-cpu data to minimize wastage. |
| 516 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 517 | - **#define : PLAT_PCPU_DATA_SIZE** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 518 | |
| 519 | Defines the memory (in bytes) to be reserved within the per-cpu data |
| 520 | structure for use by the platform layer. |
| 521 | |
| 522 | The following constants are optional. They should be defined when the platform |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 523 | memory layout implies some image overlaying like in Arm standard platforms. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 524 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 525 | - **#define : BL31_PROGBITS_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 526 | |
| 527 | Defines the maximum address in secure RAM that the BL31's progbits sections |
| 528 | can occupy. |
| 529 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 530 | - **#define : TSP_PROGBITS_LIMIT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 531 | |
| 532 | Defines the maximum address that the TSP's progbits sections can occupy. |
| 533 | |
| 534 | If the platform port uses the PL061 GPIO driver, the following constant may |
| 535 | optionally be defined: |
| 536 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 537 | - **PLAT_PL061_MAX_GPIOS** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 538 | Maximum number of GPIOs required by the platform. This allows control how |
| 539 | much memory is allocated for PL061 GPIO controllers. The default value is |
| 540 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 541 | #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 542 | |
| 543 | If the platform port uses the partition driver, the following constant may |
| 544 | optionally be defined: |
| 545 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 546 | - **PLAT_PARTITION_MAX_ENTRIES** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 547 | Maximum number of partition entries required by the platform. This allows |
| 548 | control how much memory is allocated for partition entries. The default |
| 549 | value is 128. |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 550 | For example, define the build flag in ``platform.mk``: |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 551 | PLAT_PARTITION_MAX_ENTRIES := 12 |
| 552 | $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 553 | |
Haojian Zhuang | 42a746d | 2019-09-14 18:01:16 +0800 | [diff] [blame] | 554 | - **PLAT_PARTITION_BLOCK_SIZE** |
| 555 | The size of partition block. It could be either 512 bytes or 4096 bytes. |
| 556 | The default value is 512. |
Paul Beesley | f2ec714 | 2019-10-04 16:17:46 +0000 | [diff] [blame] | 557 | For example, define the build flag in ``platform.mk``: |
Haojian Zhuang | 42a746d | 2019-09-14 18:01:16 +0800 | [diff] [blame] | 558 | PLAT_PARTITION_BLOCK_SIZE := 4096 |
| 559 | $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE)) |
| 560 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 561 | The following constant is optional. It should be defined to override the default |
| 562 | behaviour of the ``assert()`` function (for example, to save memory). |
| 563 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 564 | - **PLAT_LOG_LEVEL_ASSERT** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 565 | If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``, |
| 566 | ``assert()`` prints the name of the file, the line number and the asserted |
| 567 | expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file |
| 568 | name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it |
| 569 | doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't |
| 570 | defined, it defaults to ``LOG_LEVEL``. |
| 571 | |
Lucian Paul-Trifu | b93037a | 2022-06-22 18:45:36 +0100 | [diff] [blame] | 572 | If the platform port uses the DRTM feature, the following constants must be |
| 573 | defined: |
| 574 | |
| 575 | - **#define : PLAT_DRTM_EVENT_LOG_MAX_SIZE** |
| 576 | |
| 577 | Maximum Event Log size used by the platform. Platform can decide the maximum |
| 578 | size of the Event Log buffer, depending upon the highest hash algorithm |
| 579 | chosen and the number of components selected to measure during the DRTM |
| 580 | execution flow. |
| 581 | |
| 582 | - **#define : PLAT_DRTM_MMAP_ENTRIES** |
| 583 | |
| 584 | Number of the MMAP entries used by the DRTM implementation to calculate the |
| 585 | size of address map region of the platform. |
| 586 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 587 | File : plat_macros.S [mandatory] |
| 588 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 589 | |
| 590 | Each platform must ensure a file of this name is in the system include path with |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 591 | the following macro defined. In the Arm development platforms, this file is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 592 | found in ``plat/arm/board/<plat_name>/include/plat_macros.S``. |
| 593 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 594 | - **Macro : plat_crash_print_regs** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 595 | |
| 596 | This macro allows the crash reporting routine to print relevant platform |
| 597 | registers in case of an unhandled exception in BL31. This aids in debugging |
| 598 | and this macro can be defined to be empty in case register reporting is not |
| 599 | desired. |
| 600 | |
| 601 | For instance, GIC or interconnect registers may be helpful for |
| 602 | troubleshooting. |
| 603 | |
| 604 | Handling Reset |
| 605 | -------------- |
| 606 | |
| 607 | BL1 by default implements the reset vector where execution starts from a cold |
| 608 | or warm boot. BL31 can be optionally set as a reset vector using the |
| 609 | ``RESET_TO_BL31`` make variable. |
| 610 | |
| 611 | For each CPU, the reset vector code is responsible for the following tasks: |
| 612 | |
| 613 | #. Distinguishing between a cold boot and a warm boot. |
| 614 | |
| 615 | #. In the case of a cold boot and the CPU being a secondary CPU, ensuring that |
| 616 | the CPU is placed in a platform-specific state until the primary CPU |
| 617 | performs the necessary steps to remove it from this state. |
| 618 | |
| 619 | #. In the case of a warm boot, ensuring that the CPU jumps to a platform- |
| 620 | specific address in the BL31 image in the same processor mode as it was |
| 621 | when released from reset. |
| 622 | |
| 623 | The following functions need to be implemented by the platform port to enable |
| 624 | reset vector code to perform the above tasks. |
| 625 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 626 | Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] |
| 627 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 628 | |
| 629 | :: |
| 630 | |
| 631 | Argument : void |
| 632 | Return : uintptr_t |
| 633 | |
| 634 | This function is called with the MMU and caches disabled |
| 635 | (``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for |
| 636 | distinguishing between a warm and cold reset for the current CPU using |
| 637 | platform-specific means. If it's a warm reset, then it returns the warm |
| 638 | reset entrypoint point provided to ``plat_setup_psci_ops()`` during |
| 639 | BL31 initialization. If it's a cold reset then this function must return zero. |
| 640 | |
| 641 | This function does not follow the Procedure Call Standard used by the |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 642 | Application Binary Interface for the Arm 64-bit architecture. The caller should |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 643 | not assume that callee saved registers are preserved across a call to this |
| 644 | function. |
| 645 | |
| 646 | This function fulfills requirement 1 and 3 listed above. |
| 647 | |
| 648 | Note that for platforms that support programming the reset address, it is |
| 649 | expected that a CPU will start executing code directly at the right address, |
| 650 | both on a cold and warm reset. In this case, there is no need to identify the |
| 651 | type of reset nor to query the warm reset entrypoint. Therefore, implementing |
| 652 | this function is not required on such platforms. |
| 653 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 654 | Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] |
| 655 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 656 | |
| 657 | :: |
| 658 | |
| 659 | Argument : void |
| 660 | |
| 661 | This function is called with the MMU and data caches disabled. It is responsible |
| 662 | for placing the executing secondary CPU in a platform-specific state until the |
| 663 | primary CPU performs the necessary actions to bring it out of that state and |
| 664 | allow entry into the OS. This function must not return. |
| 665 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 666 | In the Arm FVP port, when using the normal boot flow, each secondary CPU powers |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 667 | itself off. The primary CPU is responsible for powering up the secondary CPUs |
| 668 | when normal world software requires them. When booting an EL3 payload instead, |
| 669 | they stay powered on and are put in a holding pen until their mailbox gets |
| 670 | populated. |
| 671 | |
| 672 | This function fulfills requirement 2 above. |
| 673 | |
| 674 | Note that for platforms that can't release secondary CPUs out of reset, only the |
| 675 | primary CPU will execute the cold boot code. Therefore, implementing this |
| 676 | function is not required on such platforms. |
| 677 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 678 | Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] |
| 679 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 680 | |
| 681 | :: |
| 682 | |
| 683 | Argument : void |
| 684 | Return : unsigned int |
| 685 | |
| 686 | This function identifies whether the current CPU is the primary CPU or a |
| 687 | secondary CPU. A return value of zero indicates that the CPU is not the |
| 688 | primary CPU, while a non-zero return value indicates that the CPU is the |
| 689 | primary CPU. |
| 690 | |
| 691 | Note that for platforms that can't release secondary CPUs out of reset, only the |
| 692 | primary CPU will execute the cold boot code. Therefore, there is no need to |
| 693 | distinguish between primary and secondary CPUs and implementing this function is |
| 694 | not required. |
| 695 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 696 | Function : platform_mem_init() [mandatory] |
| 697 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 698 | |
| 699 | :: |
| 700 | |
| 701 | Argument : void |
| 702 | Return : void |
| 703 | |
| 704 | This function is called before any access to data is made by the firmware, in |
| 705 | order to carry out any essential memory initialization. |
| 706 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 707 | Function: plat_get_rotpk_info() |
| 708 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 709 | |
| 710 | :: |
| 711 | |
| 712 | Argument : void *, void **, unsigned int *, unsigned int * |
| 713 | Return : int |
| 714 | |
| 715 | This function is mandatory when Trusted Board Boot is enabled. It returns a |
| 716 | pointer to the ROTPK stored in the platform (or a hash of it) and its length. |
| 717 | The ROTPK must be encoded in DER format according to the following ASN.1 |
| 718 | structure: |
| 719 | |
| 720 | :: |
| 721 | |
| 722 | AlgorithmIdentifier ::= SEQUENCE { |
| 723 | algorithm OBJECT IDENTIFIER, |
| 724 | parameters ANY DEFINED BY algorithm OPTIONAL |
| 725 | } |
| 726 | |
| 727 | SubjectPublicKeyInfo ::= SEQUENCE { |
| 728 | algorithm AlgorithmIdentifier, |
| 729 | subjectPublicKey BIT STRING |
| 730 | } |
| 731 | |
| 732 | In case the function returns a hash of the key: |
| 733 | |
| 734 | :: |
| 735 | |
| 736 | DigestInfo ::= SEQUENCE { |
| 737 | digestAlgorithm AlgorithmIdentifier, |
| 738 | digest OCTET STRING |
| 739 | } |
| 740 | |
| 741 | The function returns 0 on success. Any other value is treated as error by the |
| 742 | Trusted Board Boot. The function also reports extra information related |
| 743 | to the ROTPK in the flags parameter: |
| 744 | |
| 745 | :: |
| 746 | |
| 747 | ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a |
| 748 | hash. |
| 749 | ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK |
| 750 | verification while the platform ROTPK is not deployed. |
| 751 | When this flag is set, the function does not need to |
| 752 | return a platform ROTPK, and the authentication |
| 753 | framework uses the ROTPK in the certificate without |
| 754 | verifying it against the platform value. This flag |
| 755 | must not be used in a deployed production environment. |
| 756 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 757 | Function: plat_get_nv_ctr() |
| 758 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 759 | |
| 760 | :: |
| 761 | |
| 762 | Argument : void *, unsigned int * |
| 763 | Return : int |
| 764 | |
| 765 | This function is mandatory when Trusted Board Boot is enabled. It returns the |
| 766 | non-volatile counter value stored in the platform in the second argument. The |
| 767 | cookie in the first argument may be used to select the counter in case the |
| 768 | platform provides more than one (for example, on platforms that use the default |
| 769 | TBBR CoT, the cookie will correspond to the OID values defined in |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 770 | TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 771 | |
| 772 | The function returns 0 on success. Any other value means the counter value could |
| 773 | not be retrieved from the platform. |
| 774 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 775 | Function: plat_set_nv_ctr() |
| 776 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 777 | |
| 778 | :: |
| 779 | |
| 780 | Argument : void *, unsigned int |
| 781 | Return : int |
| 782 | |
| 783 | This function is mandatory when Trusted Board Boot is enabled. It sets a new |
| 784 | counter value in the platform. The cookie in the first argument may be used to |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 785 | select the counter (as explained in plat_get_nv_ctr()). The second argument is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 786 | the updated counter value to be written to the NV counter. |
| 787 | |
| 788 | The function returns 0 on success. Any other value means the counter value could |
| 789 | not be updated. |
| 790 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 791 | Function: plat_set_nv_ctr2() |
| 792 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 793 | |
| 794 | :: |
| 795 | |
| 796 | Argument : void *, const auth_img_desc_t *, unsigned int |
| 797 | Return : int |
| 798 | |
| 799 | This function is optional when Trusted Board Boot is enabled. If this |
| 800 | interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The |
| 801 | first argument passed is a cookie and is typically used to |
| 802 | differentiate between a Non Trusted NV Counter and a Trusted NV |
| 803 | Counter. The second argument is a pointer to an authentication image |
| 804 | descriptor and may be used to decide if the counter is allowed to be |
| 805 | updated or not. The third argument is the updated counter value to |
| 806 | be written to the NV counter. |
| 807 | |
| 808 | The function returns 0 on success. Any other value means the counter value |
| 809 | either could not be updated or the authentication image descriptor indicates |
| 810 | that it is not allowed to be updated. |
| 811 | |
Nicolas Toromanoff | 7f95ac8 | 2020-11-09 12:14:52 +0100 | [diff] [blame] | 812 | Function: plat_convert_pk() |
| 813 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 814 | |
| 815 | :: |
| 816 | |
| 817 | Argument : void *, unsigned int, void **, unsigned int * |
| 818 | Return : int |
| 819 | |
| 820 | This function is optional when Trusted Board Boot is enabled, and only |
| 821 | used if the platform saves a hash of the ROTPK. |
| 822 | First argument is the Distinguished Encoding Rules (DER) ROTPK. |
| 823 | Second argument is its size. |
| 824 | Third argument is used to return a pointer to a buffer, which hash should |
| 825 | be the one saved in OTP. |
| 826 | Fourth argument is a pointer to return its size. |
| 827 | |
| 828 | Most platforms save the hash of the ROTPK, but some may save slightly different |
| 829 | information - e.g the hash of the ROTPK plus some related information. |
| 830 | Defining this function allows to transform the ROTPK used to verify |
| 831 | the signature to the buffer (a platform specific public key) which |
| 832 | hash is saved in OTP. |
| 833 | |
| 834 | The default implementation copies the input key and length to the output without |
| 835 | modification. |
| 836 | |
| 837 | The function returns 0 on success. Any other value means the expected |
| 838 | public key buffer cannot be extracted. |
| 839 | |
Lucian Paul-Trifu | b93037a | 2022-06-22 18:45:36 +0100 | [diff] [blame] | 840 | Dynamic Root of Trust for Measurement support (in BL31) |
| 841 | ------------------------------------------------------- |
| 842 | |
| 843 | The functions mentioned in this section are mandatory, when platform enables |
| 844 | DRTM_SUPPORT build flag. |
| 845 | |
| 846 | Function : plat_get_addr_mmap() |
| 847 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 848 | |
| 849 | :: |
| 850 | |
| 851 | Argument : void |
| 852 | Return : const mmap_region_t * |
| 853 | |
| 854 | This function is used to return the address of the platform *address-map* table, |
| 855 | which describes the regions of normal memory, memory mapped I/O |
| 856 | and non-volatile memory. |
| 857 | |
| 858 | Function : plat_has_non_host_platforms() |
| 859 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 860 | |
| 861 | :: |
| 862 | |
| 863 | Argument : void |
| 864 | Return : bool |
| 865 | |
| 866 | This function returns *true* if the platform has any trusted devices capable of |
| 867 | DMA, otherwise returns *false*. |
| 868 | |
| 869 | Function : plat_has_unmanaged_dma_peripherals() |
| 870 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 871 | |
| 872 | :: |
| 873 | |
| 874 | Argument : void |
| 875 | Return : bool |
| 876 | |
| 877 | This function returns *true* if platform uses peripherals whose DMA is not |
| 878 | managed by an SMMU, otherwise returns *false*. |
| 879 | |
| 880 | Note - |
| 881 | If the platform has peripherals that are not managed by the SMMU, then the |
| 882 | platform should investigate such peripherals to determine whether they can |
| 883 | be trusted, and such peripherals should be moved under "Non-host platforms" |
| 884 | if they can be trusted. |
| 885 | |
| 886 | Function : plat_get_total_num_smmus() |
| 887 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 888 | |
| 889 | :: |
| 890 | |
| 891 | Argument : void |
| 892 | Return : unsigned int |
| 893 | |
| 894 | This function returns the total number of SMMUs in the platform. |
| 895 | |
| 896 | Function : plat_enumerate_smmus() |
| 897 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 898 | :: |
| 899 | |
| 900 | |
| 901 | Argument : void |
| 902 | Return : const uintptr_t *, size_t |
| 903 | |
| 904 | This function returns an array of SMMU addresses and the actual number of SMMUs |
| 905 | reported by the platform. |
| 906 | |
| 907 | Function : plat_drtm_get_dma_prot_features() |
| 908 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 909 | |
| 910 | :: |
| 911 | |
| 912 | Argument : void |
| 913 | Return : const plat_drtm_dma_prot_features_t* |
| 914 | |
| 915 | This function returns the address of plat_drtm_dma_prot_features_t structure |
| 916 | containing the maximum number of protected regions and bitmap with the types |
| 917 | of DMA protection supported by the platform. |
| 918 | For more details see section 3.3 Table 6 of `DRTM`_ specification. |
| 919 | |
| 920 | Function : plat_drtm_dma_prot_get_max_table_bytes() |
| 921 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 922 | |
| 923 | :: |
| 924 | |
| 925 | Argument : void |
| 926 | Return : uint64_t |
| 927 | |
| 928 | This function returns the maximum size of DMA protected regions table in |
| 929 | bytes. |
| 930 | |
| 931 | Function : plat_drtm_get_tpm_features() |
| 932 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 933 | |
| 934 | :: |
| 935 | |
| 936 | Argument : void |
| 937 | Return : const plat_drtm_tpm_features_t* |
| 938 | |
| 939 | This function returns the address of *plat_drtm_tpm_features_t* structure |
| 940 | containing PCR usage schema, TPM-based hash, and firmware hash algorithm |
| 941 | supported by the platform. |
| 942 | |
| 943 | Function : plat_drtm_get_min_size_normal_world_dce() |
| 944 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 945 | |
| 946 | :: |
| 947 | |
| 948 | Argument : void |
| 949 | Return : uint64_t |
| 950 | |
| 951 | This function returns the size normal-world DCE of the platform. |
| 952 | |
| 953 | Function : plat_drtm_get_imp_def_dlme_region_size() |
| 954 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 955 | |
| 956 | :: |
| 957 | |
| 958 | Argument : void |
| 959 | Return : uint64_t |
| 960 | |
| 961 | This function returns the size of implementation defined DLME region |
| 962 | of the platform. |
| 963 | |
| 964 | Function : plat_drtm_get_tcb_hash_table_size() |
| 965 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 966 | |
| 967 | :: |
| 968 | |
| 969 | Argument : void |
| 970 | Return : uint64_t |
| 971 | |
| 972 | This function returns the size of TCB hash table of the platform. |
| 973 | |
| 974 | Function : plat_drtm_get_tcb_hash_features() |
| 975 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 976 | |
| 977 | :: |
| 978 | |
| 979 | Argument : void |
| 980 | Return : uint64_t |
| 981 | |
| 982 | This function returns the Maximum number of TCB hashes recorded by the |
| 983 | platform. |
| 984 | For more details see section 3.3 Table 6 of `DRTM`_ specification. |
| 985 | |
| 986 | Function : plat_drtm_validate_ns_region() |
| 987 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 988 | |
| 989 | :: |
| 990 | |
| 991 | Argument : uintptr_t, uintptr_t |
| 992 | Return : int |
| 993 | |
| 994 | This function validates that given region is within the Non-Secure region |
| 995 | of DRAM. This function takes a region start address and size an input |
| 996 | arguments, and returns 0 on success and -1 on failure. |
| 997 | |
| 998 | Function : plat_set_drtm_error() |
| 999 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1000 | |
| 1001 | :: |
| 1002 | |
| 1003 | Argument : uint64_t |
| 1004 | Return : int |
| 1005 | |
| 1006 | This function writes a 64 bit error code received as input into |
| 1007 | non-volatile storage and returns 0 on success and -1 on failure. |
| 1008 | |
| 1009 | Function : plat_get_drtm_error() |
| 1010 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1011 | |
| 1012 | :: |
| 1013 | |
| 1014 | Argument : uint64_t* |
| 1015 | Return : int |
| 1016 | |
| 1017 | This function reads a 64 bit error code from the non-volatile storage |
| 1018 | into the received address, and returns 0 on success and -1 on failure. |
| 1019 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1020 | Common mandatory function modifications |
| 1021 | --------------------------------------- |
| 1022 | |
| 1023 | The following functions are mandatory functions which need to be implemented |
| 1024 | by the platform port. |
| 1025 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1026 | Function : plat_my_core_pos() |
| 1027 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1028 | |
| 1029 | :: |
| 1030 | |
| 1031 | Argument : void |
| 1032 | Return : unsigned int |
| 1033 | |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 1034 | This function returns the index of the calling CPU which is used as a |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1035 | CPU-specific linear index into blocks of memory (for example while allocating |
| 1036 | per-CPU stacks). This function will be invoked very early in the |
| 1037 | initialization sequence which mandates that this function should be |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 1038 | implemented in assembly and should not rely on the availability of a C |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1039 | runtime environment. This function can clobber x0 - x8 and must preserve |
| 1040 | x9 - x29. |
| 1041 | |
| 1042 | This function plays a crucial role in the power domain topology framework in |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1043 | PSCI and details of this can be found in |
| 1044 | :ref:`PSCI Power Domain Tree Structure`. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1045 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1046 | Function : plat_core_pos_by_mpidr() |
| 1047 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1048 | |
| 1049 | :: |
| 1050 | |
| 1051 | Argument : u_register_t |
| 1052 | Return : int |
| 1053 | |
| 1054 | This function validates the ``MPIDR`` of a CPU and converts it to an index, |
| 1055 | which can be used as a CPU-specific linear index into blocks of memory. In |
| 1056 | case the ``MPIDR`` is invalid, this function returns -1. This function will only |
| 1057 | be invoked by BL31 after the power domain topology is initialized and can |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1058 | utilize the C runtime environment. For further details about how TF-A |
| 1059 | represents the power domain topology and how this relates to the linear CPU |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1060 | index, please refer :ref:`PSCI Power Domain Tree Structure`. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1061 | |
Ambroise Vincent | d207f56 | 2019-04-10 12:50:27 +0100 | [diff] [blame] | 1062 | Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1] |
| 1063 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1064 | |
| 1065 | :: |
| 1066 | |
| 1067 | Arguments : void **heap_addr, size_t *heap_size |
| 1068 | Return : int |
| 1069 | |
| 1070 | This function is invoked during Mbed TLS library initialisation to get a heap, |
| 1071 | by means of a starting address and a size. This heap will then be used |
| 1072 | internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS |
| 1073 | must be able to provide a heap to it. |
| 1074 | |
| 1075 | A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in |
| 1076 | which a heap is statically reserved during compile time inside every image |
| 1077 | (i.e. every BL stage) that utilises Mbed TLS. In this default implementation, |
| 1078 | the function simply returns the address and size of this "pre-allocated" heap. |
| 1079 | For a platform to use this default implementation, only a call to the helper |
| 1080 | from inside plat_get_mbedtls_heap() body is enough and nothing else is needed. |
| 1081 | |
| 1082 | However, by writting their own implementation, platforms have the potential to |
| 1083 | optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is |
| 1084 | shared between BL1 and BL2 stages and, thus, the necessary space is not reserved |
| 1085 | twice. |
| 1086 | |
| 1087 | On success the function should return 0 and a negative error code otherwise. |
| 1088 | |
Sumit Garg | c0c369c | 2019-11-15 18:47:53 +0530 | [diff] [blame] | 1089 | Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1] |
| 1090 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1091 | |
| 1092 | :: |
| 1093 | |
| 1094 | Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key, |
| 1095 | size_t *key_len, unsigned int *flags, const uint8_t *img_id, |
| 1096 | size_t img_id_len |
| 1097 | Return : int |
| 1098 | |
| 1099 | This function provides a symmetric key (either SSK or BSSK depending on |
| 1100 | fw_enc_status) which is invoked during runtime decryption of encrypted |
| 1101 | firmware images. `plat/common/plat_bl_common.c` provides a dummy weak |
| 1102 | implementation for testing purposes which must be overridden by the platform |
| 1103 | trying to implement a real world firmware encryption use-case. |
| 1104 | |
| 1105 | It also allows the platform to pass symmetric key identifier rather than |
| 1106 | actual symmetric key which is useful in cases where the crypto backend provides |
| 1107 | secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER`` |
| 1108 | flag must be set in ``flags``. |
| 1109 | |
| 1110 | In addition to above a platform may also choose to provide an image specific |
| 1111 | symmetric key/identifier using img_id. |
| 1112 | |
| 1113 | On success the function should return 0 and a negative error code otherwise. |
| 1114 | |
Manish Pandey | 34a305e | 2021-10-21 21:53:49 +0100 | [diff] [blame] | 1115 | Note that this API depends on ``DECRYPTION_SUPPORT`` build flag. |
Sumit Garg | c0c369c | 2019-11-15 18:47:53 +0530 | [diff] [blame] | 1116 | |
Manish V Badarkhe | da87af1 | 2021-06-20 21:14:46 +0100 | [diff] [blame] | 1117 | Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1] |
| 1118 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1119 | |
| 1120 | :: |
| 1121 | |
Sughosh Ganu | f40154f | 2021-11-17 17:08:10 +0530 | [diff] [blame] | 1122 | Argument : const struct fwu_metadata *metadata |
Manish V Badarkhe | da87af1 | 2021-06-20 21:14:46 +0100 | [diff] [blame] | 1123 | Return : void |
| 1124 | |
| 1125 | This function is mandatory when PSA_FWU_SUPPORT is enabled. |
| 1126 | It provides a means to retrieve image specification (offset in |
| 1127 | non-volatile storage and length) of active/updated images using the passed |
| 1128 | FWU metadata, and update I/O policies of active/updated images using retrieved |
| 1129 | image specification information. |
| 1130 | Further I/O layer operations such as I/O open, I/O read, etc. on these |
| 1131 | images rely on this function call. |
| 1132 | |
| 1133 | In Arm platforms, this function is used to set an I/O policy of the FIP image, |
| 1134 | container of all active/updated secure and non-secure images. |
| 1135 | |
| 1136 | Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1] |
| 1137 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1138 | |
| 1139 | :: |
| 1140 | |
| 1141 | Argument : unsigned int image_id, uintptr_t *dev_handle, |
| 1142 | uintptr_t *image_spec |
| 1143 | Return : int |
| 1144 | |
| 1145 | This function is mandatory when PSA_FWU_SUPPORT is enabled. It is |
| 1146 | responsible for setting up the platform I/O policy of the requested metadata |
| 1147 | image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will |
| 1148 | be used to load this image from the platform's non-volatile storage. |
| 1149 | |
| 1150 | FWU metadata can not be always stored as a raw image in non-volatile storage |
| 1151 | to define its image specification (offset in non-volatile storage and length) |
| 1152 | statically in I/O policy. |
| 1153 | For example, the FWU metadata image is stored as a partition inside the GUID |
| 1154 | partition table image. Its specification is defined in the partition table |
| 1155 | that needs to be parsed dynamically. |
| 1156 | This function provides a means to retrieve such dynamic information to set |
| 1157 | the I/O policy of the FWU metadata image. |
| 1158 | Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata |
| 1159 | image relies on this function call. |
| 1160 | |
| 1161 | It returns '0' on success, otherwise a negative error value on error. |
| 1162 | Alongside, returns device handle and image specification from the I/O policy |
| 1163 | of the requested FWU metadata image. |
| 1164 | |
Sughosh Ganu | 4e336a6 | 2021-12-01 15:53:32 +0530 | [diff] [blame] | 1165 | Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1] |
| 1166 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1167 | |
| 1168 | :: |
| 1169 | |
| 1170 | Argument : void |
| 1171 | Return : uint32_t |
| 1172 | |
| 1173 | This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the |
| 1174 | means to retrieve the boot index value from the platform. The boot index is the |
| 1175 | bank from which the platform has booted the firmware images. |
| 1176 | |
| 1177 | By default, the platform will read the metadata structure and try to boot from |
| 1178 | the active bank. If the platform fails to boot from the active bank due to |
| 1179 | reasons like an Authentication failure, or on crossing a set number of watchdog |
| 1180 | resets while booting from the active bank, the platform can then switch to boot |
| 1181 | from a different bank. This function then returns the bank that the platform |
| 1182 | should boot its images from. |
| 1183 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1184 | Common optional modifications |
| 1185 | ----------------------------- |
| 1186 | |
| 1187 | The following are helper functions implemented by the firmware that perform |
| 1188 | common platform-specific tasks. A platform may choose to override these |
| 1189 | definitions. |
| 1190 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1191 | Function : plat_set_my_stack() |
| 1192 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1193 | |
| 1194 | :: |
| 1195 | |
| 1196 | Argument : void |
| 1197 | Return : void |
| 1198 | |
| 1199 | This function sets the current stack pointer to the normal memory stack that |
| 1200 | has been allocated for the current CPU. For BL images that only require a |
| 1201 | stack for the primary CPU, the UP version of the function is used. The size |
| 1202 | of the stack allocated to each CPU is specified by the platform defined |
| 1203 | constant ``PLATFORM_STACK_SIZE``. |
| 1204 | |
| 1205 | Common implementations of this function for the UP and MP BL images are |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1206 | provided in ``plat/common/aarch64/platform_up_stack.S`` and |
| 1207 | ``plat/common/aarch64/platform_mp_stack.S`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1208 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1209 | Function : plat_get_my_stack() |
| 1210 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1211 | |
| 1212 | :: |
| 1213 | |
| 1214 | Argument : void |
| 1215 | Return : uintptr_t |
| 1216 | |
| 1217 | This function returns the base address of the normal memory stack that |
| 1218 | has been allocated for the current CPU. For BL images that only require a |
| 1219 | stack for the primary CPU, the UP version of the function is used. The size |
| 1220 | of the stack allocated to each CPU is specified by the platform defined |
| 1221 | constant ``PLATFORM_STACK_SIZE``. |
| 1222 | |
| 1223 | Common implementations of this function for the UP and MP BL images are |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1224 | provided in ``plat/common/aarch64/platform_up_stack.S`` and |
| 1225 | ``plat/common/aarch64/platform_mp_stack.S`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1226 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1227 | Function : plat_report_exception() |
| 1228 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1229 | |
| 1230 | :: |
| 1231 | |
| 1232 | Argument : unsigned int |
| 1233 | Return : void |
| 1234 | |
| 1235 | A platform may need to report various information about its status when an |
| 1236 | exception is taken, for example the current exception level, the CPU security |
| 1237 | state (secure/non-secure), the exception type, and so on. This function is |
| 1238 | called in the following circumstances: |
| 1239 | |
| 1240 | - In BL1, whenever an exception is taken. |
| 1241 | - In BL2, whenever an exception is taken. |
| 1242 | |
| 1243 | The default implementation doesn't do anything, to avoid making assumptions |
| 1244 | about the way the platform displays its status information. |
| 1245 | |
| 1246 | For AArch64, this function receives the exception type as its argument. |
| 1247 | Possible values for exceptions types are listed in the |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1248 | ``include/common/bl_common.h`` header file. Note that these constants are not |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1249 | related to any architectural exception code; they are just a TF-A convention. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1250 | |
| 1251 | For AArch32, this function receives the exception mode as its argument. |
| 1252 | Possible values for exception modes are listed in the |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1253 | ``include/lib/aarch32/arch.h`` header file. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1254 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1255 | Function : plat_reset_handler() |
| 1256 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1257 | |
| 1258 | :: |
| 1259 | |
| 1260 | Argument : void |
| 1261 | Return : void |
| 1262 | |
| 1263 | A platform may need to do additional initialization after reset. This function |
Paul Beesley | f2ec714 | 2019-10-04 16:17:46 +0000 | [diff] [blame] | 1264 | allows the platform to do the platform specific initializations. Platform |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 1265 | specific errata workarounds could also be implemented here. The API should |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1266 | preserve the values of callee saved registers x19 to x29. |
| 1267 | |
| 1268 | The default implementation doesn't do anything. If a platform needs to override |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1269 | the default implementation, refer to the :ref:`Firmware Design` for general |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1270 | guidelines. |
| 1271 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1272 | Function : plat_disable_acp() |
| 1273 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1274 | |
| 1275 | :: |
| 1276 | |
| 1277 | Argument : void |
| 1278 | Return : void |
| 1279 | |
John Tsichritzis | 6dda976 | 2018-07-23 09:18:04 +0100 | [diff] [blame] | 1280 | This API allows a platform to disable the Accelerator Coherency Port (if |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1281 | present) during a cluster power down sequence. The default weak implementation |
John Tsichritzis | 6dda976 | 2018-07-23 09:18:04 +0100 | [diff] [blame] | 1282 | doesn't do anything. Since this API is called during the power down sequence, |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1283 | it has restrictions for stack usage and it can use the registers x0 - x17 as |
| 1284 | scratch registers. It should preserve the value in x18 register as it is used |
| 1285 | by the caller to store the return address. |
| 1286 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1287 | Function : plat_error_handler() |
| 1288 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1289 | |
| 1290 | :: |
| 1291 | |
| 1292 | Argument : int |
| 1293 | Return : void |
| 1294 | |
| 1295 | This API is called when the generic code encounters an error situation from |
| 1296 | which it cannot continue. It allows the platform to perform error reporting or |
| 1297 | recovery actions (for example, reset the system). This function must not return. |
| 1298 | |
| 1299 | The parameter indicates the type of error using standard codes from ``errno.h``. |
| 1300 | Possible errors reported by the generic code are: |
| 1301 | |
| 1302 | - ``-EAUTH``: a certificate or image could not be authenticated (when Trusted |
| 1303 | Board Boot is enabled) |
| 1304 | - ``-ENOENT``: the requested image or certificate could not be found or an IO |
| 1305 | error was detected |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1306 | - ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this |
| 1307 | error is usually an indication of an incorrect array size |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1308 | |
| 1309 | The default implementation simply spins. |
| 1310 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1311 | Function : plat_panic_handler() |
| 1312 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1313 | |
| 1314 | :: |
| 1315 | |
| 1316 | Argument : void |
| 1317 | Return : void |
| 1318 | |
| 1319 | This API is called when the generic code encounters an unexpected error |
| 1320 | situation from which it cannot recover. This function must not return, |
| 1321 | and must be implemented in assembly because it may be called before the C |
| 1322 | environment is initialized. |
| 1323 | |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 1324 | .. note:: |
| 1325 | The address from where it was called is stored in x30 (Link Register). |
| 1326 | The default implementation simply spins. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1327 | |
Lucian Paul-Trifu | b93037a | 2022-06-22 18:45:36 +0100 | [diff] [blame] | 1328 | Function : plat_system_reset() |
| 1329 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1330 | |
| 1331 | :: |
| 1332 | |
| 1333 | Argument : void |
| 1334 | Return : void |
| 1335 | |
| 1336 | This function is used by the platform to resets the system. It can be used |
| 1337 | in any specific use-case where system needs to be resetted. For example, |
| 1338 | in case of DRTM implementation this function reset the system after |
| 1339 | writing the DRTM error code in the non-volatile storage. This function |
| 1340 | never returns. Failure in reset results in panic. |
| 1341 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1342 | Function : plat_get_bl_image_load_info() |
| 1343 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1344 | |
| 1345 | :: |
| 1346 | |
| 1347 | Argument : void |
| 1348 | Return : bl_load_info_t * |
| 1349 | |
| 1350 | This function returns pointer to the list of images that the platform has |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1351 | populated to load. This function is invoked in BL2 to load the |
| 1352 | BL3xx images. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1353 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1354 | Function : plat_get_next_bl_params() |
| 1355 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1356 | |
| 1357 | :: |
| 1358 | |
| 1359 | Argument : void |
| 1360 | Return : bl_params_t * |
| 1361 | |
| 1362 | This function returns a pointer to the shared memory that the platform has |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1363 | kept aside to pass TF-A related information that next BL image needs. This |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1364 | function is invoked in BL2 to pass this information to the next BL |
| 1365 | image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1366 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1367 | Function : plat_get_stack_protector_canary() |
| 1368 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1369 | |
| 1370 | :: |
| 1371 | |
| 1372 | Argument : void |
| 1373 | Return : u_register_t |
| 1374 | |
| 1375 | This function returns a random value that is used to initialize the canary used |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1376 | when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1377 | value will weaken the protection as the attacker could easily write the right |
| 1378 | value as part of the attack most of the time. Therefore, it should return a |
| 1379 | true random number. |
| 1380 | |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 1381 | .. warning:: |
| 1382 | For the protection to be effective, the global data need to be placed at |
| 1383 | a lower address than the stack bases. Failure to do so would allow an |
| 1384 | attacker to overwrite the canary as part of the stack buffer overflow attack. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1385 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1386 | Function : plat_flush_next_bl_params() |
| 1387 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1388 | |
| 1389 | :: |
| 1390 | |
| 1391 | Argument : void |
| 1392 | Return : void |
| 1393 | |
| 1394 | This function flushes to main memory all the image params that are passed to |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1395 | next image. This function is invoked in BL2 to flush this information |
| 1396 | to the next BL image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1397 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1398 | Function : plat_log_get_prefix() |
| 1399 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Soby Mathew | aaf15f5 | 2017-09-04 11:49:29 +0100 | [diff] [blame] | 1400 | |
| 1401 | :: |
| 1402 | |
| 1403 | Argument : unsigned int |
| 1404 | Return : const char * |
| 1405 | |
| 1406 | This function defines the prefix string corresponding to the `log_level` to be |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1407 | prepended to all the log output from TF-A. The `log_level` (argument) will |
| 1408 | correspond to one of the standard log levels defined in debug.h. The platform |
| 1409 | can override the common implementation to define a different prefix string for |
John Tsichritzis | 30f8964 | 2018-06-07 16:31:34 +0100 | [diff] [blame] | 1410 | the log output. The implementation should be robust to future changes that |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1411 | increase the number of log levels. |
Soby Mathew | aaf15f5 | 2017-09-04 11:49:29 +0100 | [diff] [blame] | 1412 | |
Manish V Badarkhe | f809c6e | 2020-02-22 08:43:00 +0000 | [diff] [blame] | 1413 | Function : plat_get_soc_version() |
Manish V Badarkhe | 904f93a | 2020-03-26 14:20:27 +0000 | [diff] [blame] | 1414 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Manish V Badarkhe | f809c6e | 2020-02-22 08:43:00 +0000 | [diff] [blame] | 1415 | |
| 1416 | :: |
| 1417 | |
| 1418 | Argument : void |
| 1419 | Return : int32_t |
| 1420 | |
| 1421 | This function returns soc version which mainly consist of below fields |
| 1422 | |
| 1423 | :: |
| 1424 | |
| 1425 | soc_version[30:24] = JEP-106 continuation code for the SiP |
| 1426 | soc_version[23:16] = JEP-106 identification code with parity bit for the SiP |
Manish V Badarkhe | 80f13ee | 2020-07-23 20:23:01 +0100 | [diff] [blame] | 1427 | soc_version[15:0] = Implementation defined SoC ID |
Manish V Badarkhe | f809c6e | 2020-02-22 08:43:00 +0000 | [diff] [blame] | 1428 | |
| 1429 | Function : plat_get_soc_revision() |
Manish V Badarkhe | 904f93a | 2020-03-26 14:20:27 +0000 | [diff] [blame] | 1430 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Manish V Badarkhe | f809c6e | 2020-02-22 08:43:00 +0000 | [diff] [blame] | 1431 | |
| 1432 | :: |
| 1433 | |
| 1434 | Argument : void |
| 1435 | Return : int32_t |
| 1436 | |
| 1437 | This function returns soc revision in below format |
| 1438 | |
| 1439 | :: |
| 1440 | |
| 1441 | soc_revision[0:30] = SOC revision of specific SOC |
| 1442 | |
Manish V Badarkhe | 80f13ee | 2020-07-23 20:23:01 +0100 | [diff] [blame] | 1443 | Function : plat_is_smccc_feature_available() |
| 1444 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1445 | |
| 1446 | :: |
| 1447 | |
| 1448 | Argument : u_register_t |
| 1449 | Return : int32_t |
| 1450 | |
| 1451 | This function returns SMC_ARCH_CALL_SUCCESS if the platform supports |
| 1452 | the SMCCC function specified in the argument; otherwise returns |
| 1453 | SMC_ARCH_CALL_NOT_SUPPORTED. |
| 1454 | |
Manish V Badarkhe | bd617b9 | 2021-09-20 15:19:59 +0100 | [diff] [blame] | 1455 | Function : plat_mboot_measure_image() |
| 1456 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1457 | |
| 1458 | :: |
| 1459 | |
| 1460 | Argument : unsigned int, image_info_t * |
Manish V Badarkhe | 931c6ef | 2021-10-21 09:06:18 +0100 | [diff] [blame] | 1461 | Return : int |
Manish V Badarkhe | bd617b9 | 2021-09-20 15:19:59 +0100 | [diff] [blame] | 1462 | |
| 1463 | When the MEASURED_BOOT flag is enabled: |
| 1464 | |
| 1465 | - This function measures the given image and records its measurement using |
| 1466 | the measured boot backend driver. |
| 1467 | - On the Arm FVP port, this function measures the given image using its |
| 1468 | passed id and information and then records that measurement in the |
| 1469 | Event Log buffer. |
Manish V Badarkhe | 931c6ef | 2021-10-21 09:06:18 +0100 | [diff] [blame] | 1470 | - This function must return 0 on success, a signed integer error code |
| 1471 | otherwise. |
| 1472 | |
| 1473 | When the MEASURED_BOOT flag is disabled, this function doesn't do anything. |
| 1474 | |
| 1475 | Function : plat_mboot_measure_critical_data() |
| 1476 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1477 | |
| 1478 | :: |
| 1479 | |
| 1480 | Argument : unsigned int, const void *, size_t |
| 1481 | Return : int |
| 1482 | |
| 1483 | When the MEASURED_BOOT flag is enabled: |
| 1484 | |
| 1485 | - This function measures the given critical data structure and records its |
| 1486 | measurement using the measured boot backend driver. |
| 1487 | - This function must return 0 on success, a signed integer error code |
| 1488 | otherwise. |
Manish V Badarkhe | bd617b9 | 2021-09-20 15:19:59 +0100 | [diff] [blame] | 1489 | |
| 1490 | When the MEASURED_BOOT flag is disabled, this function doesn't do anything. |
| 1491 | |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 1492 | Function : plat_can_cmo() |
| 1493 | ~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1494 | |
| 1495 | :: |
| 1496 | |
| 1497 | Argument : void |
| 1498 | Return : uint64_t |
| 1499 | |
| 1500 | When CONDITIONAL_CMO flag is enabled: |
| 1501 | |
| 1502 | - This function indicates whether cache management operations should be |
| 1503 | performed. It returns 0 if CMOs should be skipped and non-zero |
| 1504 | otherwise. |
Okash Khawaja | 9453220 | 2022-11-14 12:50:30 +0000 | [diff] [blame] | 1505 | - The function must not clobber x1, x2 and x3. It's also not safe to rely on |
| 1506 | stack. Otherwise obey AAPCS. |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 1507 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1508 | Modifications specific to a Boot Loader stage |
| 1509 | --------------------------------------------- |
| 1510 | |
| 1511 | Boot Loader Stage 1 (BL1) |
| 1512 | ------------------------- |
| 1513 | |
| 1514 | BL1 implements the reset vector where execution starts from after a cold or |
| 1515 | warm boot. For each CPU, BL1 is responsible for the following tasks: |
| 1516 | |
| 1517 | #. Handling the reset as described in section 2.2 |
| 1518 | |
| 1519 | #. In the case of a cold boot and the CPU being the primary CPU, ensuring that |
| 1520 | only this CPU executes the remaining BL1 code, including loading and passing |
| 1521 | control to the BL2 stage. |
| 1522 | |
| 1523 | #. Identifying and starting the Firmware Update process (if required). |
| 1524 | |
| 1525 | #. Loading the BL2 image from non-volatile storage into secure memory at the |
| 1526 | address specified by the platform defined constant ``BL2_BASE``. |
| 1527 | |
| 1528 | #. Populating a ``meminfo`` structure with the following information in memory, |
| 1529 | accessible by BL2 immediately upon entry. |
| 1530 | |
| 1531 | :: |
| 1532 | |
| 1533 | meminfo.total_base = Base address of secure RAM visible to BL2 |
| 1534 | meminfo.total_size = Size of secure RAM visible to BL2 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1535 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1536 | By default, BL1 places this ``meminfo`` structure at the end of secure |
| 1537 | memory visible to BL2. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1538 | |
Soby Mathew | b1bf044 | 2018-02-16 14:52:52 +0000 | [diff] [blame] | 1539 | It is possible for the platform to decide where it wants to place the |
| 1540 | ``meminfo`` structure for BL2 or restrict the amount of memory visible to |
| 1541 | BL2 by overriding the weak default implementation of |
| 1542 | ``bl1_plat_handle_post_image_load`` API. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1543 | |
| 1544 | The following functions need to be implemented by the platform port to enable |
| 1545 | BL1 to perform the above tasks. |
| 1546 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1547 | Function : bl1_early_platform_setup() [mandatory] |
| 1548 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1549 | |
| 1550 | :: |
| 1551 | |
| 1552 | Argument : void |
| 1553 | Return : void |
| 1554 | |
| 1555 | This function executes with the MMU and data caches disabled. It is only called |
| 1556 | by the primary CPU. |
| 1557 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1558 | On Arm standard platforms, this function: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1559 | |
| 1560 | - Enables a secure instance of SP805 to act as the Trusted Watchdog. |
| 1561 | |
| 1562 | - Initializes a UART (PL011 console), which enables access to the ``printf`` |
| 1563 | family of functions in BL1. |
| 1564 | |
| 1565 | - Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to |
| 1566 | the CCI slave interface corresponding to the cluster that includes the |
| 1567 | primary CPU. |
| 1568 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1569 | Function : bl1_plat_arch_setup() [mandatory] |
| 1570 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1571 | |
| 1572 | :: |
| 1573 | |
| 1574 | Argument : void |
| 1575 | Return : void |
| 1576 | |
| 1577 | This function performs any platform-specific and architectural setup that the |
| 1578 | platform requires. Platform-specific setup might include configuration of |
| 1579 | memory controllers and the interconnect. |
| 1580 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1581 | In Arm standard platforms, this function enables the MMU. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1582 | |
| 1583 | This function helps fulfill requirement 2 above. |
| 1584 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1585 | Function : bl1_platform_setup() [mandatory] |
| 1586 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1587 | |
| 1588 | :: |
| 1589 | |
| 1590 | Argument : void |
| 1591 | Return : void |
| 1592 | |
| 1593 | This function executes with the MMU and data caches enabled. It is responsible |
| 1594 | for performing any remaining platform-specific setup that can occur after the |
| 1595 | MMU and data cache have been enabled. |
| 1596 | |
Roberto Vargas | 0cd866c | 2017-12-12 10:39:44 +0000 | [diff] [blame] | 1597 | if support for multiple boot sources is required, it initializes the boot |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1598 | sequence used by plat_try_next_boot_source(). |
Roberto Vargas | 0cd866c | 2017-12-12 10:39:44 +0000 | [diff] [blame] | 1599 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1600 | In Arm standard platforms, this function initializes the storage abstraction |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1601 | layer used to load the next bootloader image. |
| 1602 | |
| 1603 | This function helps fulfill requirement 4 above. |
| 1604 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1605 | Function : bl1_plat_sec_mem_layout() [mandatory] |
| 1606 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1607 | |
| 1608 | :: |
| 1609 | |
| 1610 | Argument : void |
| 1611 | Return : meminfo * |
| 1612 | |
| 1613 | This function should only be called on the cold boot path. It executes with the |
| 1614 | MMU and data caches enabled. The pointer returned by this function must point to |
| 1615 | a ``meminfo`` structure containing the extents and availability of secure RAM for |
| 1616 | the BL1 stage. |
| 1617 | |
| 1618 | :: |
| 1619 | |
| 1620 | meminfo.total_base = Base address of secure RAM visible to BL1 |
| 1621 | meminfo.total_size = Size of secure RAM visible to BL1 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1622 | |
| 1623 | This information is used by BL1 to load the BL2 image in secure RAM. BL1 also |
| 1624 | populates a similar structure to tell BL2 the extents of memory available for |
| 1625 | its own use. |
| 1626 | |
| 1627 | This function helps fulfill requirements 4 and 5 above. |
| 1628 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1629 | Function : bl1_plat_prepare_exit() [optional] |
| 1630 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1631 | |
| 1632 | :: |
| 1633 | |
| 1634 | Argument : entry_point_info_t * |
| 1635 | Return : void |
| 1636 | |
| 1637 | This function is called prior to exiting BL1 in response to the |
| 1638 | ``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform |
| 1639 | platform specific clean up or bookkeeping operations before transferring |
| 1640 | control to the next image. It receives the address of the ``entry_point_info_t`` |
| 1641 | structure passed from BL2. This function runs with MMU disabled. |
| 1642 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1643 | Function : bl1_plat_set_ep_info() [optional] |
| 1644 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1645 | |
| 1646 | :: |
| 1647 | |
| 1648 | Argument : unsigned int image_id, entry_point_info_t *ep_info |
| 1649 | Return : void |
| 1650 | |
| 1651 | This function allows platforms to override ``ep_info`` for the given ``image_id``. |
| 1652 | |
| 1653 | The default implementation just returns. |
| 1654 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1655 | Function : bl1_plat_get_next_image_id() [optional] |
| 1656 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1657 | |
| 1658 | :: |
| 1659 | |
| 1660 | Argument : void |
| 1661 | Return : unsigned int |
| 1662 | |
| 1663 | This and the following function must be overridden to enable the FWU feature. |
| 1664 | |
| 1665 | BL1 calls this function after platform setup to identify the next image to be |
| 1666 | loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds |
| 1667 | with the normal boot sequence, which loads and executes BL2. If the platform |
| 1668 | returns a different image id, BL1 assumes that Firmware Update is required. |
| 1669 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1670 | The default implementation always returns ``BL2_IMAGE_ID``. The Arm development |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1671 | platforms override this function to detect if firmware update is required, and |
| 1672 | if so, return the first image in the firmware update process. |
| 1673 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1674 | Function : bl1_plat_get_image_desc() [optional] |
| 1675 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1676 | |
| 1677 | :: |
| 1678 | |
| 1679 | Argument : unsigned int image_id |
| 1680 | Return : image_desc_t * |
| 1681 | |
| 1682 | BL1 calls this function to get the image descriptor information ``image_desc_t`` |
| 1683 | for the provided ``image_id`` from the platform. |
| 1684 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1685 | The default implementation always returns a common BL2 image descriptor. Arm |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1686 | standard platforms return an image descriptor corresponding to BL2 or one of |
| 1687 | the firmware update images defined in the Trusted Board Boot Requirements |
| 1688 | specification. |
| 1689 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1690 | Function : bl1_plat_handle_pre_image_load() [optional] |
| 1691 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1692 | |
| 1693 | :: |
| 1694 | |
Soby Mathew | 2f38ce3 | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 1695 | Argument : unsigned int image_id |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1696 | Return : int |
| 1697 | |
| 1698 | This function can be used by the platforms to update/use image information |
Soby Mathew | 2f38ce3 | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 1699 | corresponding to ``image_id``. This function is invoked in BL1, both in cold |
| 1700 | boot and FWU code path, before loading the image. |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1701 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1702 | Function : bl1_plat_handle_post_image_load() [optional] |
| 1703 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1704 | |
| 1705 | :: |
| 1706 | |
Soby Mathew | 2f38ce3 | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 1707 | Argument : unsigned int image_id |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1708 | Return : int |
| 1709 | |
| 1710 | This function can be used by the platforms to update/use image information |
Soby Mathew | 2f38ce3 | 2018-02-08 17:45:12 +0000 | [diff] [blame] | 1711 | corresponding to ``image_id``. This function is invoked in BL1, both in cold |
| 1712 | boot and FWU code path, after loading and authenticating the image. |
Masahiro Yamada | 43d20b3 | 2018-02-01 16:46:18 +0900 | [diff] [blame] | 1713 | |
Soby Mathew | b1bf044 | 2018-02-16 14:52:52 +0000 | [diff] [blame] | 1714 | The default weak implementation of this function calculates the amount of |
| 1715 | Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t`` |
| 1716 | structure at the beginning of this free memory and populates it. The address |
| 1717 | of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint |
| 1718 | information to BL2. |
| 1719 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1720 | Function : bl1_plat_fwu_done() [optional] |
| 1721 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1722 | |
| 1723 | :: |
| 1724 | |
| 1725 | Argument : unsigned int image_id, uintptr_t image_src, |
| 1726 | unsigned int image_size |
| 1727 | Return : void |
| 1728 | |
| 1729 | BL1 calls this function when the FWU process is complete. It must not return. |
| 1730 | The platform may override this function to take platform specific action, for |
| 1731 | example to initiate the normal boot flow. |
| 1732 | |
| 1733 | The default implementation spins forever. |
| 1734 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1735 | Function : bl1_plat_mem_check() [mandatory] |
| 1736 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1737 | |
| 1738 | :: |
| 1739 | |
| 1740 | Argument : uintptr_t mem_base, unsigned int mem_size, |
| 1741 | unsigned int flags |
| 1742 | Return : int |
| 1743 | |
| 1744 | BL1 calls this function while handling FWU related SMCs, more specifically when |
| 1745 | copying or authenticating an image. Its responsibility is to ensure that the |
| 1746 | region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and |
| 1747 | that this memory corresponds to either a secure or non-secure memory region as |
| 1748 | indicated by the security state of the ``flags`` argument. |
| 1749 | |
| 1750 | This function can safely assume that the value resulting from the addition of |
| 1751 | ``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not |
| 1752 | overflow. |
| 1753 | |
| 1754 | This function must return 0 on success, a non-null error code otherwise. |
| 1755 | |
| 1756 | The default implementation of this function asserts therefore platforms must |
| 1757 | override it when using the FWU feature. |
| 1758 | |
Manish V Badarkhe | bd617b9 | 2021-09-20 15:19:59 +0100 | [diff] [blame] | 1759 | Function : bl1_plat_mboot_init() [optional] |
| 1760 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1761 | |
| 1762 | :: |
| 1763 | |
| 1764 | Argument : void |
| 1765 | Return : void |
| 1766 | |
| 1767 | When the MEASURED_BOOT flag is enabled: |
| 1768 | |
| 1769 | - This function is used to initialize the backend driver(s) of measured boot. |
| 1770 | - On the Arm FVP port, this function is used to initialize the Event Log |
| 1771 | backend driver, and also to write header information in the Event Log buffer. |
| 1772 | |
| 1773 | When the MEASURED_BOOT flag is disabled, this function doesn't do anything. |
| 1774 | |
| 1775 | Function : bl1_plat_mboot_finish() [optional] |
| 1776 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1777 | |
| 1778 | :: |
| 1779 | |
| 1780 | Argument : void |
| 1781 | Return : void |
| 1782 | |
| 1783 | When the MEASURED_BOOT flag is enabled: |
| 1784 | |
| 1785 | - This function is used to finalize the measured boot backend driver(s), |
| 1786 | and also, set the information for the next bootloader component to |
| 1787 | extend the measurement if needed. |
| 1788 | - On the Arm FVP port, this function is used to pass the base address of |
| 1789 | the Event Log buffer and its size to BL2 via tb_fw_config to extend the |
| 1790 | Event Log buffer with the measurement of various images loaded by BL2. |
| 1791 | It results in panic on error. |
| 1792 | |
| 1793 | When the MEASURED_BOOT flag is disabled, this function doesn't do anything. |
| 1794 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1795 | Boot Loader Stage 2 (BL2) |
| 1796 | ------------------------- |
| 1797 | |
| 1798 | The BL2 stage is executed only by the primary CPU, which is determined in BL1 |
| 1799 | using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1800 | ``BL2_BASE``. BL2 executes in Secure EL1 and and invokes |
| 1801 | ``plat_get_bl_image_load_info()`` to retrieve the list of images to load from |
| 1802 | non-volatile storage to secure/non-secure RAM. After all the images are loaded |
| 1803 | then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable |
| 1804 | images to be passed to the next BL image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1805 | |
| 1806 | The following functions must be implemented by the platform port to enable BL2 |
| 1807 | to perform the above tasks. |
| 1808 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1809 | Function : bl2_early_platform_setup2() [mandatory] |
| 1810 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1811 | |
| 1812 | :: |
| 1813 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1814 | Argument : u_register_t, u_register_t, u_register_t, u_register_t |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1815 | Return : void |
| 1816 | |
| 1817 | This function executes with the MMU and data caches disabled. It is only called |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1818 | by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments |
| 1819 | are platform specific. |
| 1820 | |
| 1821 | On Arm standard platforms, the arguments received are : |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1822 | |
Manish V Badarkhe | 8141451 | 2020-06-24 15:58:38 +0100 | [diff] [blame] | 1823 | arg0 - Points to load address of FW_CONFIG |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1824 | |
| 1825 | arg1 - ``meminfo`` structure populated by BL1. The platform copies |
| 1826 | the contents of ``meminfo`` as it may be subsequently overwritten by BL2. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1827 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1828 | On Arm standard platforms, this function also: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1829 | |
| 1830 | - Initializes a UART (PL011 console), which enables access to the ``printf`` |
| 1831 | family of functions in BL2. |
| 1832 | |
| 1833 | - Initializes the storage abstraction layer used to load further bootloader |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1834 | images. It is necessary to do this early on platforms with a SCP_BL2 image, |
| 1835 | since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1836 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1837 | Function : bl2_plat_arch_setup() [mandatory] |
| 1838 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1839 | |
| 1840 | :: |
| 1841 | |
| 1842 | Argument : void |
| 1843 | Return : void |
| 1844 | |
| 1845 | This function executes with the MMU and data caches disabled. It is only called |
| 1846 | by the primary CPU. |
| 1847 | |
| 1848 | The purpose of this function is to perform any architectural initialization |
| 1849 | that varies across platforms. |
| 1850 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1851 | On Arm standard platforms, this function enables the MMU. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1852 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1853 | Function : bl2_platform_setup() [mandatory] |
| 1854 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1855 | |
| 1856 | :: |
| 1857 | |
| 1858 | Argument : void |
| 1859 | Return : void |
| 1860 | |
| 1861 | This function may execute with the MMU and data caches enabled if the platform |
| 1862 | port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only |
| 1863 | called by the primary CPU. |
| 1864 | |
| 1865 | The purpose of this function is to perform any platform initialization |
| 1866 | specific to BL2. |
| 1867 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1868 | In Arm standard platforms, this function performs security setup, including |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1869 | configuration of the TrustZone controller to allow non-secure masters access |
| 1870 | to most of DRAM. Part of DRAM is reserved for secure world use. |
| 1871 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1872 | Function : bl2_plat_handle_pre_image_load() [optional] |
| 1873 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1874 | |
| 1875 | :: |
| 1876 | |
| 1877 | Argument : unsigned int |
| 1878 | Return : int |
| 1879 | |
| 1880 | This function can be used by the platforms to update/use image information |
Masahiro Yamada | 02a0d3d | 2018-02-01 16:45:51 +0900 | [diff] [blame] | 1881 | for given ``image_id``. This function is currently invoked in BL2 before |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1882 | loading each image. |
Masahiro Yamada | 02a0d3d | 2018-02-01 16:45:51 +0900 | [diff] [blame] | 1883 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1884 | Function : bl2_plat_handle_post_image_load() [optional] |
| 1885 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Masahiro Yamada | 02a0d3d | 2018-02-01 16:45:51 +0900 | [diff] [blame] | 1886 | |
| 1887 | :: |
| 1888 | |
| 1889 | Argument : unsigned int |
| 1890 | Return : int |
| 1891 | |
| 1892 | This function can be used by the platforms to update/use image information |
| 1893 | for given ``image_id``. This function is currently invoked in BL2 after |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1894 | loading each image. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1895 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1896 | Function : bl2_plat_preload_setup [optional] |
| 1897 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1898 | |
| 1899 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 1900 | |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1901 | Argument : void |
| 1902 | Return : void |
| 1903 | |
| 1904 | This optional function performs any BL2 platform initialization |
| 1905 | required before image loading, that is not done later in |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1906 | bl2_platform_setup(). Specifically, if support for multiple |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1907 | boot sources is required, it initializes the boot sequence used by |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1908 | plat_try_next_boot_source(). |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1909 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1910 | Function : plat_try_next_boot_source() [optional] |
| 1911 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1912 | |
| 1913 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 1914 | |
Roberto Vargas | bc1ae1f | 2017-09-26 12:53:01 +0100 | [diff] [blame] | 1915 | Argument : void |
| 1916 | Return : int |
| 1917 | |
| 1918 | This optional function passes to the next boot source in the redundancy |
| 1919 | sequence. |
| 1920 | |
| 1921 | This function moves the current boot redundancy source to the next |
| 1922 | element in the boot sequence. If there are no more boot sources then it |
| 1923 | must return 0, otherwise it must return 1. The default implementation |
| 1924 | of this always returns 0. |
| 1925 | |
Sandrine Bailleux | eb5fadc | 2022-07-13 10:07:54 +0200 | [diff] [blame] | 1926 | Function : bl2_plat_mboot_init() [optional] |
| 1927 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1928 | |
| 1929 | :: |
| 1930 | |
| 1931 | Argument : void |
| 1932 | Return : void |
| 1933 | |
| 1934 | When the MEASURED_BOOT flag is enabled: |
| 1935 | |
| 1936 | - This function is used to initialize the backend driver(s) of measured boot. |
| 1937 | - On the Arm FVP port, this function is used to initialize the Event Log |
| 1938 | backend driver with the Event Log buffer information (base address and |
| 1939 | size) received from BL1. It results in panic on error. |
| 1940 | |
| 1941 | When the MEASURED_BOOT flag is disabled, this function doesn't do anything. |
| 1942 | |
| 1943 | Function : bl2_plat_mboot_finish() [optional] |
| 1944 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1945 | |
| 1946 | :: |
| 1947 | |
| 1948 | Argument : void |
| 1949 | Return : void |
| 1950 | |
| 1951 | When the MEASURED_BOOT flag is enabled: |
| 1952 | |
| 1953 | - This function is used to finalize the measured boot backend driver(s), |
| 1954 | and also, set the information for the next bootloader component to extend |
| 1955 | the measurement if needed. |
| 1956 | - On the Arm FVP port, this function is used to pass the Event Log buffer |
| 1957 | information (base address and size) to non-secure(BL33) and trusted OS(BL32) |
| 1958 | via nt_fw and tos_fw config respectively. It results in panic on error. |
| 1959 | |
| 1960 | When the MEASURED_BOOT flag is disabled, this function doesn't do anything. |
| 1961 | |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1962 | Boot Loader Stage 2 (BL2) at EL3 |
| 1963 | -------------------------------- |
| 1964 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1965 | When the platform has a non-TF-A Boot ROM it is desirable to jump |
| 1966 | directly to BL2 instead of TF-A BL1. In this case BL2 is expected to |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 1967 | execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design` |
| 1968 | document for more information. |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1969 | |
| 1970 | All mandatory functions of BL2 must be implemented, except the functions |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1971 | bl2_early_platform_setup and bl2_el3_plat_arch_setup, because |
| 1972 | their work is done now by bl2_el3_early_platform_setup and |
| 1973 | bl2_el3_plat_arch_setup. These functions should generally implement |
| 1974 | the bl1_plat_xxx() and bl2_plat_xxx() functionality combined. |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1975 | |
| 1976 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1977 | Function : bl2_el3_early_platform_setup() [mandatory] |
| 1978 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1979 | |
| 1980 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 1981 | |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1982 | Argument : u_register_t, u_register_t, u_register_t, u_register_t |
| 1983 | Return : void |
| 1984 | |
| 1985 | This function executes with the MMU and data caches disabled. It is only called |
| 1986 | by the primary CPU. This function receives four parameters which can be used |
| 1987 | by the platform to pass any needed information from the Boot ROM to BL2. |
| 1988 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1989 | On Arm standard platforms, this function does the following: |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1990 | |
| 1991 | - Initializes a UART (PL011 console), which enables access to the ``printf`` |
| 1992 | family of functions in BL2. |
| 1993 | |
| 1994 | - Initializes the storage abstraction layer used to load further bootloader |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 1995 | images. It is necessary to do this early on platforms with a SCP_BL2 image, |
| 1996 | since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded. |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 1997 | |
| 1998 | - Initializes the private variables that define the memory layout used. |
| 1999 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2000 | Function : bl2_el3_plat_arch_setup() [mandatory] |
| 2001 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 2002 | |
| 2003 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 2004 | |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 2005 | Argument : void |
| 2006 | Return : void |
| 2007 | |
| 2008 | This function executes with the MMU and data caches disabled. It is only called |
| 2009 | by the primary CPU. |
| 2010 | |
| 2011 | The purpose of this function is to perform any architectural initialization |
| 2012 | that varies across platforms. |
| 2013 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2014 | On Arm standard platforms, this function enables the MMU. |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 2015 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2016 | Function : bl2_el3_plat_prepare_exit() [optional] |
| 2017 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 2018 | |
| 2019 | :: |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 2020 | |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 2021 | Argument : void |
| 2022 | Return : void |
| 2023 | |
| 2024 | This function is called prior to exiting BL2 and run the next image. |
| 2025 | It should be used to perform platform specific clean up or bookkeeping |
| 2026 | operations before transferring control to the next image. This function |
| 2027 | runs with MMU disabled. |
| 2028 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2029 | FWU Boot Loader Stage 2 (BL2U) |
| 2030 | ------------------------------ |
| 2031 | |
| 2032 | The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU |
| 2033 | process and is executed only by the primary CPU. BL1 passes control to BL2U at |
| 2034 | ``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for: |
| 2035 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2036 | #. (Optional) Transferring the optional SCP_BL2U binary image from AP secure |
| 2037 | memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1. |
| 2038 | ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U |
| 2039 | should be copied from. Subsequent handling of the SCP_BL2U image is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2040 | implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function. |
| 2041 | If ``SCP_BL2U_BASE`` is not defined then this step is not performed. |
| 2042 | |
| 2043 | #. Any platform specific setup required to perform the FWU process. For |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2044 | example, Arm standard platforms initialize the TZC controller so that the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2045 | normal world can access DDR memory. |
| 2046 | |
| 2047 | The following functions must be implemented by the platform port to enable |
| 2048 | BL2U to perform the tasks mentioned above. |
| 2049 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2050 | Function : bl2u_early_platform_setup() [mandatory] |
| 2051 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2052 | |
| 2053 | :: |
| 2054 | |
| 2055 | Argument : meminfo *mem_info, void *plat_info |
| 2056 | Return : void |
| 2057 | |
| 2058 | This function executes with the MMU and data caches disabled. It is only |
| 2059 | called by the primary CPU. The arguments to this function is the address |
| 2060 | of the ``meminfo`` structure and platform specific info provided by BL1. |
| 2061 | |
| 2062 | The platform may copy the contents of the ``mem_info`` and ``plat_info`` into |
| 2063 | private storage as the original memory may be subsequently overwritten by BL2U. |
| 2064 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2065 | On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure, |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2066 | to extract SCP_BL2U image information, which is then copied into a private |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2067 | variable. |
| 2068 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2069 | Function : bl2u_plat_arch_setup() [mandatory] |
| 2070 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2071 | |
| 2072 | :: |
| 2073 | |
| 2074 | Argument : void |
| 2075 | Return : void |
| 2076 | |
| 2077 | This function executes with the MMU and data caches disabled. It is only |
| 2078 | called by the primary CPU. |
| 2079 | |
| 2080 | The purpose of this function is to perform any architectural initialization |
| 2081 | that varies across platforms, for example enabling the MMU (since the memory |
| 2082 | map differs across platforms). |
| 2083 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2084 | Function : bl2u_platform_setup() [mandatory] |
| 2085 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2086 | |
| 2087 | :: |
| 2088 | |
| 2089 | Argument : void |
| 2090 | Return : void |
| 2091 | |
| 2092 | This function may execute with the MMU and data caches enabled if the platform |
| 2093 | port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only |
| 2094 | called by the primary CPU. |
| 2095 | |
| 2096 | The purpose of this function is to perform any platform initialization |
| 2097 | specific to BL2U. |
| 2098 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2099 | In Arm standard platforms, this function performs security setup, including |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2100 | configuration of the TrustZone controller to allow non-secure masters access |
| 2101 | to most of DRAM. Part of DRAM is reserved for secure world use. |
| 2102 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2103 | Function : bl2u_plat_handle_scp_bl2u() [optional] |
| 2104 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2105 | |
| 2106 | :: |
| 2107 | |
| 2108 | Argument : void |
| 2109 | Return : int |
| 2110 | |
| 2111 | This function is used to perform any platform-specific actions required to |
| 2112 | handle the SCP firmware. Typically it transfers the image into SCP memory using |
| 2113 | a platform-specific protocol and waits until SCP executes it and signals to the |
| 2114 | Application Processor (AP) for BL2U execution to continue. |
| 2115 | |
| 2116 | This function returns 0 on success, a negative error code otherwise. |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2117 | This function is included if SCP_BL2U_BASE is defined. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2118 | |
| 2119 | Boot Loader Stage 3-1 (BL31) |
| 2120 | ---------------------------- |
| 2121 | |
| 2122 | During cold boot, the BL31 stage is executed only by the primary CPU. This is |
| 2123 | determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes |
| 2124 | control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all |
| 2125 | CPUs. BL31 executes at EL3 and is responsible for: |
| 2126 | |
| 2127 | #. Re-initializing all architectural and platform state. Although BL1 performs |
| 2128 | some of this initialization, BL31 remains resident in EL3 and must ensure |
| 2129 | that EL3 architectural and platform state is completely initialized. It |
| 2130 | should make no assumptions about the system state when it receives control. |
| 2131 | |
| 2132 | #. Passing control to a normal world BL image, pre-loaded at a platform- |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 2133 | specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list |
| 2134 | populated by BL2 in memory to do this. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2135 | |
| 2136 | #. Providing runtime firmware services. Currently, BL31 only implements a |
| 2137 | subset of the Power State Coordination Interface (PSCI) API as a runtime |
Boyan Karatotev | 907d38b | 2022-11-22 12:01:09 +0000 | [diff] [blame] | 2138 | service. See :ref:`psci_in_bl31` below for details of porting the PSCI |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2139 | implementation. |
| 2140 | |
| 2141 | #. Optionally passing control to the BL32 image, pre-loaded at a platform- |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 2142 | specific address by BL2. BL31 exports a set of APIs that allow runtime |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2143 | services to specify the security state in which the next image should be |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 2144 | executed and run the corresponding image. On ARM platforms, BL31 uses the |
| 2145 | ``bl_params`` list populated by BL2 in memory to do this. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2146 | |
| 2147 | If BL31 is a reset vector, It also needs to handle the reset as specified in |
| 2148 | section 2.2 before the tasks described above. |
| 2149 | |
| 2150 | The following functions must be implemented by the platform port to enable BL31 |
| 2151 | to perform the above tasks. |
| 2152 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2153 | Function : bl31_early_platform_setup2() [mandatory] |
| 2154 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2155 | |
| 2156 | :: |
| 2157 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 2158 | Argument : u_register_t, u_register_t, u_register_t, u_register_t |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2159 | Return : void |
| 2160 | |
| 2161 | This function executes with the MMU and data caches disabled. It is only called |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 2162 | by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are |
| 2163 | platform specific. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2164 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 2165 | In Arm standard platforms, the arguments received are : |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2166 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 2167 | arg0 - The pointer to the head of `bl_params_t` list |
| 2168 | which is list of executable images following BL31, |
| 2169 | |
| 2170 | arg1 - Points to load address of SOC_FW_CONFIG if present |
Mikael Olsson | 0232da2 | 2021-02-12 17:30:16 +0100 | [diff] [blame] | 2171 | except in case of Arm FVP and Juno platform. |
Manish V Badarkhe | 8141451 | 2020-06-24 15:58:38 +0100 | [diff] [blame] | 2172 | |
Mikael Olsson | 0232da2 | 2021-02-12 17:30:16 +0100 | [diff] [blame] | 2173 | In case of Arm FVP and Juno platform, points to load address |
Manish V Badarkhe | 8141451 | 2020-06-24 15:58:38 +0100 | [diff] [blame] | 2174 | of FW_CONFIG. |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 2175 | |
| 2176 | arg2 - Points to load address of HW_CONFIG if present |
| 2177 | |
| 2178 | arg3 - A special value to verify platform parameters from BL2 to BL31. Not |
| 2179 | used in release builds. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2180 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 2181 | The function runs through the `bl_param_t` list and extracts the entry point |
| 2182 | information for BL32 and BL33. It also performs the following: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2183 | |
| 2184 | - Initialize a UART (PL011 console), which enables access to the ``printf`` |
| 2185 | family of functions in BL31. |
| 2186 | |
| 2187 | - Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the |
| 2188 | CCI slave interface corresponding to the cluster that includes the primary |
| 2189 | CPU. |
| 2190 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2191 | Function : bl31_plat_arch_setup() [mandatory] |
| 2192 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2193 | |
| 2194 | :: |
| 2195 | |
| 2196 | Argument : void |
| 2197 | Return : void |
| 2198 | |
| 2199 | This function executes with the MMU and data caches disabled. It is only called |
| 2200 | by the primary CPU. |
| 2201 | |
| 2202 | The purpose of this function is to perform any architectural initialization |
| 2203 | that varies across platforms. |
| 2204 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2205 | On Arm standard platforms, this function enables the MMU. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2206 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2207 | Function : bl31_platform_setup() [mandatory] |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2208 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2209 | |
| 2210 | :: |
| 2211 | |
| 2212 | Argument : void |
| 2213 | Return : void |
| 2214 | |
| 2215 | This function may execute with the MMU and data caches enabled if the platform |
| 2216 | port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only |
| 2217 | called by the primary CPU. |
| 2218 | |
| 2219 | The purpose of this function is to complete platform initialization so that both |
| 2220 | BL31 runtime services and normal world software can function correctly. |
| 2221 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2222 | On Arm standard platforms, this function does the following: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2223 | |
| 2224 | - Initialize the generic interrupt controller. |
| 2225 | |
| 2226 | Depending on the GIC driver selected by the platform, the appropriate GICv2 |
| 2227 | or GICv3 initialization will be done, which mainly consists of: |
| 2228 | |
| 2229 | - Enable secure interrupts in the GIC CPU interface. |
| 2230 | - Disable the legacy interrupt bypass mechanism. |
| 2231 | - Configure the priority mask register to allow interrupts of all priorities |
| 2232 | to be signaled to the CPU interface. |
| 2233 | - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. |
| 2234 | - Target all secure SPIs to CPU0. |
| 2235 | - Enable these secure interrupts in the GIC distributor. |
| 2236 | - Configure all other interrupts as non-secure. |
| 2237 | - Enable signaling of secure interrupts in the GIC distributor. |
| 2238 | |
| 2239 | - Enable system-level implementation of the generic timer counter through the |
| 2240 | memory mapped interface. |
| 2241 | |
| 2242 | - Grant access to the system counter timer module |
| 2243 | |
| 2244 | - Initialize the power controller device. |
| 2245 | |
| 2246 | In particular, initialise the locks that prevent concurrent accesses to the |
| 2247 | power controller device. |
| 2248 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2249 | Function : bl31_plat_runtime_setup() [optional] |
| 2250 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2251 | |
| 2252 | :: |
| 2253 | |
| 2254 | Argument : void |
| 2255 | Return : void |
| 2256 | |
| 2257 | The purpose of this function is allow the platform to perform any BL31 runtime |
| 2258 | setup just prior to BL31 exit during cold boot. The default weak |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 2259 | implementation of this function will invoke ``console_switch_state()`` to switch |
| 2260 | console output to consoles marked for use in the ``runtime`` state. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2261 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2262 | Function : bl31_plat_get_next_image_ep_info() [mandatory] |
| 2263 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2264 | |
| 2265 | :: |
| 2266 | |
Sandrine Bailleux | 842117d | 2018-05-14 14:25:47 +0200 | [diff] [blame] | 2267 | Argument : uint32_t |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2268 | Return : entry_point_info * |
| 2269 | |
| 2270 | This function may execute with the MMU and data caches enabled if the platform |
| 2271 | port does the necessary initializations in ``bl31_plat_arch_setup()``. |
| 2272 | |
| 2273 | This function is called by ``bl31_main()`` to retrieve information provided by |
| 2274 | BL2 for the next image in the security state specified by the argument. BL31 |
| 2275 | uses this information to pass control to that image in the specified security |
| 2276 | state. This function must return a pointer to the ``entry_point_info`` structure |
| 2277 | (that was copied during ``bl31_early_platform_setup()``) if the image exists. It |
| 2278 | should return NULL otherwise. |
| 2279 | |
Javier Almansa Sobrino | 7176a77 | 2021-11-24 18:37:37 +0000 | [diff] [blame] | 2280 | Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1] |
Soby Mathew | 294e1cf | 2022-03-22 16:19:39 +0000 | [diff] [blame] | 2281 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2282 | |
| 2283 | :: |
| 2284 | |
| 2285 | Argument : uintptr_t, size_t *, uintptr_t, size_t |
| 2286 | Return : int |
| 2287 | |
| 2288 | This function returns the Platform attestation token. |
| 2289 | |
| 2290 | The parameters of the function are: |
| 2291 | |
| 2292 | arg0 - A pointer to the buffer where the Platform token should be copied by |
| 2293 | this function. The buffer must be big enough to hold the Platform |
| 2294 | token. |
| 2295 | |
| 2296 | arg1 - Contains the size (in bytes) of the buffer passed in arg0. The |
| 2297 | function returns the platform token length in this parameter. |
| 2298 | |
| 2299 | arg2 - A pointer to the buffer where the challenge object is stored. |
| 2300 | |
| 2301 | arg3 - The length of the challenge object in bytes. Possible values are 32, |
| 2302 | 48 and 64. |
| 2303 | |
| 2304 | The function returns 0 on success, -EINVAL on failure. |
| 2305 | |
Javier Almansa Sobrino | 7176a77 | 2021-11-24 18:37:37 +0000 | [diff] [blame] | 2306 | Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1] |
| 2307 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Soby Mathew | f05d93a | 2022-03-22 16:21:19 +0000 | [diff] [blame] | 2308 | |
| 2309 | :: |
| 2310 | |
| 2311 | Argument : uintptr_t, size_t *, unsigned int |
| 2312 | Return : int |
| 2313 | |
| 2314 | This function returns the delegated realm attestation key which will be used to |
| 2315 | sign Realm attestation token. The API currently only supports P-384 ECC curve |
| 2316 | key. |
| 2317 | |
| 2318 | The parameters of the function are: |
| 2319 | |
| 2320 | arg0 - A pointer to the buffer where the attestation key should be copied |
| 2321 | by this function. The buffer must be big enough to hold the |
| 2322 | attestation key. |
| 2323 | |
| 2324 | arg1 - Contains the size (in bytes) of the buffer passed in arg0. The |
| 2325 | function returns the attestation key length in this parameter. |
| 2326 | |
| 2327 | arg2 - The type of the elliptic curve to which the requested attestation key |
| 2328 | belongs. |
| 2329 | |
| 2330 | The function returns 0 on success, -EINVAL on failure. |
| 2331 | |
Javier Almansa Sobrino | 7176a77 | 2021-11-24 18:37:37 +0000 | [diff] [blame] | 2332 | Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1] |
| 2333 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2334 | |
| 2335 | :: |
| 2336 | |
| 2337 | Argument : uintptr_t * |
| 2338 | Return : size_t |
| 2339 | |
| 2340 | This function returns the size of the shared area between EL3 and RMM (or 0 on |
| 2341 | failure). A pointer to the shared area (or a NULL pointer on failure) is stored |
| 2342 | in the pointer passed as argument. |
| 2343 | |
Javier Almansa Sobrino | 4165e84 | 2022-04-25 17:18:15 +0100 | [diff] [blame] | 2344 | Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1] |
| 2345 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2346 | |
| 2347 | :: |
| 2348 | |
| 2349 | Arguments : rmm_manifest_t *manifest |
| 2350 | Return : int |
| 2351 | |
| 2352 | When ENABLE_RME is enabled, this function populates a boot manifest for the |
| 2353 | RMM image and stores it in the area specified by manifest. |
| 2354 | |
| 2355 | When ENABLE_RME is disabled, this function is not used. |
| 2356 | |
Jeenu Viswambharan | e834ee1 | 2018-04-27 15:17:03 +0100 | [diff] [blame] | 2357 | Function : bl31_plat_enable_mmu [optional] |
| 2358 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2359 | |
| 2360 | :: |
| 2361 | |
| 2362 | Argument : uint32_t |
| 2363 | Return : void |
| 2364 | |
| 2365 | This function enables the MMU. The boot code calls this function with MMU and |
| 2366 | caches disabled. This function should program necessary registers to enable |
| 2367 | translation, and upon return, the MMU on the calling PE must be enabled. |
| 2368 | |
| 2369 | The function must honor flags passed in the first argument. These flags are |
| 2370 | defined by the translation library, and can be found in the file |
| 2371 | ``include/lib/xlat_tables/xlat_mmu_helpers.h``. |
| 2372 | |
| 2373 | On DynamIQ systems, this function must not use stack while enabling MMU, which |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 2374 | is how the function in xlat table library version 2 is implemented. |
Jeenu Viswambharan | e834ee1 | 2018-04-27 15:17:03 +0100 | [diff] [blame] | 2375 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 2376 | Function : plat_init_apkey [optional] |
| 2377 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 2378 | |
| 2379 | :: |
| 2380 | |
| 2381 | Argument : void |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 2382 | Return : uint128_t |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 2383 | |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 2384 | This function returns the 128-bit value which can be used to program ARMv8.3 |
| 2385 | pointer authentication keys. |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 2386 | |
| 2387 | The value should be obtained from a reliable source of randomness. |
| 2388 | |
| 2389 | This function is only needed if ARMv8.3 pointer authentication is used in the |
Alexei Fedorov | f41355c | 2019-09-13 14:11:59 +0100 | [diff] [blame] | 2390 | Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero. |
Antonio Nino Diaz | 25cda67 | 2019-02-19 11:53:51 +0000 | [diff] [blame] | 2391 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2392 | Function : plat_get_syscnt_freq2() [mandatory] |
| 2393 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2394 | |
| 2395 | :: |
| 2396 | |
| 2397 | Argument : void |
| 2398 | Return : unsigned int |
| 2399 | |
| 2400 | This function is used by the architecture setup code to retrieve the counter |
| 2401 | frequency for the CPU's generic timer. This value will be programmed into the |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2402 | ``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2403 | of the system counter, which is retrieved from the first entry in the frequency |
| 2404 | modes table. |
| 2405 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2406 | #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] |
| 2407 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2408 | |
| 2409 | When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in |
| 2410 | bytes) aligned to the cache line boundary that should be allocated per-cpu to |
| 2411 | accommodate all the bakery locks. |
| 2412 | |
| 2413 | If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker |
Chris Kay | 33bfc5e | 2023-02-14 11:30:04 +0000 | [diff] [blame] | 2414 | calculates the size of the ``.bakery_lock`` input section, aligns it to the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2415 | nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT`` |
| 2416 | and stores the result in a linker symbol. This constant prevents a platform |
| 2417 | from relying on the linker and provide a more efficient mechanism for |
| 2418 | accessing per-cpu bakery lock information. |
| 2419 | |
| 2420 | If this constant is defined and its value is not equal to the value |
| 2421 | calculated by the linker then a link time assertion is raised. A compile time |
| 2422 | assertion is raised if the value of the constant is not aligned to the cache |
| 2423 | line boundary. |
| 2424 | |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2425 | .. _porting_guide_sdei_requirements: |
| 2426 | |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2427 | SDEI porting requirements |
| 2428 | ~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2429 | |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 2430 | The |SDEI| dispatcher requires the platform to provide the following macros |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2431 | and functions, of which some are optional, and some others mandatory. |
| 2432 | |
| 2433 | Macros |
| 2434 | ...... |
| 2435 | |
| 2436 | Macro: PLAT_SDEI_NORMAL_PRI [mandatory] |
| 2437 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 2438 | |
| 2439 | This macro must be defined to the EL3 exception priority level associated with |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 2440 | Normal |SDEI| events on the platform. This must have a higher value |
| 2441 | (therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2442 | |
| 2443 | Macro: PLAT_SDEI_CRITICAL_PRI [mandatory] |
| 2444 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 2445 | |
| 2446 | This macro must be defined to the EL3 exception priority level associated with |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 2447 | Critical |SDEI| events on the platform. This must have a lower value |
| 2448 | (therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2449 | |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 2450 | **Note**: |SDEI| exception priorities must be the lowest among Secure |
| 2451 | priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must |
| 2452 | be higher than Normal |SDEI| priority. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2453 | |
| 2454 | Functions |
| 2455 | ......... |
| 2456 | |
Sandrine Bailleux | 95db98b | 2020-05-15 12:05:51 +0200 | [diff] [blame] | 2457 | Function: int plat_sdei_validate_entry_point() [optional] |
| 2458 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2459 | |
| 2460 | :: |
| 2461 | |
Sandrine Bailleux | 95db98b | 2020-05-15 12:05:51 +0200 | [diff] [blame] | 2462 | Argument: uintptr_t ep, unsigned int client_mode |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2463 | Return: int |
| 2464 | |
Sandrine Bailleux | 95db98b | 2020-05-15 12:05:51 +0200 | [diff] [blame] | 2465 | This function validates the entry point address of the event handler provided by |
| 2466 | the client for both event registration and *Complete and Resume* |SDEI| calls. |
| 2467 | The function ensures that the address is valid in the client translation regime. |
| 2468 | |
| 2469 | The second argument is the exception level that the client is executing in. It |
| 2470 | can be Non-Secure EL1 or Non-Secure EL2. |
| 2471 | |
| 2472 | The function must return ``0`` for successful validation, or ``-1`` upon failure. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2473 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2474 | The default implementation always returns ``0``. On Arm platforms, this function |
Sandrine Bailleux | 95db98b | 2020-05-15 12:05:51 +0200 | [diff] [blame] | 2475 | translates the entry point address within the client translation regime and |
| 2476 | further ensures that the resulting physical address is located in Non-secure |
| 2477 | DRAM. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2478 | |
| 2479 | Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional] |
| 2480 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 2481 | |
| 2482 | :: |
| 2483 | |
| 2484 | Argument: uint64_t |
| 2485 | Argument: unsigned int |
| 2486 | Return: void |
| 2487 | |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 2488 | |SDEI| specification requires that a PE comes out of reset with the events |
| 2489 | masked. The client therefore is expected to call ``PE_UNMASK`` to unmask |
| 2490 | |SDEI| events on the PE. No |SDEI| events can be dispatched until such |
| 2491 | time. |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2492 | |
Paul Beesley | 606d807 | 2019-03-13 13:58:02 +0000 | [diff] [blame] | 2493 | Should a PE receive an interrupt that was bound to an |SDEI| event while the |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 2494 | events are masked on the PE, the dispatcher implementation invokes the function |
| 2495 | ``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the |
| 2496 | interrupt and the interrupt ID are passed as parameters. |
| 2497 | |
| 2498 | The default implementation only prints out a warning message. |
| 2499 | |
Jimmy Brisson | 26c5b5c | 2020-06-22 14:18:42 -0500 | [diff] [blame] | 2500 | .. _porting_guide_trng_requirements: |
| 2501 | |
| 2502 | TRNG porting requirements |
| 2503 | ~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2504 | |
| 2505 | The |TRNG| backend requires the platform to provide the following values |
| 2506 | and mandatory functions. |
| 2507 | |
| 2508 | Values |
| 2509 | ...... |
| 2510 | |
| 2511 | value: uuid_t plat_trng_uuid [mandatory] |
| 2512 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 2513 | |
| 2514 | This value must be defined to the UUID of the TRNG backend that is specific to |
Jayanth Dodderi Chidanand | 7c7faff | 2022-10-11 17:16:07 +0100 | [diff] [blame] | 2515 | the hardware after ``plat_entropy_setup`` function is called. This value must |
Jimmy Brisson | 26c5b5c | 2020-06-22 14:18:42 -0500 | [diff] [blame] | 2516 | conform to the SMCCC calling convention; The most significant 32 bits of the |
| 2517 | UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in |
| 2518 | w0 indicates failure to get a TRNG source. |
| 2519 | |
| 2520 | Functions |
| 2521 | ......... |
| 2522 | |
| 2523 | Function: void plat_entropy_setup(void) [mandatory] |
| 2524 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 2525 | |
| 2526 | :: |
| 2527 | |
| 2528 | Argument: none |
| 2529 | Return: none |
| 2530 | |
| 2531 | This function is expected to do platform-specific initialization of any TRNG |
| 2532 | hardware. This may include generating a UUID from a hardware-specific seed. |
| 2533 | |
| 2534 | Function: bool plat_get_entropy(uint64_t \*out) [mandatory] |
| 2535 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 2536 | |
| 2537 | :: |
| 2538 | |
| 2539 | Argument: uint64_t * |
| 2540 | Return: bool |
| 2541 | Out : when the return value is true, the entropy has been written into the |
| 2542 | storage pointed to |
| 2543 | |
| 2544 | This function writes entropy into storage provided by the caller. If no entropy |
| 2545 | is available, it must return false and the storage must not be written. |
| 2546 | |
Boyan Karatotev | 907d38b | 2022-11-22 12:01:09 +0000 | [diff] [blame] | 2547 | .. _psci_in_bl31: |
| 2548 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2549 | Power State Coordination Interface (in BL31) |
| 2550 | -------------------------------------------- |
| 2551 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2552 | The TF-A implementation of the PSCI API is based around the concept of a |
| 2553 | *power domain*. A *power domain* is a CPU or a logical group of CPUs which |
| 2554 | share some state on which power management operations can be performed as |
| 2555 | specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is |
| 2556 | a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The |
| 2557 | *power domains* are arranged in a hierarchical tree structure and each |
| 2558 | *power domain* can be identified in a system by the cpu index of any CPU that |
| 2559 | is part of that domain and a *power domain level*. A processing element (for |
| 2560 | example, a CPU) is at level 0. If the *power domain* node above a CPU is a |
| 2561 | logical grouping of CPUs that share some state, then level 1 is that group of |
| 2562 | CPUs (for example, a cluster), and level 2 is a group of clusters (for |
| 2563 | example, the system). More details on the power domain topology and its |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2564 | organization can be found in :ref:`PSCI Power Domain Tree Structure`. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2565 | |
| 2566 | BL31's platform initialization code exports a pointer to the platform-specific |
| 2567 | power management operations required for the PSCI implementation to function |
| 2568 | correctly. This information is populated in the ``plat_psci_ops`` structure. The |
| 2569 | PSCI implementation calls members of the ``plat_psci_ops`` structure for performing |
| 2570 | power management operations on the power domains. For example, the target |
| 2571 | CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()`` |
| 2572 | handler (if present) is called for the CPU power domain. |
| 2573 | |
| 2574 | The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to |
| 2575 | describe composite power states specific to a platform. The PSCI implementation |
Antonio Nino Diaz | 56b68ad | 2019-02-28 13:35:21 +0000 | [diff] [blame] | 2576 | defines a generic representation of the power-state parameter, which is an |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2577 | array of local power states where each index corresponds to a power domain |
| 2578 | level. Each entry contains the local power state the power domain at that power |
| 2579 | level could enter. It depends on the ``validate_power_state()`` handler to |
| 2580 | convert the power-state parameter (possibly encoding a composite power state) |
| 2581 | passed in a PSCI ``CPU_SUSPEND`` call to this representation. |
| 2582 | |
| 2583 | The following functions form part of platform port of PSCI functionality. |
| 2584 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2585 | Function : plat_psci_stat_accounting_start() [optional] |
| 2586 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2587 | |
| 2588 | :: |
| 2589 | |
| 2590 | Argument : const psci_power_state_t * |
| 2591 | Return : void |
| 2592 | |
| 2593 | This is an optional hook that platforms can implement for residency statistics |
| 2594 | accounting before entering a low power state. The ``pwr_domain_state`` field of |
| 2595 | ``state_info`` (first argument) can be inspected if stat accounting is done |
| 2596 | differently at CPU level versus higher levels. As an example, if the element at |
| 2597 | index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down |
| 2598 | state, special hardware logic may be programmed in order to keep track of the |
| 2599 | residency statistics. For higher levels (array indices > 0), the residency |
| 2600 | statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the |
| 2601 | default implementation will use PMF to capture timestamps. |
| 2602 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2603 | Function : plat_psci_stat_accounting_stop() [optional] |
| 2604 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2605 | |
| 2606 | :: |
| 2607 | |
| 2608 | Argument : const psci_power_state_t * |
| 2609 | Return : void |
| 2610 | |
| 2611 | This is an optional hook that platforms can implement for residency statistics |
| 2612 | accounting after exiting from a low power state. The ``pwr_domain_state`` field |
| 2613 | of ``state_info`` (first argument) can be inspected if stat accounting is done |
| 2614 | differently at CPU level versus higher levels. As an example, if the element at |
| 2615 | index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down |
| 2616 | state, special hardware logic may be programmed in order to keep track of the |
| 2617 | residency statistics. For higher levels (array indices > 0), the residency |
| 2618 | statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the |
| 2619 | default implementation will use PMF to capture timestamps. |
| 2620 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2621 | Function : plat_psci_stat_get_residency() [optional] |
| 2622 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2623 | |
| 2624 | :: |
| 2625 | |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 2626 | Argument : unsigned int, const psci_power_state_t *, unsigned int |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2627 | Return : u_register_t |
| 2628 | |
| 2629 | This is an optional interface that is is invoked after resuming from a low power |
| 2630 | state and provides the time spent resident in that low power state by the power |
| 2631 | domain at a particular power domain level. When a CPU wakes up from suspend, |
| 2632 | all its parent power domain levels are also woken up. The generic PSCI code |
| 2633 | invokes this function for each parent power domain that is resumed and it |
| 2634 | identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second |
| 2635 | argument) describes the low power state that the power domain has resumed from. |
| 2636 | The current CPU is the first CPU in the power domain to resume from the low |
| 2637 | power state and the ``last_cpu_idx`` (third parameter) is the index of the last |
| 2638 | CPU in the power domain to suspend and may be needed to calculate the residency |
| 2639 | for that power domain. |
| 2640 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2641 | Function : plat_get_target_pwr_state() [optional] |
| 2642 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2643 | |
| 2644 | :: |
| 2645 | |
| 2646 | Argument : unsigned int, const plat_local_state_t *, unsigned int |
| 2647 | Return : plat_local_state_t |
| 2648 | |
| 2649 | The PSCI generic code uses this function to let the platform participate in |
| 2650 | state coordination during a power management operation. The function is passed |
| 2651 | a pointer to an array of platform specific local power state ``states`` (second |
| 2652 | argument) which contains the requested power state for each CPU at a particular |
| 2653 | power domain level ``lvl`` (first argument) within the power domain. The function |
| 2654 | is expected to traverse this array of upto ``ncpus`` (third argument) and return |
| 2655 | a coordinated target power state by the comparing all the requested power |
| 2656 | states. The target power state should not be deeper than any of the requested |
| 2657 | power states. |
| 2658 | |
| 2659 | A weak definition of this API is provided by default wherein it assumes |
| 2660 | that the platform assigns a local state value in order of increasing depth |
| 2661 | of the power state i.e. for two power states X & Y, if X < Y |
| 2662 | then X represents a shallower power state than Y. As a result, the |
| 2663 | coordinated target local power state for a power domain will be the minimum |
| 2664 | of the requested local power state values. |
| 2665 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2666 | Function : plat_get_power_domain_tree_desc() [mandatory] |
| 2667 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2668 | |
| 2669 | :: |
| 2670 | |
| 2671 | Argument : void |
| 2672 | Return : const unsigned char * |
| 2673 | |
| 2674 | This function returns a pointer to the byte array containing the power domain |
| 2675 | topology tree description. The format and method to construct this array are |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2676 | described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI |
| 2677 | initialization code requires this array to be described by the platform, either |
| 2678 | statically or dynamically, to initialize the power domain topology tree. In case |
| 2679 | the array is populated dynamically, then plat_core_pos_by_mpidr() and |
| 2680 | plat_my_core_pos() should also be implemented suitably so that the topology tree |
| 2681 | description matches the CPU indices returned by these APIs. These APIs together |
| 2682 | form the platform interface for the PSCI topology framework. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2683 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2684 | Function : plat_setup_psci_ops() [mandatory] |
| 2685 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2686 | |
| 2687 | :: |
| 2688 | |
| 2689 | Argument : uintptr_t, const plat_psci_ops ** |
| 2690 | Return : int |
| 2691 | |
| 2692 | This function may execute with the MMU and data caches enabled if the platform |
| 2693 | port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only |
| 2694 | called by the primary CPU. |
| 2695 | |
| 2696 | This function is called by PSCI initialization code. Its purpose is to let |
| 2697 | the platform layer know about the warm boot entrypoint through the |
| 2698 | ``sec_entrypoint`` (first argument) and to export handler routines for |
| 2699 | platform-specific psci power management actions by populating the passed |
| 2700 | pointer with a pointer to BL31's private ``plat_psci_ops`` structure. |
| 2701 | |
| 2702 | A description of each member of this structure is given below. Please refer to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2703 | the Arm FVP specific implementation of these handlers in |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2704 | ``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2705 | platform wants to support, the associated operation or operations in this |
| 2706 | structure must be provided and implemented (Refer section 4 of |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2707 | :ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2708 | function in a platform port, the operation should be removed from this |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2709 | structure instead of providing an empty implementation. |
| 2710 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2711 | plat_psci_ops.cpu_standby() |
| 2712 | ........................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2713 | |
| 2714 | Perform the platform-specific actions to enter the standby state for a cpu |
| 2715 | indicated by the passed argument. This provides a fast path for CPU standby |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 2716 | wherein overheads of PSCI state management and lock acquisition is avoided. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2717 | For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation, |
| 2718 | the suspend state type specified in the ``power-state`` parameter should be |
| 2719 | STANDBY and the target power domain level specified should be the CPU. The |
| 2720 | handler should put the CPU into a low power retention state (usually by |
| 2721 | issuing a wfi instruction) and ensure that it can be woken up from that |
| 2722 | state by a normal interrupt. The generic code expects the handler to succeed. |
| 2723 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2724 | plat_psci_ops.pwr_domain_on() |
| 2725 | ............................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2726 | |
| 2727 | Perform the platform specific actions to power on a CPU, specified |
| 2728 | by the ``MPIDR`` (first argument). The generic code expects the platform to |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2729 | return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2730 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2731 | plat_psci_ops.pwr_domain_off() |
| 2732 | .............................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2733 | |
| 2734 | Perform the platform specific actions to prepare to power off the calling CPU |
| 2735 | and its higher parent power domain levels as indicated by the ``target_state`` |
| 2736 | (first argument). It is called by the PSCI ``CPU_OFF`` API implementation. |
| 2737 | |
| 2738 | The ``target_state`` encodes the platform coordinated target local power states |
| 2739 | for the CPU power domain and its parent power domain levels. The handler |
| 2740 | needs to perform power management operation corresponding to the local state |
| 2741 | at each power level. |
| 2742 | |
| 2743 | For this handler, the local power state for the CPU power domain will be a |
| 2744 | power down state where as it could be either power down, retention or run state |
| 2745 | for the higher power domain levels depending on the result of state |
| 2746 | coordination. The generic code expects the handler to succeed. |
| 2747 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2748 | plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional] |
| 2749 | ........................................................... |
Varun Wadekar | ae87f4b | 2017-07-10 16:02:05 -0700 | [diff] [blame] | 2750 | |
| 2751 | This optional function may be used as a performance optimization to replace |
| 2752 | or complement pwr_domain_suspend() on some platforms. Its calling semantics |
| 2753 | are identical to pwr_domain_suspend(), except the PSCI implementation only |
| 2754 | calls this function when suspending to a power down state, and it guarantees |
| 2755 | that data caches are enabled. |
| 2756 | |
| 2757 | When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches |
| 2758 | before calling pwr_domain_suspend(). If the target_state corresponds to a |
| 2759 | power down state and it is safe to perform some or all of the platform |
| 2760 | specific actions in that function with data caches enabled, it may be more |
| 2761 | efficient to move those actions to this function. When HW_ASSISTED_COHERENCY |
| 2762 | = 1, data caches remain enabled throughout, and so there is no advantage to |
| 2763 | moving platform specific actions to this function. |
| 2764 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2765 | plat_psci_ops.pwr_domain_suspend() |
| 2766 | .................................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2767 | |
| 2768 | Perform the platform specific actions to prepare to suspend the calling |
| 2769 | CPU and its higher parent power domain levels as indicated by the |
| 2770 | ``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND`` |
| 2771 | API implementation. |
| 2772 | |
| 2773 | The ``target_state`` has a similar meaning as described in |
| 2774 | the ``pwr_domain_off()`` operation. It encodes the platform coordinated |
| 2775 | target local power states for the CPU power domain and its parent |
| 2776 | power domain levels. The handler needs to perform power management operation |
| 2777 | corresponding to the local state at each power level. The generic code |
| 2778 | expects the handler to succeed. |
| 2779 | |
Douglas Raillard | a84996b | 2017-08-02 16:57:32 +0100 | [diff] [blame] | 2780 | The difference between turning a power domain off versus suspending it is that |
| 2781 | in the former case, the power domain is expected to re-initialize its state |
| 2782 | when it is next powered on (see ``pwr_domain_on_finish()``). In the latter |
| 2783 | case, the power domain is expected to save enough state so that it can resume |
| 2784 | execution by restoring this state when its powered on (see |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2785 | ``pwr_domain_suspend_finish()``). |
| 2786 | |
Douglas Raillard | a84996b | 2017-08-02 16:57:32 +0100 | [diff] [blame] | 2787 | When suspending a core, the platform can also choose to power off the GICv3 |
| 2788 | Redistributor and ITS through an implementation-defined sequence. To achieve |
| 2789 | this safely, the ITS context must be saved first. The architectural part is |
| 2790 | implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed |
| 2791 | sequence is implementation defined and it is therefore the responsibility of |
| 2792 | the platform code to implement the necessary sequence. Then the GIC |
| 2793 | Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper. |
| 2794 | Powering off the Redistributor requires the implementation to support it and it |
| 2795 | is the responsibility of the platform code to execute the right implementation |
| 2796 | defined sequence. |
| 2797 | |
| 2798 | When a system suspend is requested, the platform can also make use of the |
| 2799 | ``gicv3_distif_save()`` helper to save the context of the GIC Distributor after |
| 2800 | it has saved the context of the Redistributors and ITS of all the cores in the |
| 2801 | system. The context of the Distributor can be large and may require it to be |
| 2802 | allocated in a special area if it cannot fit in the platform's global static |
| 2803 | data, for example in DRAM. The Distributor can then be powered down using an |
| 2804 | implementation-defined sequence. |
| 2805 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2806 | plat_psci_ops.pwr_domain_pwr_down_wfi() |
| 2807 | ....................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2808 | |
| 2809 | This is an optional function and, if implemented, is expected to perform |
| 2810 | platform specific actions including the ``wfi`` invocation which allows the |
| 2811 | CPU to powerdown. Since this function is invoked outside the PSCI locks, |
| 2812 | the actions performed in this hook must be local to the CPU or the platform |
| 2813 | must ensure that races between multiple CPUs cannot occur. |
| 2814 | |
| 2815 | The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()`` |
| 2816 | operation and it encodes the platform coordinated target local power states for |
| 2817 | the CPU power domain and its parent power domain levels. This function must |
Boyan Karatotev | 43771f3 | 2022-10-05 13:41:56 +0100 | [diff] [blame] | 2818 | not return back to the caller (by calling wfi in an infinite loop to ensure |
| 2819 | some CPUs power down mitigations work properly). |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2820 | |
| 2821 | If this function is not implemented by the platform, PSCI generic |
| 2822 | implementation invokes ``psci_power_down_wfi()`` for power down. |
| 2823 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2824 | plat_psci_ops.pwr_domain_on_finish() |
| 2825 | .................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2826 | |
| 2827 | This function is called by the PSCI implementation after the calling CPU is |
| 2828 | powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call. |
| 2829 | It performs the platform-specific setup required to initialize enough state for |
| 2830 | this CPU to enter the normal world and also provide secure runtime firmware |
| 2831 | services. |
| 2832 | |
| 2833 | The ``target_state`` (first argument) is the prior state of the power domains |
| 2834 | immediately before the CPU was turned on. It indicates which power domains |
| 2835 | above the CPU might require initialization due to having previously been in |
| 2836 | low power states. The generic code expects the handler to succeed. |
| 2837 | |
Madhukar Pappireddy | 33bd514 | 2019-08-12 18:31:33 -0500 | [diff] [blame] | 2838 | plat_psci_ops.pwr_domain_on_finish_late() [optional] |
| 2839 | ........................................................... |
| 2840 | |
| 2841 | This optional function is called by the PSCI implementation after the calling |
| 2842 | CPU is fully powered on with respective data caches enabled. The calling CPU and |
| 2843 | the associated cluster are guaranteed to be participating in coherency. This |
| 2844 | function gives the flexibility to perform any platform-specific actions safely, |
| 2845 | such as initialization or modification of shared data structures, without the |
| 2846 | overhead of explicit cache maintainace operations. |
| 2847 | |
| 2848 | The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()`` |
| 2849 | operation. The generic code expects the handler to succeed. |
| 2850 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2851 | plat_psci_ops.pwr_domain_suspend_finish() |
| 2852 | ......................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2853 | |
| 2854 | This function is called by the PSCI implementation after the calling CPU is |
| 2855 | powered on and released from reset in response to an asynchronous wakeup |
| 2856 | event, for example a timer interrupt that was programmed by the CPU during the |
| 2857 | ``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific |
| 2858 | setup required to restore the saved state for this CPU to resume execution |
| 2859 | in the normal world and also provide secure runtime firmware services. |
| 2860 | |
| 2861 | The ``target_state`` (first argument) has a similar meaning as described in |
| 2862 | the ``pwr_domain_on_finish()`` operation. The generic code expects the platform |
| 2863 | to succeed. |
| 2864 | |
Douglas Raillard | a84996b | 2017-08-02 16:57:32 +0100 | [diff] [blame] | 2865 | If the Distributor, Redistributors or ITS have been powered off as part of a |
| 2866 | suspend, their context must be restored in this function in the reverse order |
| 2867 | to how they were saved during suspend sequence. |
| 2868 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2869 | plat_psci_ops.system_off() |
| 2870 | .......................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2871 | |
| 2872 | This function is called by PSCI implementation in response to a ``SYSTEM_OFF`` |
| 2873 | call. It performs the platform-specific system poweroff sequence after |
| 2874 | notifying the Secure Payload Dispatcher. |
| 2875 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2876 | plat_psci_ops.system_reset() |
| 2877 | ............................ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2878 | |
| 2879 | This function is called by PSCI implementation in response to a ``SYSTEM_RESET`` |
| 2880 | call. It performs the platform-specific system reset sequence after |
| 2881 | notifying the Secure Payload Dispatcher. |
| 2882 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2883 | plat_psci_ops.validate_power_state() |
| 2884 | .................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2885 | |
| 2886 | This function is called by the PSCI implementation during the ``CPU_SUSPEND`` |
| 2887 | call to validate the ``power_state`` parameter of the PSCI API and if valid, |
| 2888 | populate it in ``req_state`` (second argument) array as power domain level |
| 2889 | specific local states. If the ``power_state`` is invalid, the platform must |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2890 | return PSCI_E_INVALID_PARAMS as error, which is propagated back to the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2891 | normal world PSCI client. |
| 2892 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2893 | plat_psci_ops.validate_ns_entrypoint() |
| 2894 | ...................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2895 | |
| 2896 | This function is called by the PSCI implementation during the ``CPU_SUSPEND``, |
| 2897 | ``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point`` |
| 2898 | parameter passed by the normal world. If the ``entry_point`` is invalid, |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2899 | the platform must return PSCI_E_INVALID_ADDRESS as error, which is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2900 | propagated back to the normal world PSCI client. |
| 2901 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2902 | plat_psci_ops.get_sys_suspend_power_state() |
| 2903 | ........................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2904 | |
| 2905 | This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND`` |
| 2906 | call to get the ``req_state`` parameter from platform which encodes the power |
| 2907 | domain level specific local states to suspend to system affinity level. The |
| 2908 | ``req_state`` will be utilized to do the PSCI state coordination and |
| 2909 | ``pwr_domain_suspend()`` will be invoked with the coordinated target state to |
| 2910 | enter system suspend. |
| 2911 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2912 | plat_psci_ops.get_pwr_lvl_state_idx() |
| 2913 | ..................................... |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2914 | |
| 2915 | This is an optional function and, if implemented, is invoked by the PSCI |
| 2916 | implementation to convert the ``local_state`` (first argument) at a specified |
| 2917 | ``pwr_lvl`` (second argument) to an index between 0 and |
| 2918 | ``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform |
| 2919 | supports more than two local power states at each power domain level, that is |
| 2920 | ``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these |
| 2921 | local power states. |
| 2922 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2923 | plat_psci_ops.translate_power_state_by_mpidr() |
| 2924 | .............................................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2925 | |
| 2926 | This is an optional function and, if implemented, verifies the ``power_state`` |
| 2927 | (second argument) parameter of the PSCI API corresponding to a target power |
| 2928 | domain. The target power domain is identified by using both ``MPIDR`` (first |
| 2929 | argument) and the power domain level encoded in ``power_state``. The power domain |
| 2930 | level specific local states are to be extracted from ``power_state`` and be |
| 2931 | populated in the ``output_state`` (third argument) array. The functionality |
| 2932 | is similar to the ``validate_power_state`` function described above and is |
| 2933 | envisaged to be used in case the validity of ``power_state`` depend on the |
| 2934 | targeted power domain. If the ``power_state`` is invalid for the targeted power |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2935 | domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2936 | function is not implemented, then the generic implementation relies on |
| 2937 | ``validate_power_state`` function to translate the ``power_state``. |
| 2938 | |
| 2939 | This function can also be used in case the platform wants to support local |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2940 | power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2941 | APIs as described in Section 5.18 of `PSCI`_. |
| 2942 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2943 | plat_psci_ops.get_node_hw_state() |
| 2944 | ................................. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2945 | |
| 2946 | This is an optional function. If implemented this function is intended to return |
| 2947 | the power state of a node (identified by the first parameter, the ``MPIDR``) in |
| 2948 | the power domain topology (identified by the second parameter, ``power_level``), |
| 2949 | as retrieved from a power controller or equivalent component on the platform. |
| 2950 | Upon successful completion, the implementation must map and return the final |
| 2951 | status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it |
| 2952 | must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as |
| 2953 | appropriate. |
| 2954 | |
| 2955 | Implementations are not expected to handle ``power_levels`` greater than |
| 2956 | ``PLAT_MAX_PWR_LVL``. |
| 2957 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2958 | plat_psci_ops.system_reset2() |
| 2959 | ............................. |
Roberto Vargas | d963e3e | 2017-09-12 10:28:35 +0100 | [diff] [blame] | 2960 | |
| 2961 | This is an optional function. If implemented this function is |
| 2962 | called during the ``SYSTEM_RESET2`` call to perform a reset |
| 2963 | based on the first parameter ``reset_type`` as specified in |
| 2964 | `PSCI`_. The parameter ``cookie`` can be used to pass additional |
| 2965 | reset information. If the ``reset_type`` is not supported, the |
| 2966 | function must return ``PSCI_E_NOT_SUPPORTED``. For architectural |
| 2967 | resets, all failures must return ``PSCI_E_INVALID_PARAMETERS`` |
| 2968 | and vendor reset can return other PSCI error codes as defined |
| 2969 | in `PSCI`_. On success this function will not return. |
| 2970 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2971 | plat_psci_ops.write_mem_protect() |
| 2972 | ................................. |
Roberto Vargas | d963e3e | 2017-09-12 10:28:35 +0100 | [diff] [blame] | 2973 | |
| 2974 | This is an optional function. If implemented it enables or disables the |
| 2975 | ``MEM_PROTECT`` functionality based on the value of ``val``. |
| 2976 | A non-zero value enables ``MEM_PROTECT`` and a value of zero |
| 2977 | disables it. Upon encountering failures it must return a negative value |
| 2978 | and on success it must return 0. |
| 2979 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2980 | plat_psci_ops.read_mem_protect() |
| 2981 | ................................ |
Roberto Vargas | d963e3e | 2017-09-12 10:28:35 +0100 | [diff] [blame] | 2982 | |
| 2983 | This is an optional function. If implemented it returns the current |
| 2984 | state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering |
| 2985 | failures it must return a negative value and on success it must |
| 2986 | return 0. |
| 2987 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 2988 | plat_psci_ops.mem_protect_chk() |
| 2989 | ............................... |
Roberto Vargas | d963e3e | 2017-09-12 10:28:35 +0100 | [diff] [blame] | 2990 | |
| 2991 | This is an optional function. If implemented it checks if a memory |
| 2992 | region defined by a base address ``base`` and with a size of ``length`` |
| 2993 | bytes is protected by ``MEM_PROTECT``. If the region is protected |
| 2994 | then it must return 0, otherwise it must return a negative number. |
| 2995 | |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 2996 | .. _porting_guide_imf_in_bl31: |
| 2997 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2998 | Interrupt Management framework (in BL31) |
| 2999 | ---------------------------------------- |
| 3000 | |
| 3001 | BL31 implements an Interrupt Management Framework (IMF) to manage interrupts |
| 3002 | generated in either security state and targeted to EL1 or EL2 in the non-secure |
| 3003 | state or EL3/S-EL1 in the secure state. The design of this framework is |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 3004 | described in the :ref:`Interrupt Management Framework` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3005 | |
| 3006 | A platform should export the following APIs to support the IMF. The following |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 3007 | text briefly describes each API and its implementation in Arm standard |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3008 | platforms. The API implementation depends upon the type of interrupt controller |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3009 | present in the platform. Arm standard platform layer supports both |
| 3010 | `Arm Generic Interrupt Controller version 2.0 (GICv2)`_ |
| 3011 | and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the |
| 3012 | FVP can be configured to use either GICv2 or GICv3 depending on the build flag |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 3013 | ``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more |
| 3014 | details). |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3015 | |
Madhukar Pappireddy | 86350ae | 2020-07-29 09:37:25 -0500 | [diff] [blame] | 3016 | See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`. |
Jeenu Viswambharan | b1e957e | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 3017 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3018 | Function : plat_interrupt_type_to_line() [mandatory] |
| 3019 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3020 | |
| 3021 | :: |
| 3022 | |
| 3023 | Argument : uint32_t, uint32_t |
| 3024 | Return : uint32_t |
| 3025 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3026 | The Arm processor signals an interrupt exception either through the IRQ or FIQ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3027 | interrupt line. The specific line that is signaled depends on how the interrupt |
| 3028 | controller (IC) reports different interrupt types from an execution context in |
| 3029 | either security state. The IMF uses this API to determine which interrupt line |
| 3030 | the platform IC uses to signal each type of interrupt supported by the framework |
| 3031 | from a given security state. This API must be invoked at EL3. |
| 3032 | |
| 3033 | The first parameter will be one of the ``INTR_TYPE_*`` values (see |
Paul Beesley | f864067 | 2019-04-12 14:19:42 +0100 | [diff] [blame] | 3034 | :ref:`Interrupt Management Framework`) indicating the target type of the |
| 3035 | interrupt, the second parameter is the security state of the originating |
| 3036 | execution context. The return result is the bit position in the ``SCR_EL3`` |
| 3037 | register of the respective interrupt trap: IRQ=1, FIQ=2. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3038 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3039 | In the case of Arm standard platforms using GICv2, S-EL1 interrupts are |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3040 | configured as FIQs and Non-secure interrupts as IRQs from either security |
| 3041 | state. |
| 3042 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3043 | In the case of Arm standard platforms using GICv3, the interrupt line to be |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3044 | configured depends on the security state of the execution context when the |
| 3045 | interrupt is signalled and are as follows: |
| 3046 | |
| 3047 | - The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in |
| 3048 | NS-EL0/1/2 context. |
| 3049 | - The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ |
| 3050 | in the NS-EL0/1/2 context. |
| 3051 | - The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 |
| 3052 | context. |
| 3053 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3054 | Function : plat_ic_get_pending_interrupt_type() [mandatory] |
| 3055 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3056 | |
| 3057 | :: |
| 3058 | |
| 3059 | Argument : void |
| 3060 | Return : uint32_t |
| 3061 | |
| 3062 | This API returns the type of the highest priority pending interrupt at the |
| 3063 | platform IC. The IMF uses the interrupt type to retrieve the corresponding |
| 3064 | handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt |
| 3065 | pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``, |
| 3066 | ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3. |
| 3067 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3068 | In the case of Arm standard platforms using GICv2, the *Highest Priority |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3069 | Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of |
| 3070 | the pending interrupt. The type of interrupt depends upon the id value as |
| 3071 | follows. |
| 3072 | |
| 3073 | #. id < 1022 is reported as a S-EL1 interrupt |
| 3074 | #. id = 1022 is reported as a Non-secure interrupt. |
| 3075 | #. id = 1023 is reported as an invalid interrupt type. |
| 3076 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3077 | In the case of Arm standard platforms using GICv3, the system register |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3078 | ``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*, |
| 3079 | is read to determine the id of the pending interrupt. The type of interrupt |
| 3080 | depends upon the id value as follows. |
| 3081 | |
| 3082 | #. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt |
| 3083 | #. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt. |
| 3084 | #. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type. |
| 3085 | #. All other interrupt id's are reported as EL3 interrupt. |
| 3086 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3087 | Function : plat_ic_get_pending_interrupt_id() [mandatory] |
| 3088 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3089 | |
| 3090 | :: |
| 3091 | |
| 3092 | Argument : void |
| 3093 | Return : uint32_t |
| 3094 | |
| 3095 | This API returns the id of the highest priority pending interrupt at the |
| 3096 | platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt |
| 3097 | pending. |
| 3098 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3099 | In the case of Arm standard platforms using GICv2, the *Highest Priority |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3100 | Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the |
| 3101 | pending interrupt. The id that is returned by API depends upon the value of |
| 3102 | the id read from the interrupt controller as follows. |
| 3103 | |
| 3104 | #. id < 1022. id is returned as is. |
| 3105 | #. id = 1022. The *Aliased Highest Priority Pending Interrupt Register* |
| 3106 | (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt. |
| 3107 | This id is returned by the API. |
| 3108 | #. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned. |
| 3109 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3110 | In the case of Arm standard platforms using GICv3, if the API is invoked from |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3111 | EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt |
| 3112 | group 0 Register*, is read to determine the id of the pending interrupt. The id |
| 3113 | that is returned by API depends upon the value of the id read from the |
| 3114 | interrupt controller as follows. |
| 3115 | |
| 3116 | #. id < ``PENDING_G1S_INTID`` (1020). id is returned as is. |
| 3117 | #. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system |
| 3118 | register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1 |
| 3119 | Register* is read to determine the id of the group 1 interrupt. This id |
| 3120 | is returned by the API as long as it is a valid interrupt id |
| 3121 | #. If the id is any of the special interrupt identifiers, |
| 3122 | ``INTR_ID_UNAVAILABLE`` is returned. |
| 3123 | |
| 3124 | When the API invoked from S-EL1 for GICv3 systems, the id read from system |
| 3125 | register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3126 | Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3127 | ``INTR_ID_UNAVAILABLE`` is returned. |
| 3128 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3129 | Function : plat_ic_acknowledge_interrupt() [mandatory] |
| 3130 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3131 | |
| 3132 | :: |
| 3133 | |
| 3134 | Argument : void |
| 3135 | Return : uint32_t |
| 3136 | |
| 3137 | This API is used by the CPU to indicate to the platform IC that processing of |
Jeenu Viswambharan | 055af4b | 2017-10-24 15:13:59 +0100 | [diff] [blame] | 3138 | the highest pending interrupt has begun. It should return the raw, unmodified |
| 3139 | value obtained from the interrupt controller when acknowledging an interrupt. |
| 3140 | The actual interrupt number shall be extracted from this raw value using the API |
Madhukar Pappireddy | 86350ae | 2020-07-29 09:37:25 -0500 | [diff] [blame] | 3141 | `plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3142 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3143 | This function in Arm standard platforms using GICv2, reads the *Interrupt |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3144 | Acknowledge Register* (``GICC_IAR``). This changes the state of the highest |
| 3145 | priority pending interrupt from pending to active in the interrupt controller. |
Jeenu Viswambharan | 055af4b | 2017-10-24 15:13:59 +0100 | [diff] [blame] | 3146 | It returns the value read from the ``GICC_IAR``, unmodified. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3147 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3148 | In the case of Arm standard platforms using GICv3, if the API is invoked |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3149 | from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt |
| 3150 | Acknowledge Register group 0*. If the API is invoked from S-EL1, the function |
| 3151 | reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register |
| 3152 | group 1*. The read changes the state of the highest pending interrupt from |
| 3153 | pending to active in the interrupt controller. The value read is returned |
Jeenu Viswambharan | 055af4b | 2017-10-24 15:13:59 +0100 | [diff] [blame] | 3154 | unmodified. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3155 | |
| 3156 | The TSP uses this API to start processing of the secure physical timer |
| 3157 | interrupt. |
| 3158 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3159 | Function : plat_ic_end_of_interrupt() [mandatory] |
| 3160 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3161 | |
| 3162 | :: |
| 3163 | |
| 3164 | Argument : uint32_t |
| 3165 | Return : void |
| 3166 | |
| 3167 | This API is used by the CPU to indicate to the platform IC that processing of |
| 3168 | the interrupt corresponding to the id (passed as the parameter) has |
| 3169 | finished. The id should be the same as the id returned by the |
| 3170 | ``plat_ic_acknowledge_interrupt()`` API. |
| 3171 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3172 | Arm standard platforms write the id to the *End of Interrupt Register* |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3173 | (``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1`` |
| 3174 | system register in case of GICv3 depending on where the API is invoked from, |
| 3175 | EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt |
| 3176 | controller. |
| 3177 | |
| 3178 | The TSP uses this API to finish processing of the secure physical timer |
| 3179 | interrupt. |
| 3180 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3181 | Function : plat_ic_get_interrupt_type() [mandatory] |
| 3182 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3183 | |
| 3184 | :: |
| 3185 | |
| 3186 | Argument : uint32_t |
| 3187 | Return : uint32_t |
| 3188 | |
| 3189 | This API returns the type of the interrupt id passed as the parameter. |
| 3190 | ``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid |
| 3191 | interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is |
| 3192 | returned depending upon how the interrupt has been configured by the platform |
| 3193 | IC. This API must be invoked at EL3. |
| 3194 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3195 | Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3196 | and Non-secure interrupts as Group1 interrupts. It reads the group value |
| 3197 | corresponding to the interrupt id from the relevant *Interrupt Group Register* |
| 3198 | (``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt. |
| 3199 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3200 | In the case of Arm standard platforms using GICv3, both the *Interrupt Group |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3201 | Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register* |
| 3202 | (``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured |
| 3203 | as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. |
| 3204 | |
Manish Pandey | 3161fa5 | 2022-11-02 16:30:09 +0000 | [diff] [blame] | 3205 | Common helper functions |
| 3206 | ----------------------- |
Govindraj Raja | b6709b0 | 2023-02-21 17:43:55 +0000 | [diff] [blame] | 3207 | Function : elx_panic() |
| 3208 | ~~~~~~~~~~~~~~~~~~~~~~ |
Manish Pandey | 3161fa5 | 2022-11-02 16:30:09 +0000 | [diff] [blame] | 3209 | |
Govindraj Raja | b6709b0 | 2023-02-21 17:43:55 +0000 | [diff] [blame] | 3210 | :: |
| 3211 | |
| 3212 | Argument : void |
| 3213 | Return : void |
| 3214 | |
| 3215 | This API is called from assembly files when reporting a critical failure |
| 3216 | that has occured in lower EL and is been trapped in EL3. This call |
| 3217 | **must not** return. |
Manish Pandey | 3161fa5 | 2022-11-02 16:30:09 +0000 | [diff] [blame] | 3218 | |
Govindraj Raja | a796b1b | 2023-01-16 17:35:07 +0000 | [diff] [blame] | 3219 | Function : el3_panic() |
| 3220 | ~~~~~~~~~~~~~~~~~~~~~~ |
Manish Pandey | 3161fa5 | 2022-11-02 16:30:09 +0000 | [diff] [blame] | 3221 | |
| 3222 | :: |
| 3223 | |
| 3224 | Argument : void |
| 3225 | Return : void |
| 3226 | |
| 3227 | This API is called from assembly files when encountering a critical failure that |
Govindraj Raja | a796b1b | 2023-01-16 17:35:07 +0000 | [diff] [blame] | 3228 | cannot be recovered from. This function assumes that it is invoked from a C |
| 3229 | runtime environment i.e. valid stack exists. This call **must not** return. |
Manish Pandey | 3161fa5 | 2022-11-02 16:30:09 +0000 | [diff] [blame] | 3230 | |
| 3231 | Function : panic() |
| 3232 | ~~~~~~~~~~~~~~~~~~ |
| 3233 | |
| 3234 | :: |
| 3235 | |
| 3236 | Argument : void |
| 3237 | Return : void |
| 3238 | |
| 3239 | This API called from C files when encountering a critical failure that cannot |
| 3240 | be recovered from. This function in turn prints backtrace (if enabled) and calls |
Govindraj Raja | a796b1b | 2023-01-16 17:35:07 +0000 | [diff] [blame] | 3241 | el3_panic(). This call **must not** return. |
Manish Pandey | 3161fa5 | 2022-11-02 16:30:09 +0000 | [diff] [blame] | 3242 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3243 | Crash Reporting mechanism (in BL31) |
| 3244 | ----------------------------------- |
| 3245 | |
| 3246 | BL31 implements a crash reporting mechanism which prints the various registers |
Antonio Nino Diaz | 4bac045 | 2018-10-16 14:32:34 +0100 | [diff] [blame] | 3247 | of the CPU to enable quick crash analysis and debugging. This mechanism relies |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 3248 | on the platform implementing ``plat_crash_console_init``, |
Antonio Nino Diaz | 4bac045 | 2018-10-16 14:32:34 +0100 | [diff] [blame] | 3249 | ``plat_crash_console_putc`` and ``plat_crash_console_flush``. |
| 3250 | |
| 3251 | The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample |
| 3252 | implementation of all of them. Platforms may include this file to their |
| 3253 | makefiles in order to benefit from them. By default, they will cause the crash |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 3254 | output to be routed over the normal console infrastructure and get printed on |
| 3255 | consoles configured to output in crash state. ``console_set_scope()`` can be |
| 3256 | used to control whether a console is used for crash output. |
Paul Beesley | ba3ed40 | 2019-03-13 16:20:44 +0000 | [diff] [blame] | 3257 | |
| 3258 | .. note:: |
| 3259 | Platforms are responsible for making sure that they only mark consoles for |
| 3260 | use in the crash scope that are able to support this, i.e. that are written |
| 3261 | in assembly and conform with the register clobber rules for putc() |
| 3262 | (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3263 | |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 3264 | In some cases (such as debugging very early crashes that happen before the |
| 3265 | normal boot console can be set up), platforms may want to control crash output |
Julius Werner | 1338c9c | 2018-11-19 14:25:55 -0800 | [diff] [blame] | 3266 | more explicitly. These platforms may instead provide custom implementations for |
| 3267 | these. They are executed outside of a C environment and without a stack. Many |
| 3268 | console drivers provide functions named ``console_xxx_core_init/putc/flush`` |
| 3269 | that are designed to be used by these functions. See Arm platforms (like juno) |
| 3270 | for an example of this. |
Antonio Nino Diaz | 4bac045 | 2018-10-16 14:32:34 +0100 | [diff] [blame] | 3271 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3272 | Function : plat_crash_console_init [mandatory] |
| 3273 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3274 | |
| 3275 | :: |
| 3276 | |
| 3277 | Argument : void |
| 3278 | Return : int |
| 3279 | |
| 3280 | This API is used by the crash reporting mechanism to initialize the crash |
Julius Werner | aae9bb1 | 2017-09-18 16:49:48 -0700 | [diff] [blame] | 3281 | console. It must only use the general purpose registers x0 through x7 to do the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3282 | initialization and returns 1 on success. |
| 3283 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3284 | Function : plat_crash_console_putc [mandatory] |
| 3285 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3286 | |
| 3287 | :: |
| 3288 | |
| 3289 | Argument : int |
| 3290 | Return : int |
| 3291 | |
| 3292 | This API is used by the crash reporting mechanism to print a character on the |
| 3293 | designated crash console. It must only use general purpose registers x1 and |
| 3294 | x2 to do its work. The parameter and the return value are in general purpose |
| 3295 | register x0. |
| 3296 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3297 | Function : plat_crash_console_flush [mandatory] |
| 3298 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3299 | |
| 3300 | :: |
| 3301 | |
| 3302 | Argument : void |
Jimmy Brisson | 39f9eee | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 3303 | Return : void |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3304 | |
| 3305 | This API is used by the crash reporting mechanism to force write of all buffered |
| 3306 | data on the designated crash console. It should only use general purpose |
Jimmy Brisson | 39f9eee | 2020-08-05 13:44:05 -0500 | [diff] [blame] | 3307 | registers x0 through x5 to do its work. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3308 | |
Manish Pandey | 9c9f38a | 2020-06-30 00:46:08 +0100 | [diff] [blame] | 3309 | .. _External Abort handling and RAS Support: |
| 3310 | |
Jeenu Viswambharan | e34bf58 | 2018-10-12 08:48:36 +0100 | [diff] [blame] | 3311 | External Abort handling and RAS Support |
| 3312 | --------------------------------------- |
Jeenu Viswambharan | bf235bc | 2018-07-12 10:00:01 +0100 | [diff] [blame] | 3313 | |
| 3314 | Function : plat_ea_handler |
| 3315 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 3316 | |
| 3317 | :: |
| 3318 | |
| 3319 | Argument : int |
| 3320 | Argument : uint64_t |
| 3321 | Argument : void * |
| 3322 | Argument : void * |
| 3323 | Argument : uint64_t |
| 3324 | Return : void |
| 3325 | |
| 3326 | This function is invoked by the RAS framework for the platform to handle an |
| 3327 | External Abort received at EL3. The intention of the function is to attempt to |
| 3328 | resolve the cause of External Abort and return; if that's not possible, to |
| 3329 | initiate orderly shutdown of the system. |
| 3330 | |
| 3331 | The first parameter (``int ea_reason``) indicates the reason for External Abort. |
| 3332 | Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``. |
| 3333 | |
| 3334 | The second parameter (``uint64_t syndrome``) is the respective syndrome |
| 3335 | presented to EL3 after having received the External Abort. Depending on the |
| 3336 | nature of the abort (as can be inferred from the ``ea_reason`` parameter), this |
| 3337 | can be the content of either ``ESR_EL3`` or ``DISR_EL1``. |
| 3338 | |
| 3339 | The third parameter (``void *cookie``) is unused for now. The fourth parameter |
| 3340 | (``void *handle``) is a pointer to the preempted context. The fifth parameter |
| 3341 | (``uint64_t flags``) indicates the preempted security state. These parameters |
| 3342 | are received from the top-level exception handler. |
| 3343 | |
| 3344 | If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this |
| 3345 | function iterates through RAS handlers registered by the platform. If any of the |
| 3346 | RAS handlers resolve the External Abort, no further action is taken. |
| 3347 | |
| 3348 | If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers |
| 3349 | could resolve the External Abort, the default implementation prints an error |
| 3350 | message, and panics. |
| 3351 | |
| 3352 | Function : plat_handle_uncontainable_ea |
| 3353 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 3354 | |
| 3355 | :: |
| 3356 | |
| 3357 | Argument : int |
| 3358 | Argument : uint64_t |
| 3359 | Return : void |
| 3360 | |
| 3361 | This function is invoked by the RAS framework when an External Abort of |
| 3362 | Uncontainable type is received at EL3. Due to the critical nature of |
| 3363 | Uncontainable errors, the intention of this function is to initiate orderly |
| 3364 | shutdown of the system, and is not expected to return. |
| 3365 | |
| 3366 | This function must be implemented in assembly. |
| 3367 | |
| 3368 | The first and second parameters are the same as that of ``plat_ea_handler``. |
| 3369 | |
| 3370 | The default implementation of this function calls |
| 3371 | ``report_unhandled_exception``. |
| 3372 | |
| 3373 | Function : plat_handle_double_fault |
| 3374 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 3375 | |
| 3376 | :: |
| 3377 | |
| 3378 | Argument : int |
| 3379 | Argument : uint64_t |
| 3380 | Return : void |
| 3381 | |
| 3382 | This function is invoked by the RAS framework when another External Abort is |
| 3383 | received at EL3 while one is already being handled. I.e., a call to |
| 3384 | ``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of |
| 3385 | this function is to initiate orderly shutdown of the system, and is not expected |
| 3386 | recover or return. |
| 3387 | |
| 3388 | This function must be implemented in assembly. |
| 3389 | |
| 3390 | The first and second parameters are the same as that of ``plat_ea_handler``. |
| 3391 | |
| 3392 | The default implementation of this function calls |
| 3393 | ``report_unhandled_exception``. |
| 3394 | |
| 3395 | Function : plat_handle_el3_ea |
| 3396 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 3397 | |
| 3398 | :: |
| 3399 | |
| 3400 | Return : void |
| 3401 | |
| 3402 | This function is invoked when an External Abort is received while executing in |
| 3403 | EL3. Due to its critical nature, the intention of this function is to initiate |
| 3404 | orderly shutdown of the system, and is not expected recover or return. |
| 3405 | |
| 3406 | This function must be implemented in assembly. |
| 3407 | |
| 3408 | The default implementation of this function calls |
| 3409 | ``report_unhandled_exception``. |
| 3410 | |
Andre Przywara | bdc76f1 | 2022-11-21 17:07:25 +0000 | [diff] [blame] | 3411 | Function : plat_handle_rng_trap |
| 3412 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 3413 | |
| 3414 | :: |
| 3415 | |
| 3416 | Argument : uint64_t |
| 3417 | Argument : cpu_context_t * |
| 3418 | Return : int |
| 3419 | |
| 3420 | This function is invoked by BL31's exception handler when there is a synchronous |
| 3421 | system register trap caused by access to the RNDR or RNDRRS registers. It allows |
| 3422 | platforms implementing ``FEAT_RNG_TRAP`` and enabling ``ENABLE_FEAT_RNG_TRAP`` to |
| 3423 | emulate those system registers by returing back some entropy to the lower EL. |
| 3424 | |
| 3425 | The first parameter (``uint64_t esr_el3``) contains the content of the ESR_EL3 |
| 3426 | syndrome register, which encodes the instruction that was trapped. The interesting |
| 3427 | information in there is the target register (``get_sysreg_iss_rt()``). |
| 3428 | |
| 3429 | The second parameter (``cpu_context_t *ctx``) represents the CPU state in the |
| 3430 | lower exception level, at the time when the execution of the ``mrs`` instruction |
| 3431 | was trapped. Its content can be changed, to put the entropy into the target |
| 3432 | register. |
| 3433 | |
| 3434 | The return value indicates how to proceed: |
| 3435 | |
| 3436 | - When returning ``TRAP_RET_UNHANDLED`` (-1), the machine will panic. |
| 3437 | - When returning ``TRAP_RET_REPEAT`` (0), the exception handler will return |
| 3438 | to the same instruction, so its execution will be repeated. |
| 3439 | - When returning ``TRAP_RET_CONTINUE`` (1), the exception handler will return |
| 3440 | to the next instruction. |
| 3441 | |
| 3442 | This function needs to be implemented by a platform if it enables FEAT_RNG_TRAP. |
| 3443 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3444 | Build flags |
| 3445 | ----------- |
| 3446 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3447 | There are some build flags which can be defined by the platform to control |
| 3448 | inclusion or exclusion of certain BL stages from the FIP image. These flags |
| 3449 | need to be defined in the platform makefile which will get included by the |
| 3450 | build system. |
| 3451 | |
Sandrine Bailleux | 8d1a055 | 2019-02-08 14:44:53 +0100 | [diff] [blame] | 3452 | - **NEED_BL33** |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3453 | By default, this flag is defined ``yes`` by the build system and ``BL33`` |
| 3454 | build option should be supplied as a build option. The platform has the |
| 3455 | option of excluding the BL33 image in the ``fip`` image by defining this flag |
| 3456 | to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE`` |
| 3457 | are used, this flag will be set to ``no`` automatically. |
| 3458 | |
Paul Beesley | 07f0a31 | 2019-05-16 13:33:18 +0100 | [diff] [blame] | 3459 | Platform include paths |
| 3460 | ---------------------- |
| 3461 | |
| 3462 | Platforms are allowed to add more include paths to be passed to the compiler. |
| 3463 | The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in |
| 3464 | particular for the file ``platform_def.h``. |
| 3465 | |
| 3466 | Example: |
| 3467 | |
| 3468 | .. code:: c |
| 3469 | |
| 3470 | PLAT_INCLUDES += -Iinclude/plat/myplat/include |
| 3471 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3472 | C Library |
| 3473 | --------- |
| 3474 | |
| 3475 | To avoid subtle toolchain behavioral dependencies, the header files provided |
| 3476 | by the compiler are not used. The software is built with the ``-nostdinc`` flag |
| 3477 | to ensure no headers are included from the toolchain inadvertently. Instead the |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3478 | required headers are included in the TF-A source tree. The library only |
| 3479 | contains those C library definitions required by the local implementation. If |
| 3480 | more functionality is required, the needed library functions will need to be |
| 3481 | added to the local implementation. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3482 | |
Antonio Nino Diaz | cf0f805 | 2018-08-17 10:45:47 +0100 | [diff] [blame] | 3483 | Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have |
Paul Beesley | f2ec714 | 2019-10-04 16:17:46 +0000 | [diff] [blame] | 3484 | been written specifically for TF-A. Some implementation files have been obtained |
Antonio Nino Diaz | cf0f805 | 2018-08-17 10:45:47 +0100 | [diff] [blame] | 3485 | from `FreeBSD`_, others have been written specifically for TF-A as well. The |
| 3486 | files can be found in ``include/lib/libc`` and ``lib/libc``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3487 | |
Sandrine Bailleux | 6f0ecd7 | 2019-02-08 14:46:42 +0100 | [diff] [blame] | 3488 | SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources |
| 3489 | can be obtained from http://github.com/freebsd/freebsd. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3490 | |
| 3491 | Storage abstraction layer |
| 3492 | ------------------------- |
| 3493 | |
Louis Mayencourt | b546900 | 2019-07-15 13:56:03 +0100 | [diff] [blame] | 3494 | In order to improve platform independence and portability a storage abstraction |
| 3495 | layer is used to load data from non-volatile platform storage. Currently |
| 3496 | storage access is only required by BL1 and BL2 phases and performed inside the |
| 3497 | ``load_image()`` function in ``bl_common.c``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3498 | |
Louis Mayencourt | b546900 | 2019-07-15 13:56:03 +0100 | [diff] [blame] | 3499 | .. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3500 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3501 | It is mandatory to implement at least one storage driver. For the Arm |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3502 | development platforms the Firmware Image Package (FIP) driver is provided as |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 3503 | the default means to load data from storage (see :ref:`firmware_design_fip`). |
| 3504 | The storage layer is described in the header file |
| 3505 | ``include/drivers/io/io_storage.h``. The implementation of the common library is |
| 3506 | in ``drivers/io/io_storage.c`` and the driver files are located in |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3507 | ``drivers/io/``. |
| 3508 | |
Louis Mayencourt | b546900 | 2019-07-15 13:56:03 +0100 | [diff] [blame] | 3509 | .. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml |
| 3510 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3511 | Each IO driver must provide ``io_dev_*`` structures, as described in |
| 3512 | ``drivers/io/io_driver.h``. These are returned via a mandatory registration |
| 3513 | function that is called on platform initialization. The semi-hosting driver |
| 3514 | implementation in ``io_semihosting.c`` can be used as an example. |
| 3515 | |
Louis Mayencourt | b546900 | 2019-07-15 13:56:03 +0100 | [diff] [blame] | 3516 | Each platform should register devices and their drivers via the storage |
| 3517 | abstraction layer. These drivers then need to be initialized by bootloader |
| 3518 | phases as required in their respective ``blx_platform_setup()`` functions. |
| 3519 | |
| 3520 | .. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml |
| 3521 | |
| 3522 | The storage abstraction layer provides mechanisms (``io_dev_init()``) to |
| 3523 | initialize storage devices before IO operations are called. |
| 3524 | |
| 3525 | .. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml |
| 3526 | |
| 3527 | The basic operations supported by the layer |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3528 | include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``. |
| 3529 | Drivers do not have to implement all operations, but each platform must |
| 3530 | provide at least one driver for a device capable of supporting generic |
| 3531 | operations such as loading a bootloader image. |
| 3532 | |
| 3533 | The current implementation only allows for known images to be loaded by the |
| 3534 | firmware. These images are specified by using their identifiers, as defined in |
Antonio Nino Diaz | 645feb4 | 2019-02-13 14:07:38 +0000 | [diff] [blame] | 3535 | ``include/plat/common/common_def.h`` (or a separate header file included from |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3536 | there). The platform layer (``plat_get_image_source()``) then returns a reference |
| 3537 | to a device and a driver-specific ``spec`` which will be understood by the driver |
| 3538 | to allow access to the image data. |
| 3539 | |
| 3540 | The layer is designed in such a way that is it possible to chain drivers with |
| 3541 | other drivers. For example, file-system drivers may be implemented on top of |
| 3542 | physical block devices, both represented by IO devices with corresponding |
| 3543 | drivers. In such a case, the file-system "binding" with the block device may |
| 3544 | be deferred until the file-system device is initialised. |
| 3545 | |
| 3546 | The abstraction currently depends on structures being statically allocated |
| 3547 | by the drivers and callers, as the system does not yet provide a means of |
| 3548 | dynamically allocating memory. This may also have the affect of limiting the |
| 3549 | amount of open resources per driver. |
| 3550 | |
| 3551 | -------------- |
| 3552 | |
Chris Kay | 33bfc5e | 2023-02-14 11:30:04 +0000 | [diff] [blame] | 3553 | *Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3554 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3555 | .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 3556 | .. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3557 | .. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html |
Paul Beesley | 2437ddc | 2019-02-08 16:43:05 +0000 | [diff] [blame] | 3558 | .. _FreeBSD: https://www.freebsd.org |
Antonio Nino Diaz | cf0f805 | 2018-08-17 10:45:47 +0100 | [diff] [blame] | 3559 | .. _SCC: http://www.simple-cc.org/ |
Lucian Paul-Trifu | b93037a | 2022-06-22 18:45:36 +0100 | [diff] [blame] | 3560 | .. _DRTM: https://developer.arm.com/documentation/den0113/a |