Blame - arch/powerpc/include/asm/config_mpc85xx.h - filogic/uboot

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Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	1	/*
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	3	*
Wolfgang Denk	d79de1d	2013-07-08 09:37:19 +0200	[diff] [blame]	4	* SPDX-License-Identifier: GPL-2.0+
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	5	*/
				6
				7	#ifndef _ASM_MPC85xx_CONFIG_H_
				8	#define _ASM_MPC85xx_CONFIG_H_
				9
				10	/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
				11
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	12	#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
				13	#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
				14	#endif
				15
York Sun	f066a04	2012-10-28 08:12:54 +0000	[diff] [blame]	16	/*
				17	* This macro should be removed when we no longer care about backwards
				18	* compatibility with older operating systems.
				19	*/
				20	#define CONFIG_PPC_SPINTABLE_COMPATIBLE
				21
York Sun	7d69ea3	2012-10-08 07:44:22 +0000	[diff] [blame]	22	#define FSL_DDR_VER_4_7 47
				23
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	24	/* Number of TLB CAM entries we have on FSL Book-E chips */
				25	#if defined(CONFIG_E500MC)
				26	#define CONFIG_SYS_NUM_TLBCAMS 64
				27	#elif defined(CONFIG_E500)
				28	#define CONFIG_SYS_NUM_TLBCAMS 16
				29	#endif
				30
				31	#if defined(CONFIG_MPC8536)
				32	#define CONFIG_MAX_CPUS 1
				33	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	826cf62	2012-08-15 04:12:43 +0000	[diff] [blame]	34	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	35	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	36	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	37	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	38
Wolfgang Denk	a4de835	2011-02-02 22:36:10 +0100	[diff] [blame]	39	#elif defined(CONFIG_MPC8540)
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	40	#define CONFIG_MAX_CPUS 1
				41	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	42	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	43
Wolfgang Denk	a4de835	2011-02-02 22:36:10 +0100	[diff] [blame]	44	#elif defined(CONFIG_MPC8541)
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	45	#define CONFIG_MAX_CPUS 1
				46	#define CONFIG_SYS_FSL_NUM_LAWS 8
				47	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	48	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	49
				50	#elif defined(CONFIG_MPC8544)
				51	#define CONFIG_MAX_CPUS 1
				52	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	826cf62	2012-08-15 04:12:43 +0000	[diff] [blame]	53	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	54	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	55	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	56	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	57
				58	#elif defined(CONFIG_MPC8548)
				59	#define CONFIG_MAX_CPUS 1
				60	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	826cf62	2012-08-15 04:12:43 +0000	[diff] [blame]	61	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	62	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	63	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	866c6fa	2011-09-16 09:54:30 -0500	[diff] [blame]	64	#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala	f3339d6	2011-10-03 08:37:57 -0500	[diff] [blame]	65	#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhao	c8caa8a	2011-10-03 08:38:50 -0500	[diff] [blame]	66	#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	67	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				68	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				69	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				70	#define CONFIG_SYS_FSL_RMU
				71	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	72	#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan	9254640	2013-08-16 15:10:37 +0800	[diff] [blame]	73	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				74	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	75
				76	#elif defined(CONFIG_MPC8555)
				77	#define CONFIG_MAX_CPUS 1
				78	#define CONFIG_SYS_FSL_NUM_LAWS 8
				79	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	80	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	81
				82	#elif defined(CONFIG_MPC8560)
				83	#define CONFIG_MAX_CPUS 1
				84	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	85	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	86
				87	#elif defined(CONFIG_MPC8568)
				88	#define CONFIG_MAX_CPUS 1
				89	#define CONFIG_SYS_FSL_NUM_LAWS 10
				90	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	52bd815	2011-01-31 23:09:25 -0600	[diff] [blame]	91	#define QE_MURAM_SIZE 0x10000UL
				92	#define MAX_QE_RISC 2
				93	#define QE_NUM_OF_SNUM 28
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	94	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	95	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				96	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				97	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				98	#define CONFIG_SYS_FSL_RMU
				99	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	100
				101	#elif defined(CONFIG_MPC8569)
				102	#define CONFIG_MAX_CPUS 1
				103	#define CONFIG_SYS_FSL_NUM_LAWS 10
				104	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	52bd815	2011-01-31 23:09:25 -0600	[diff] [blame]	105	#define QE_MURAM_SIZE 0x20000UL
				106	#define MAX_QE_RISC 4
				107	#define QE_NUM_OF_SNUM 46
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	108	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	109	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				110	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				111	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				112	#define CONFIG_SYS_FSL_RMU
				113	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	114	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	115
				116	#elif defined(CONFIG_MPC8572)
				117	#define CONFIG_MAX_CPUS 2
				118	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	826cf62	2012-08-15 04:12:43 +0000	[diff] [blame]	119	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	120	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	121	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	9aa857b	2011-01-25 21:51:27 -0800	[diff] [blame]	122	#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun	c8fc959	2011-01-25 22:05:49 -0800	[diff] [blame]	123	#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	124	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	125
				126	#elif defined(CONFIG_P1010)
				127	#define CONFIG_MAX_CPUS 1
Priyanka Jain	0244963	2011-02-09 09:24:10 +0530	[diff] [blame]	128	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	129	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	130	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	131	#define CONFIG_TSECV2
				132	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	7373c59	2011-02-06 11:31:44 +0530	[diff] [blame]	133	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				134	#define CONFIG_NUM_DDR_CONTROLLERS 1
Mingkai Hu	6f024c9	2013-05-16 10:18:13 +0800	[diff] [blame]	135	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal	7373c59	2011-02-06 11:31:44 +0530	[diff] [blame]	136	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	137	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh	3fb68ee	2011-03-23 15:20:43 +0530	[diff] [blame]	138	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	c7664a4	2011-06-30 03:00:28 -0500	[diff] [blame]	139	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	af54a5f	2011-06-29 16:32:52 +0530	[diff] [blame]	140	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Shengzhou Liu	097be70	2013-08-15 09:31:47 +0800	[diff] [blame]	141	#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
Poonam Aggrwal	46b86ca	2011-07-07 20:36:47 +0530	[diff] [blame]	142	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	143	#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan	9254640	2013-08-16 15:10:37 +0800	[diff] [blame]	144	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				145	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	146
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	147	/* P1011 is single core version of P1020 */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	148	#elif defined(CONFIG_P1011)
				149	#define CONFIG_MAX_CPUS 1
				150	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	151	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	152	#define CONFIG_TSECV2
Prabhakar Kushwaha	1c48e77	2011-02-01 15:55:58 +0000	[diff] [blame]	153	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	154	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	155	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	156	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				157	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	158	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	159
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	160	/* P1012 is single core version of P1021 */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	161	#elif defined(CONFIG_P1012)
				162	#define CONFIG_MAX_CPUS 1
				163	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	164	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	165	#define CONFIG_TSECV2
Prabhakar Kushwaha	1c48e77	2011-02-01 15:55:58 +0000	[diff] [blame]	166	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	167	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	168	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	169	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				170	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	8cb2af7	2011-02-11 01:25:30 -0600	[diff] [blame]	171	#define QE_MURAM_SIZE 0x6000UL
				172	#define MAX_QE_RISC 1
				173	#define QE_NUM_OF_SNUM 28
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	174	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	175
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	176	/* P1013 is single core version of P1022 */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	177	#elif defined(CONFIG_P1013)
				178	#define CONFIG_MAX_CPUS 1
				179	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	180	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	181	#define CONFIG_TSECV2
				182	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	183	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	7cd0590	2011-01-30 17:06:20 -0600	[diff] [blame]	184	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				185	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				186	#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	187	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	188
				189	#elif defined(CONFIG_P1014)
				190	#define CONFIG_MAX_CPUS 1
Priyanka Jain	0244963	2011-02-09 09:24:10 +0530	[diff] [blame]	191	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	192	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	193	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	194	#define CONFIG_TSECV2
				195	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	7373c59	2011-02-06 11:31:44 +0530	[diff] [blame]	196	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				197	#define CONFIG_NUM_DDR_CONTROLLERS 1
				198	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh	3fb68ee	2011-03-23 15:20:43 +0530	[diff] [blame]	199	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	c7664a4	2011-06-30 03:00:28 -0500	[diff] [blame]	200	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	af54a5f	2011-06-29 16:32:52 +0530	[diff] [blame]	201	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal	46b86ca	2011-07-07 20:36:47 +0530	[diff] [blame]	202	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	203
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	204	/* P1017 is single core version of P1023 */
Roy Zang	1de20b0	2011-02-03 22:14:19 -0600	[diff] [blame]	205	#elif defined(CONFIG_P1017)
				206	#define CONFIG_MAX_CPUS 1
				207	#define CONFIG_SYS_FSL_NUM_LAWS 12
				208	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				209	#define CONFIG_SYS_NUM_FMAN 1
				210	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				211	#define CONFIG_NUM_DDR_CONTROLLERS 1
				212	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				213	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	214	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	215	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	216	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	217	#define CONFIG_SYS_FSL_ERRATUM_A005125
Roy Zang	1de20b0	2011-02-03 22:14:19 -0600	[diff] [blame]	218
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	219	#elif defined(CONFIG_P1020)
				220	#define CONFIG_MAX_CPUS 2
				221	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	222	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	223	#define CONFIG_TSECV2
Prabhakar Kushwaha	1c48e77	2011-02-01 15:55:58 +0000	[diff] [blame]	224	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	225	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	226	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	227	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				228	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	229	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	230
				231	#elif defined(CONFIG_P1021)
				232	#define CONFIG_MAX_CPUS 2
				233	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	234	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	235	#define CONFIG_TSECV2
Prabhakar Kushwaha	1c48e77	2011-02-01 15:55:58 +0000	[diff] [blame]	236	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	237	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	238	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	239	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				240	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	8cb2af7	2011-02-11 01:25:30 -0600	[diff] [blame]	241	#define QE_MURAM_SIZE 0x6000UL
				242	#define MAX_QE_RISC 1
				243	#define QE_NUM_OF_SNUM 28
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	244	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	245
				246	#elif defined(CONFIG_P1022)
				247	#define CONFIG_MAX_CPUS 2
				248	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	249	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	250	#define CONFIG_TSECV2
				251	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	252	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	7cd0590	2011-01-30 17:06:20 -0600	[diff] [blame]	253	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				254	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				255	#define CONFIG_FSL_SATA_ERRATUM_A001
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	256	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	257
Roy Zang	1de20b0	2011-02-03 22:14:19 -0600	[diff] [blame]	258	#elif defined(CONFIG_P1023)
				259	#define CONFIG_MAX_CPUS 2
				260	#define CONFIG_SYS_FSL_NUM_LAWS 12
				261	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				262	#define CONFIG_SYS_NUM_FMAN 1
				263	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				264	#define CONFIG_NUM_DDR_CONTROLLERS 1
				265	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				266	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	267	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	268	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	269	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	270	#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan	9254640	2013-08-16 15:10:37 +0800	[diff] [blame]	271	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				272	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Roy Zang	1de20b0	2011-02-03 22:14:19 -0600	[diff] [blame]	273
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	274	/* P1024 is lower end variant of P1020 */
				275	#elif defined(CONFIG_P1024)
				276	#define CONFIG_MAX_CPUS 2
				277	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	278	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	279	#define CONFIG_TSECV2
				280	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				281	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	282	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	283	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				284	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	285	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	286
				287	/* P1025 is lower end variant of P1021 */
				288	#elif defined(CONFIG_P1025)
				289	#define CONFIG_MAX_CPUS 2
				290	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	291	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	292	#define CONFIG_TSECV2
				293	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				294	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	295	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	296	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				297	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	8cb2af7	2011-02-11 01:25:30 -0600	[diff] [blame]	298	#define QE_MURAM_SIZE 0x6000UL
				299	#define MAX_QE_RISC 1
				300	#define QE_NUM_OF_SNUM 28
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	301	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	302
				303	/* P2010 is single core version of P2020 */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	304	#elif defined(CONFIG_P2010)
				305	#define CONFIG_MAX_CPUS 1
				306	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	307	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	308	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	309	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	7b5b480	2011-01-26 01:43:15 -0600	[diff] [blame]	310	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	9a878d5	2011-01-29 15:36:10 -0600	[diff] [blame]	311	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	312	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	313
				314	#elif defined(CONFIG_P2020)
				315	#define CONFIG_MAX_CPUS 2
				316	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	317	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	318	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	319	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	7b5b480	2011-01-26 01:43:15 -0600	[diff] [blame]	320	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	9a878d5	2011-01-29 15:36:10 -0600	[diff] [blame]	321	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	322	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				323	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				324	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				325	#define CONFIG_SYS_FSL_RMU
				326	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	327	#define CONFIG_SYS_FSL_ERRATUM_A005125
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	328
Scott Wood	a1ef48c	2012-08-14 10:14:51 +0000	[diff] [blame]	329	#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sun	7e0edbd	2012-10-08 07:44:15 +0000	[diff] [blame]	330	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	331	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	332	#define CONFIG_MAX_CPUS 4
Kumar Gala	3842bb5	2011-02-16 02:03:29 -0600	[diff] [blame]	333	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	334	#define CONFIG_SYS_FSL_NUM_LAWS 32
				335	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	619541b	2011-05-13 01:16:07 -0500	[diff] [blame]	336	#define CONFIG_SYS_NUM_FMAN 1
				337	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				338	#define CONFIG_SYS_NUM_FM1_10GEC 1
				339	#define CONFIG_NUM_DDR_CONTROLLERS 1
				340	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				341	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				342	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	343	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	619541b	2011-05-13 01:16:07 -0500	[diff] [blame]	344	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				345	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	a49034f	2011-04-13 00:19:10 -0500	[diff] [blame]	346	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala	619541b	2011-05-13 01:16:07 -0500	[diff] [blame]	347	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	9ed8811	2012-05-07 07:26:47 +0000	[diff] [blame]	348	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	cf4f493	2013-03-11 17:56:34 +0000	[diff] [blame]	349	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	945e59a	2011-11-22 06:51:15 -0600	[diff] [blame]	350	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	52db64b	2013-03-25 07:30:11 +0000	[diff] [blame]	351	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	df2be19	2011-11-20 10:01:35 -0800	[diff] [blame]	352	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	353	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				354	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				355	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	8080696	2012-08-14 10:14:53 +0000	[diff] [blame]	356	#define CONFIG_SYS_FSL_ERRATUM_A004510
				357	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				358	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				359	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	712b662	2012-09-28 21:26:19 +0000	[diff] [blame]	360	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	e3ab8c1	2012-10-25 12:40:00 +0000	[diff] [blame]	361	#define CONFIG_SYS_FSL_ERRATUM_A004849
Chunhe Lan	9254640	2013-08-16 15:10:37 +0800	[diff] [blame]	362	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				363	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Kumar Gala	619541b	2011-05-13 01:16:07 -0500	[diff] [blame]	364
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	365	#elif defined(CONFIG_PPC_P3041)
York Sun	7e0edbd	2012-10-08 07:44:15 +0000	[diff] [blame]	366	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	367	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	368	#define CONFIG_MAX_CPUS 4
Kumar Gala	3842bb5	2011-02-16 02:03:29 -0600	[diff] [blame]	369	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	370	#define CONFIG_SYS_FSL_NUM_LAWS 32
				371	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	60d95d8	2011-01-25 12:42:32 -0600	[diff] [blame]	372	#define CONFIG_SYS_NUM_FMAN 1
				373	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				374	#define CONFIG_SYS_NUM_FM1_10GEC 1
				375	#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	376	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	f4fb90f	2011-02-18 05:40:54 -0600	[diff] [blame]	377	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	378	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	379	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	6d6a0e1	2011-04-13 00:08:51 -0500	[diff] [blame]	380	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				381	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	a49034f	2011-04-13 00:19:10 -0500	[diff] [blame]	382	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3227620	2011-04-19 15:28:41 +0800	[diff] [blame]	383	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	5315553	2012-08-08 18:04:53 +0000	[diff] [blame]	384	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	cf4f493	2013-03-11 17:56:34 +0000	[diff] [blame]	385	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	945e59a	2011-11-22 06:51:15 -0600	[diff] [blame]	386	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	52db64b	2013-03-25 07:30:11 +0000	[diff] [blame]	387	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	df2be19	2011-11-20 10:01:35 -0800	[diff] [blame]	388	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	389	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				390	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				391	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	8080696	2012-08-14 10:14:53 +0000	[diff] [blame]	392	#define CONFIG_SYS_FSL_ERRATUM_A004510
				393	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				394	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				395	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	712b662	2012-09-28 21:26:19 +0000	[diff] [blame]	396	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	e3ab8c1	2012-10-25 12:40:00 +0000	[diff] [blame]	397	#define CONFIG_SYS_FSL_ERRATUM_A004849
York Sun	cca41c5	2013-06-25 11:37:49 -0700	[diff] [blame]	398	#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan	9254640	2013-08-16 15:10:37 +0800	[diff] [blame]	399	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				400	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	401
Scott Wood	a1ef48c	2012-08-14 10:14:51 +0000	[diff] [blame]	402	#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sun	7e0edbd	2012-10-08 07:44:15 +0000	[diff] [blame]	403	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	404	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	405	#define CONFIG_MAX_CPUS 8
Kumar Gala	3842bb5	2011-02-16 02:03:29 -0600	[diff] [blame]	406	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	407	#define CONFIG_SYS_FSL_NUM_LAWS 32
				408	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				409	#define CONFIG_SYS_NUM_FMAN 2
				410	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				411	#define CONFIG_SYS_NUM_FM2_DTSEC 4
				412	#define CONFIG_SYS_NUM_FM1_10GEC 1
				413	#define CONFIG_SYS_NUM_FM2_10GEC 1
				414	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	415	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	f4fb90f	2011-02-18 05:40:54 -0600	[diff] [blame]	416	#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	417	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	418	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	419	#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
				420	#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun	922f40f	2011-01-10 12:03:01 +0000	[diff] [blame]	421	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	422	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				423	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				424	#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R61911	8365992	2012-09-18 09:50:08 +0000	[diff] [blame]	425	#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	426	#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun	9ed8811	2012-05-07 07:26:47 +0000	[diff] [blame]	427	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	428	#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medve	b01c81f	2010-08-31 22:57:38 -0500	[diff] [blame]	429	#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi	6a62dc4	2011-04-18 17:16:00 -0500	[diff] [blame]	430	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi	90f381d	2011-04-01 13:19:36 -0500	[diff] [blame]	431	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala	945e59a	2011-11-22 06:51:15 -0600	[diff] [blame]	432	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	df2be19	2011-11-20 10:01:35 -0800	[diff] [blame]	433	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	434	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				435	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				436	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				437	#define CONFIG_SYS_FSL_RMU
				438	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood	8080696	2012-08-14 10:14:53 +0000	[diff] [blame]	439	#define CONFIG_SYS_FSL_ERRATUM_A004510
				440	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
				441	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gang	712b662	2012-09-28 21:26:19 +0000	[diff] [blame]	442	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	e3ab8c1	2012-10-25 12:40:00 +0000	[diff] [blame]	443	#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabi	c5355dd	2012-11-01 08:20:23 +0000	[diff] [blame]	444	#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chen	c48234e	2012-11-26 23:49:45 +0000	[diff] [blame]	445	#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
York Sun	cca41c5	2013-06-25 11:37:49 -0700	[diff] [blame]	446	#define CONFIG_SYS_FSL_ERRATUM_A005812
Chunhe Lan	9254640	2013-08-16 15:10:37 +0800	[diff] [blame]	447	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				448	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	449
Scott Wood	a1ef48c	2012-08-14 10:14:51 +0000	[diff] [blame]	450	#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sun	2394a0f	2012-10-08 07:44:30 +0000	[diff] [blame]	451	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	7e0edbd	2012-10-08 07:44:15 +0000	[diff] [blame]	452	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	453	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	454	#define CONFIG_MAX_CPUS 2
Kumar Gala	3842bb5	2011-02-16 02:03:29 -0600	[diff] [blame]	455	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	456	#define CONFIG_SYS_FSL_NUM_LAWS 32
				457	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	60d95d8	2011-01-25 12:42:32 -0600	[diff] [blame]	458	#define CONFIG_SYS_NUM_FMAN 1
				459	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				460	#define CONFIG_SYS_NUM_FM1_10GEC 1
				461	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	462	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	f4fb90f	2011-02-18 05:40:54 -0600	[diff] [blame]	463	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	464	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	465	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	6d6a0e1	2011-04-13 00:08:51 -0500	[diff] [blame]	466	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				467	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	a49034f	2011-04-13 00:19:10 -0500	[diff] [blame]	468	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3227620	2011-04-19 15:28:41 +0800	[diff] [blame]	469	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	cf4f493	2013-03-11 17:56:34 +0000	[diff] [blame]	470	#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sun	52db64b	2013-03-25 07:30:11 +0000	[diff] [blame]	471	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	df2be19	2011-11-20 10:01:35 -0800	[diff] [blame]	472	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	473	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				474	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				475	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	8080696	2012-08-14 10:14:53 +0000	[diff] [blame]	476	#define CONFIG_SYS_FSL_ERRATUM_A004510
				477	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				478	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gang	712b662	2012-09-28 21:26:19 +0000	[diff] [blame]	479	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Chunhe Lan	9254640	2013-08-16 15:10:37 +0800	[diff] [blame]	480	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				481	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	482
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	483	#elif defined(CONFIG_PPC_P5040)
Timur Tabi	9a7b5a3	2012-10-23 10:48:09 +0000	[diff] [blame]	484	#define CONFIG_SYS_PPC64
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	485	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	486	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	487	#define CONFIG_MAX_CPUS 4
				488	#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
				489	#define CONFIG_SYS_FSL_NUM_LAWS 32
				490	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				491	#define CONFIG_SYS_NUM_FMAN 2
				492	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				493	#define CONFIG_SYS_NUM_FM1_10GEC 1
				494	#define CONFIG_SYS_NUM_FM2_DTSEC 5
				495	#define CONFIG_SYS_NUM_FM2_10GEC 1
				496	#define CONFIG_NUM_DDR_CONTROLLERS 2
				497	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				498	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				499	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				500	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				501	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				502	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				503	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				504	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	cf4f493	2013-03-11 17:56:34 +0000	[diff] [blame]	505	#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	506	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
				507	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
				508	#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	509	#define CONFIG_SYS_FSL_ERRATUM_A004510
				510	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				511	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
York Sun	cca41c5	2013-06-25 11:37:49 -0700	[diff] [blame]	512	#define CONFIG_SYS_FSL_ERRATUM_A005812
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	513
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	514	#elif defined(CONFIG_BSC9131)
				515	#define CONFIG_MAX_CPUS 1
				516	#define CONFIG_FSL_SDHC_V2_3
				517	#define CONFIG_SYS_FSL_NUM_LAWS 12
				518	#define CONFIG_TSECV2
				519	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				520	#define CONFIG_NUM_DDR_CONTROLLERS 1
Priyanka Jain	f81e8b2	2013-04-04 09:31:54 +0530	[diff] [blame]	521	#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
				522	#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu	6f024c9	2013-05-16 10:18:13 +0800	[diff] [blame]	523	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	524	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				525	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	526	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	527	#define CONFIG_SYS_FSL_ERRATUM_A005125
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	528
Prabhakar Kushwaha	92543c2	2013-01-23 17:59:57 +0000	[diff] [blame]	529	#elif defined(CONFIG_BSC9132)
				530	#define CONFIG_MAX_CPUS 2
				531	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
				532	#define CONFIG_FSL_SDHC_V2_3
				533	#define CONFIG_SYS_FSL_NUM_LAWS 12
				534	#define CONFIG_TSECV2
				535	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				536	#define CONFIG_NUM_DDR_CONTROLLERS 2
Priyanka Jain	c73b903	2013-07-02 09:21:04 +0530	[diff] [blame]	537	#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
				538	#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
				539	#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
				540	#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
York Sun	84fa67e	2013-04-18 19:31:01 -0700	[diff] [blame]	541	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha	92543c2	2013-01-23 17:59:57 +0000	[diff] [blame]	542	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				543	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	92543c2	2013-01-23 17:59:57 +0000	[diff] [blame]	544	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				545	#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
				546	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	547	#define CONFIG_SYS_FSL_ERRATUM_A005125
Chunhe Lan	9254640	2013-08-16 15:10:37 +0800	[diff] [blame]	548	#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
				549	#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
Prabhakar Kushwaha	92543c2	2013-01-23 17:59:57 +0000	[diff] [blame]	550
York Sun	64fd08b	2013-03-25 07:40:05 +0000	[diff] [blame]	551	#elif defined(CONFIG_PPC_T4240) \|\| defined(CONFIG_PPC_T4160)
				552	#define CONFIG_E6500
York Sun	2394a0f	2012-10-08 07:44:30 +0000	[diff] [blame]	553	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	9941a22	2012-10-08 07:44:19 +0000	[diff] [blame]	554	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				555	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sun	aa150bb	2013-03-25 07:40:07 +0000	[diff] [blame]	556	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun	9941a22	2012-10-08 07:44:19 +0000	[diff] [blame]	557	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun	64fd08b	2013-03-25 07:40:05 +0000	[diff] [blame]	558	#ifdef CONFIG_PPC_T4240
York Sun	9941a22	2012-10-08 07:44:19 +0000	[diff] [blame]	559	#define CONFIG_MAX_CPUS 12
York Sun	9941a22	2012-10-08 07:44:19 +0000	[diff] [blame]	560	#define CONFIG_SYS_NUM_FM1_DTSEC 8
				561	#define CONFIG_SYS_NUM_FM1_10GEC 2
				562	#define CONFIG_SYS_NUM_FM2_DTSEC 8
				563	#define CONFIG_SYS_NUM_FM2_10GEC 2
				564	#define CONFIG_NUM_DDR_CONTROLLERS 3
York Sun	64fd08b	2013-03-25 07:40:05 +0000	[diff] [blame]	565	#else
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	566	#define CONFIG_MAX_CPUS 8
York Sun	64fd08b	2013-03-25 07:40:05 +0000	[diff] [blame]	567	#define CONFIG_SYS_NUM_FM1_DTSEC 7
				568	#define CONFIG_SYS_NUM_FM1_10GEC 1
				569	#define CONFIG_SYS_NUM_FM2_DTSEC 7
				570	#define CONFIG_SYS_NUM_FM2_10GEC 1
				571	#define CONFIG_NUM_DDR_CONTROLLERS 2
				572	#endif
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	573	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
				574	#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwaha	873e9f0	2013-07-31 16:56:41 +0530	[diff] [blame]	575	#define CONFIG_SYS_FSL_SRDS_1
				576	#define CONFIG_SYS_FSL_SRDS_2
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	577	#define CONFIG_SYS_FSL_SRDS_3
				578	#define CONFIG_SYS_FSL_SRDS_4
				579	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				580	#define CONFIG_SYS_NUM_FMAN 2
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	581	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu	6f024c9	2013-05-16 10:18:13 +0800	[diff] [blame]	582	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	583	#define CONFIG_SYS_FMAN_V3
				584	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				585	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				586	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
				587	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				588	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				589	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang	d5eca7e	2013-06-25 18:12:14 +0800	[diff] [blame]	590	#define CONFIG_SYS_FSL_SRIO_LIODN
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	591	#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
				592	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				593	#define CONFIG_SYS_FSL_ERRATUM_A004468
				594	#define CONFIG_SYS_FSL_ERRATUM_A_004934
				595	#define CONFIG_SYS_FSL_ERRATUM_A005871
Scott Wood	3f4a5c4	2013-05-15 17:50:13 -0500	[diff] [blame]	596	#define CONFIG_SYS_FSL_ERRATUM_A006593
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	597	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				598	#define CONFIG_SYS_FSL_PCI_VER_3_X
				599
Poonam Aggrwal	525ab51	2013-03-25 07:40:20 +0000	[diff] [blame]	600	#elif defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_B4420)
				601	#define CONFIG_E6500
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	602	#define CONFIG_SYS_PPC64 /* 64-bit core */
				603	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				604	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
				605	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	606	#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwaha	873e9f0	2013-07-31 16:56:41 +0530	[diff] [blame]	607	#define CONFIG_SYS_FSL_SRDS_1
				608	#define CONFIG_SYS_FSL_SRDS_2
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	609	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				610	#define CONFIG_SYS_NUM_FMAN 1
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	611	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu	6f024c9	2013-05-16 10:18:13 +0800	[diff] [blame]	612	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	613	#define CONFIG_SYS_FMAN_V3
				614	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				615	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				616	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				617	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				618	#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu	5d9606e	2013-02-27 21:56:54 +0000	[diff] [blame]	619	#define CONFIG_SYS_FSL_ERRATUM_A005871
Scott Wood	3f4a5c4	2013-05-15 17:50:13 -0500	[diff] [blame]	620	#define CONFIG_SYS_FSL_ERRATUM_A006593
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	621	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				622
Poonam Aggrwal	525ab51	2013-03-25 07:40:20 +0000	[diff] [blame]	623	#ifdef CONFIG_PPC_B4860
York Sun	aa150bb	2013-03-25 07:40:07 +0000	[diff] [blame]	624	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun	bcf7b3d	2012-10-08 07:44:20 +0000	[diff] [blame]	625	#define CONFIG_MAX_CPUS 4
				626	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
York Sun	bcf7b3d	2012-10-08 07:44:20 +0000	[diff] [blame]	627	#define CONFIG_SYS_NUM_FM1_DTSEC 6
				628	#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwal	1c85955	2012-12-23 19:22:33 +0000	[diff] [blame]	629	#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun	bcf7b3d	2012-10-08 07:44:20 +0000	[diff] [blame]	630	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				631	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				632	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang	bc6486a	2013-06-25 18:12:13 +0800	[diff] [blame]	633	#define CONFIG_SYS_FSL_SRIO_LIODN
Poonam Aggrwal	525ab51	2013-03-25 07:40:20 +0000	[diff] [blame]	634	#else
				635	#define CONFIG_MAX_CPUS 2
				636	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
				637	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
				638	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				639	#define CONFIG_SYS_NUM_FM1_10GEC 0
				640	#define CONFIG_NUM_DDR_CONTROLLERS 1
				641	#endif
York Sun	bcf7b3d	2012-10-08 07:44:20 +0000	[diff] [blame]	642
York Sun	4657136	2013-03-25 07:40:06 +0000	[diff] [blame]	643	#elif defined(CONFIG_PPC_T1040)
				644	#define CONFIG_E5500
				645	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				646	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sun	aa150bb	2013-03-25 07:40:07 +0000	[diff] [blame]	647	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun	4657136	2013-03-25 07:40:06 +0000	[diff] [blame]	648	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
				649	#define CONFIG_MAX_CPUS 4
				650	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
				651	#define CONFIG_SYS_FSL_NUM_LAWS 16
				652	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				653	#define CONFIG_SYS_NUM_FMAN 1
				654	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				655	#define CONFIG_NUM_DDR_CONTROLLERS 1
				656	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
				657	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
				658	#define CONFIG_SYS_FMAN_V3
				659	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				660	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				661	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				662	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				663	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				664	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				665	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				666	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				667	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				668	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				669
Mingkai Hu	1a25807	2013-07-04 17:30:36 +0800	[diff] [blame]	670	#elif defined(CONFIG_PPC_C29X)
				671	#define CONFIG_MAX_CPUS 1
				672	#define CONFIG_FSL_SDHC_V2_3
				673	#define CONFIG_SYS_FSL_NUM_LAWS 12
				674	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
				675	#define CONFIG_TSECV2_1
				676	#define CONFIG_SYS_FSL_SEC_COMPAT 6
				677	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				678	#define CONFIG_NUM_DDR_CONTROLLERS 1
				679	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
				680	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	0cc5907	2013-08-20 15:09:43 -0700	[diff] [blame]	681	#define CONFIG_SYS_FSL_ERRATUM_A005125
Mingkai Hu	1a25807	2013-07-04 17:30:36 +0800	[diff] [blame]	682
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	683	#else
				684	#error Processor type not defined for this platform
				685	#endif
				686
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	687	#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
				688	#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
				689	#endif
				690
York Sun	aa150bb	2013-03-25 07:40:07 +0000	[diff] [blame]	691	#ifdef CONFIG_E6500
				692	#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
				693	#else
				694	#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
				695	#endif
				696
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	697	#endif /* _ASM_MPC85xx_CONFIG_H_ */