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git01.mediatek.com / filogic / uboot / d8f341c3f2b955dd45e0fe716801853e8262ac7c / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: 691c075582a4de5b1f9ff4fe5fde19a26d9b5da9 [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]30/* Number of TLB CAM entries we have on FSL Book-E chips */
31#if defined(CONFIG_E500MC)
32#define CONFIG_SYS_NUM_TLBCAMS 64
33#elif defined(CONFIG_E500)
34#define CONFIG_SYS_NUM_TLBCAMS 16
35#endif
36
37#if defined(CONFIG_MPC8536)
38#define CONFIG_MAX_CPUS 1
39#define CONFIG_SYS_FSL_NUM_LAWS 12
40#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]41#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]42
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]43#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]44#define CONFIG_MAX_CPUS 1
45#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]46#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]47
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]48#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]49#define CONFIG_MAX_CPUS 1
50#define CONFIG_SYS_FSL_NUM_LAWS 8
51#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]52#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]53
54#elif defined(CONFIG_MPC8544)
55#define CONFIG_MAX_CPUS 1
56#define CONFIG_SYS_FSL_NUM_LAWS 10
57#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]58#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]59
60#elif defined(CONFIG_MPC8548)
61#define CONFIG_MAX_CPUS 1
62#define CONFIG_SYS_FSL_NUM_LAWS 10
63#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]64#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]65
66#elif defined(CONFIG_MPC8555)
67#define CONFIG_MAX_CPUS 1
68#define CONFIG_SYS_FSL_NUM_LAWS 8
69#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]70#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]71
72#elif defined(CONFIG_MPC8560)
73#define CONFIG_MAX_CPUS 1
74#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]75#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]76
77#elif defined(CONFIG_MPC8568)
78#define CONFIG_MAX_CPUS 1
79#define CONFIG_SYS_FSL_NUM_LAWS 10
80#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]81#define QE_MURAM_SIZE 0x10000UL
82#define MAX_QE_RISC 2
83#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]84#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]85
86#elif defined(CONFIG_MPC8569)
87#define CONFIG_MAX_CPUS 1
88#define CONFIG_SYS_FSL_NUM_LAWS 10
89#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]90#define QE_MURAM_SIZE 0x20000UL
91#define MAX_QE_RISC 4
92#define QE_NUM_OF_SNUM 46
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]93#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]94
95#elif defined(CONFIG_MPC8572)
96#define CONFIG_MAX_CPUS 2
97#define CONFIG_SYS_FSL_NUM_LAWS 12
98#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]99#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]100#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]101#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]102
103#elif defined(CONFIG_P1010)
104#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]105#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]106#define CONFIG_SYS_FSL_NUM_LAWS 12
107#define CONFIG_TSECV2
108#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]109#define CONFIG_FSL_SATA_V2
110#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
111#define CONFIG_NUM_DDR_CONTROLLERS 1
112#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]113#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]114#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]115
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]116/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]117#elif defined(CONFIG_P1011)
118#define CONFIG_MAX_CPUS 1
119#define CONFIG_SYS_FSL_NUM_LAWS 12
120#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]121#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]122#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]123#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]124#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
125#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]126
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]127/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]128#elif defined(CONFIG_P1012)
129#define CONFIG_MAX_CPUS 1
130#define CONFIG_SYS_FSL_NUM_LAWS 12
131#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]132#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]133#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]134#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]135#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
136#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]137#define QE_MURAM_SIZE 0x6000UL
138#define MAX_QE_RISC 1
139#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]140
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]141/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]142#elif defined(CONFIG_P1013)
143#define CONFIG_MAX_CPUS 1
144#define CONFIG_SYS_FSL_NUM_LAWS 12
145#define CONFIG_TSECV2
146#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]147#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]148#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
149#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
150#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]151
152#elif defined(CONFIG_P1014)
153#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]154#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]155#define CONFIG_SYS_FSL_NUM_LAWS 12
156#define CONFIG_TSECV2
157#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]158#define CONFIG_FSL_SATA_V2
159#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
160#define CONFIG_NUM_DDR_CONTROLLERS 1
161#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]162#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]163
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]164/* P1015 is single core version of P1024 */
165#elif defined(CONFIG_P1015)
166#define CONFIG_MAX_CPUS 1
167#define CONFIG_SYS_FSL_NUM_LAWS 12
168#define CONFIG_TSECV2
169#define CONFIG_FSL_PCIE_DISABLE_ASPM
170#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]171#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]172#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
173#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
174
175/* P1016 is single core version of P1025 */
176#elif defined(CONFIG_P1016)
177#define CONFIG_MAX_CPUS 1
178#define CONFIG_SYS_FSL_NUM_LAWS 12
179#define CONFIG_TSECV2
180#define CONFIG_FSL_PCIE_DISABLE_ASPM
181#define CONFIG_SYS_FSL_SEC_COMPAT 2
182#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
183#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]184#define QE_MURAM_SIZE 0x6000UL
185#define MAX_QE_RISC 1
186#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]187#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]188
189/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]190#elif defined(CONFIG_P1017)
191#define CONFIG_MAX_CPUS 1
192#define CONFIG_SYS_FSL_NUM_LAWS 12
193#define CONFIG_SYS_FSL_SEC_COMPAT 4
194#define CONFIG_SYS_NUM_FMAN 1
195#define CONFIG_SYS_NUM_FM1_DTSEC 2
196#define CONFIG_NUM_DDR_CONTROLLERS 1
197#define CONFIG_SYS_QMAN_NUM_PORTALS 3
198#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]199#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]200#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]201#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]202
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]203#elif defined(CONFIG_P1020)
204#define CONFIG_MAX_CPUS 2
205#define CONFIG_SYS_FSL_NUM_LAWS 12
206#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]207#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]208#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]209#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]210#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
211#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]212
213#elif defined(CONFIG_P1021)
214#define CONFIG_MAX_CPUS 2
215#define CONFIG_SYS_FSL_NUM_LAWS 12
216#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]217#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]218#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]219#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]220#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
221#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]222#define QE_MURAM_SIZE 0x6000UL
223#define MAX_QE_RISC 1
224#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]225
226#elif defined(CONFIG_P1022)
227#define CONFIG_MAX_CPUS 2
228#define CONFIG_SYS_FSL_NUM_LAWS 12
229#define CONFIG_TSECV2
230#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]231#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]232#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
233#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
234#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]235
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]236#elif defined(CONFIG_P1023)
237#define CONFIG_MAX_CPUS 2
238#define CONFIG_SYS_FSL_NUM_LAWS 12
239#define CONFIG_SYS_FSL_SEC_COMPAT 4
240#define CONFIG_SYS_NUM_FMAN 1
241#define CONFIG_SYS_NUM_FM1_DTSEC 2
242#define CONFIG_NUM_DDR_CONTROLLERS 1
243#define CONFIG_SYS_QMAN_NUM_PORTALS 3
244#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]245#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]246#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]247#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]248
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]249/* P1024 is lower end variant of P1020 */
250#elif defined(CONFIG_P1024)
251#define CONFIG_MAX_CPUS 2
252#define CONFIG_SYS_FSL_NUM_LAWS 12
253#define CONFIG_TSECV2
254#define CONFIG_FSL_PCIE_DISABLE_ASPM
255#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]256#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]257#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
258#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
259
260/* P1025 is lower end variant of P1021 */
261#elif defined(CONFIG_P1025)
262#define CONFIG_MAX_CPUS 2
263#define CONFIG_SYS_FSL_NUM_LAWS 12
264#define CONFIG_TSECV2
265#define CONFIG_FSL_PCIE_DISABLE_ASPM
266#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]267#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]268#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
269#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]270#define QE_MURAM_SIZE 0x6000UL
271#define MAX_QE_RISC 1
272#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]273
274/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]275#elif defined(CONFIG_P2010)
276#define CONFIG_MAX_CPUS 1
277#define CONFIG_SYS_FSL_NUM_LAWS 12
278#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]279#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]280#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]281#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]282
283#elif defined(CONFIG_P2020)
284#define CONFIG_MAX_CPUS 2
285#define CONFIG_SYS_FSL_NUM_LAWS 12
286#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]287#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]288#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]289#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]290
291#elif defined(CONFIG_PPC_P2040)
292#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]293#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]294#define CONFIG_SYS_FSL_NUM_LAWS 32
295#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]296#define CONFIG_SYS_NUM_FMAN 1
297#define CONFIG_SYS_NUM_FM1_DTSEC 5
298#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]299#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]300#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]301#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]302#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]303#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
304#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]305#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]306#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]307
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]308#elif defined(CONFIG_PPC_P2041)
309#define CONFIG_MAX_CPUS 4
310#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
311#define CONFIG_SYS_FSL_NUM_LAWS 32
312#define CONFIG_SYS_FSL_SEC_COMPAT 4
313#define CONFIG_SYS_NUM_FMAN 1
314#define CONFIG_SYS_NUM_FM1_DTSEC 5
315#define CONFIG_SYS_NUM_FM1_10GEC 1
316#define CONFIG_NUM_DDR_CONTROLLERS 1
317#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
318#define CONFIG_SYS_FSL_TBCLK_DIV 32
319#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]320#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]321#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
322#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]323#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]324#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
325
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]326#elif defined(CONFIG_PPC_P3041)
327#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]328#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]329#define CONFIG_SYS_FSL_NUM_LAWS 32
330#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]331#define CONFIG_SYS_NUM_FMAN 1
332#define CONFIG_SYS_NUM_FM1_DTSEC 5
333#define CONFIG_SYS_NUM_FM1_10GEC 1
334#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]335#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]336#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]337#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]338#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]339#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
340#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]341#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]342#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]343
344#elif defined(CONFIG_PPC_P4040)
345#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]346#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]347#define CONFIG_SYS_FSL_NUM_LAWS 32
348#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]349#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]350#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]351#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]352#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]353
354#elif defined(CONFIG_PPC_P4080)
355#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]356#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]357#define CONFIG_SYS_FSL_NUM_LAWS 32
358#define CONFIG_SYS_FSL_SEC_COMPAT 4
359#define CONFIG_SYS_NUM_FMAN 2
360#define CONFIG_SYS_NUM_FM1_DTSEC 4
361#define CONFIG_SYS_NUM_FM2_DTSEC 4
362#define CONFIG_SYS_NUM_FM1_10GEC 1
363#define CONFIG_SYS_NUM_FM2_10GEC 1
364#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]365#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]366#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]367#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]368#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]369#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
370#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]371#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]372#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
373#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
374#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
375#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
376#define CONFIG_SYS_P4080_ERRATUM_CPU22
377#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]378#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500[diff] [blame]379#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500[diff] [blame]380#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]381
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]382/* P5010 is single core version of P5020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]383#elif defined(CONFIG_PPC_P5010)
384#define CONFIG_MAX_CPUS 1
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]385#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]386#define CONFIG_SYS_FSL_NUM_LAWS 32
387#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]388#define CONFIG_SYS_NUM_FMAN 1
389#define CONFIG_SYS_NUM_FM1_DTSEC 5
390#define CONFIG_SYS_NUM_FM1_10GEC 1
391#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]392#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]393#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]394#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]395#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]396#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
397#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]398#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]399#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]400
401#elif defined(CONFIG_PPC_P5020)
402#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]403#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]404#define CONFIG_SYS_FSL_NUM_LAWS 32
405#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]406#define CONFIG_SYS_NUM_FMAN 1
407#define CONFIG_SYS_NUM_FM1_DTSEC 5
408#define CONFIG_SYS_NUM_FM1_10GEC 1
409#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]410#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]411#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]412#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]413#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]414#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
415#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]416#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]417#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]418
419#else
420#error Processor type not defined for this platform
421#endif
422
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame^]423#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
424#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
425#endif
426
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]427#endif /* _ASM_MPC85xx_CONFIG_H_ */