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git01.mediatek.com / filogic / uboot / 6a62dc4e2799f8ffbfe69038f619fadbd3930262 / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: ccf703b2430eb87a4805a2f5fc5cad18f45e9dca [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
26/* Number of TLB CAM entries we have on FSL Book-E chips */
27#if defined(CONFIG_E500MC)
28#define CONFIG_SYS_NUM_TLBCAMS 64
29#elif defined(CONFIG_E500)
30#define CONFIG_SYS_NUM_TLBCAMS 16
31#endif
32
33#if defined(CONFIG_MPC8536)
34#define CONFIG_MAX_CPUS 1
35#define CONFIG_SYS_FSL_NUM_LAWS 12
36#define CONFIG_SYS_FSL_SEC_COMPAT 2
37
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]38#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]39#define CONFIG_MAX_CPUS 1
40#define CONFIG_SYS_FSL_NUM_LAWS 8
41
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]42#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]43#define CONFIG_MAX_CPUS 1
44#define CONFIG_SYS_FSL_NUM_LAWS 8
45#define CONFIG_SYS_FSL_SEC_COMPAT 2
46
47#elif defined(CONFIG_MPC8544)
48#define CONFIG_MAX_CPUS 1
49#define CONFIG_SYS_FSL_NUM_LAWS 10
50#define CONFIG_SYS_FSL_SEC_COMPAT 2
51
52#elif defined(CONFIG_MPC8548)
53#define CONFIG_MAX_CPUS 1
54#define CONFIG_SYS_FSL_NUM_LAWS 10
55#define CONFIG_SYS_FSL_SEC_COMPAT 2
56
57#elif defined(CONFIG_MPC8555)
58#define CONFIG_MAX_CPUS 1
59#define CONFIG_SYS_FSL_NUM_LAWS 8
60#define CONFIG_SYS_FSL_SEC_COMPAT 2
61
62#elif defined(CONFIG_MPC8560)
63#define CONFIG_MAX_CPUS 1
64#define CONFIG_SYS_FSL_NUM_LAWS 8
65
66#elif defined(CONFIG_MPC8568)
67#define CONFIG_MAX_CPUS 1
68#define CONFIG_SYS_FSL_NUM_LAWS 10
69#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]70#define QE_MURAM_SIZE 0x10000UL
71#define MAX_QE_RISC 2
72#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]73
74#elif defined(CONFIG_MPC8569)
75#define CONFIG_MAX_CPUS 1
76#define CONFIG_SYS_FSL_NUM_LAWS 10
77#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]78#define QE_MURAM_SIZE 0x20000UL
79#define MAX_QE_RISC 4
80#define QE_NUM_OF_SNUM 46
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]81
82#elif defined(CONFIG_MPC8572)
83#define CONFIG_MAX_CPUS 2
84#define CONFIG_SYS_FSL_NUM_LAWS 12
85#define CONFIG_SYS_FSL_SEC_COMPAT 2
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]86#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]87#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]88
89#elif defined(CONFIG_P1010)
90#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]91#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]92#define CONFIG_SYS_FSL_NUM_LAWS 12
93#define CONFIG_TSECV2
94#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]95#define CONFIG_FSL_SATA_V2
96#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
97#define CONFIG_NUM_DDR_CONTROLLERS 1
98#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]99
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]100/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]101#elif defined(CONFIG_P1011)
102#define CONFIG_MAX_CPUS 1
103#define CONFIG_SYS_FSL_NUM_LAWS 12
104#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]105#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]106#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]107#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
108#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]109
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]110/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]111#elif defined(CONFIG_P1012)
112#define CONFIG_MAX_CPUS 1
113#define CONFIG_SYS_FSL_NUM_LAWS 12
114#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]115#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]116#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]117#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
118#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]119#define QE_MURAM_SIZE 0x6000UL
120#define MAX_QE_RISC 1
121#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]122
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]123/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]124#elif defined(CONFIG_P1013)
125#define CONFIG_MAX_CPUS 1
126#define CONFIG_SYS_FSL_NUM_LAWS 12
127#define CONFIG_TSECV2
128#define CONFIG_SYS_FSL_SEC_COMPAT 2
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]129#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
130#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
131#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]132
133#elif defined(CONFIG_P1014)
134#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]135#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]136#define CONFIG_SYS_FSL_NUM_LAWS 12
137#define CONFIG_TSECV2
138#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]139#define CONFIG_FSL_SATA_V2
140#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
141#define CONFIG_NUM_DDR_CONTROLLERS 1
142#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]143
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]144/* P1015 is single core version of P1024 */
145#elif defined(CONFIG_P1015)
146#define CONFIG_MAX_CPUS 1
147#define CONFIG_SYS_FSL_NUM_LAWS 12
148#define CONFIG_TSECV2
149#define CONFIG_FSL_PCIE_DISABLE_ASPM
150#define CONFIG_SYS_FSL_SEC_COMPAT 2
151#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
152#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
153
154/* P1016 is single core version of P1025 */
155#elif defined(CONFIG_P1016)
156#define CONFIG_MAX_CPUS 1
157#define CONFIG_SYS_FSL_NUM_LAWS 12
158#define CONFIG_TSECV2
159#define CONFIG_FSL_PCIE_DISABLE_ASPM
160#define CONFIG_SYS_FSL_SEC_COMPAT 2
161#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
162#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]163#define QE_MURAM_SIZE 0x6000UL
164#define MAX_QE_RISC 1
165#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]166
167/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]168#elif defined(CONFIG_P1017)
169#define CONFIG_MAX_CPUS 1
170#define CONFIG_SYS_FSL_NUM_LAWS 12
171#define CONFIG_SYS_FSL_SEC_COMPAT 4
172#define CONFIG_SYS_NUM_FMAN 1
173#define CONFIG_SYS_NUM_FM1_DTSEC 2
174#define CONFIG_NUM_DDR_CONTROLLERS 1
175#define CONFIG_SYS_QMAN_NUM_PORTALS 3
176#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]177#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]178
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]179#elif defined(CONFIG_P1020)
180#define CONFIG_MAX_CPUS 2
181#define CONFIG_SYS_FSL_NUM_LAWS 12
182#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]183#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]184#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]185#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
186#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]187
188#elif defined(CONFIG_P1021)
189#define CONFIG_MAX_CPUS 2
190#define CONFIG_SYS_FSL_NUM_LAWS 12
191#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]192#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]193#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]194#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
195#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]196#define QE_MURAM_SIZE 0x6000UL
197#define MAX_QE_RISC 1
198#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]199
200#elif defined(CONFIG_P1022)
201#define CONFIG_MAX_CPUS 2
202#define CONFIG_SYS_FSL_NUM_LAWS 12
203#define CONFIG_TSECV2
204#define CONFIG_SYS_FSL_SEC_COMPAT 2
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]205#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
206#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
207#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]208
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]209#elif defined(CONFIG_P1023)
210#define CONFIG_MAX_CPUS 2
211#define CONFIG_SYS_FSL_NUM_LAWS 12
212#define CONFIG_SYS_FSL_SEC_COMPAT 4
213#define CONFIG_SYS_NUM_FMAN 1
214#define CONFIG_SYS_NUM_FM1_DTSEC 2
215#define CONFIG_NUM_DDR_CONTROLLERS 1
216#define CONFIG_SYS_QMAN_NUM_PORTALS 3
217#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]218#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]219
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]220/* P1024 is lower end variant of P1020 */
221#elif defined(CONFIG_P1024)
222#define CONFIG_MAX_CPUS 2
223#define CONFIG_SYS_FSL_NUM_LAWS 12
224#define CONFIG_TSECV2
225#define CONFIG_FSL_PCIE_DISABLE_ASPM
226#define CONFIG_SYS_FSL_SEC_COMPAT 2
227#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
228#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
229
230/* P1025 is lower end variant of P1021 */
231#elif defined(CONFIG_P1025)
232#define CONFIG_MAX_CPUS 2
233#define CONFIG_SYS_FSL_NUM_LAWS 12
234#define CONFIG_TSECV2
235#define CONFIG_FSL_PCIE_DISABLE_ASPM
236#define CONFIG_SYS_FSL_SEC_COMPAT 2
237#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
238#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]239#define QE_MURAM_SIZE 0x6000UL
240#define MAX_QE_RISC 1
241#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]242
243/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]244#elif defined(CONFIG_P2010)
245#define CONFIG_MAX_CPUS 1
246#define CONFIG_SYS_FSL_NUM_LAWS 12
247#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]248#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]249#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]250
251#elif defined(CONFIG_P2020)
252#define CONFIG_MAX_CPUS 2
253#define CONFIG_SYS_FSL_NUM_LAWS 12
254#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]255#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]256#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]257
258#elif defined(CONFIG_PPC_P2040)
259#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]260#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]261#define CONFIG_SYS_FSL_NUM_LAWS 32
262#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]263#define CONFIG_SYS_NUM_FMAN 1
264#define CONFIG_SYS_NUM_FM1_DTSEC 5
265#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]266#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]267#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
268#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]269#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]270
271#elif defined(CONFIG_PPC_P3041)
272#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]273#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]274#define CONFIG_SYS_FSL_NUM_LAWS 32
275#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]276#define CONFIG_SYS_NUM_FMAN 1
277#define CONFIG_SYS_NUM_FM1_DTSEC 5
278#define CONFIG_SYS_NUM_FM1_10GEC 1
279#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]280#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]281#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
282#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]283#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]284
285#elif defined(CONFIG_PPC_P4040)
286#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]287#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]288#define CONFIG_SYS_FSL_NUM_LAWS 32
289#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]290#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]291
292#elif defined(CONFIG_PPC_P4080)
293#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]294#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]295#define CONFIG_SYS_FSL_NUM_LAWS 32
296#define CONFIG_SYS_FSL_SEC_COMPAT 4
297#define CONFIG_SYS_NUM_FMAN 2
298#define CONFIG_SYS_NUM_FM1_DTSEC 4
299#define CONFIG_SYS_NUM_FM2_DTSEC 4
300#define CONFIG_SYS_NUM_FM1_10GEC 1
301#define CONFIG_SYS_NUM_FM2_10GEC 1
302#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]303#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]304#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
305#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]306#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]307#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
308#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
309#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
310#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
311#define CONFIG_SYS_P4080_ERRATUM_CPU22
312#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]313#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500[diff] [blame^]314#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500[diff] [blame]315#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]316
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]317/* P5010 is single core version of P5020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]318#elif defined(CONFIG_PPC_P5010)
319#define CONFIG_MAX_CPUS 1
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]320#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]321#define CONFIG_SYS_FSL_NUM_LAWS 32
322#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]323#define CONFIG_SYS_NUM_FMAN 1
324#define CONFIG_SYS_NUM_FM1_DTSEC 5
325#define CONFIG_SYS_NUM_FM1_10GEC 1
326#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]327#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]328#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
329#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]330#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]331
332#elif defined(CONFIG_PPC_P5020)
333#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]334#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]335#define CONFIG_SYS_FSL_NUM_LAWS 32
336#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]337#define CONFIG_SYS_NUM_FMAN 1
338#define CONFIG_SYS_NUM_FM1_DTSEC 5
339#define CONFIG_SYS_NUM_FM1_10GEC 1
340#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]341#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]342#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
343#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]344#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]345
346#else
347#error Processor type not defined for this platform
348#endif
349
350#endif /* _ASM_MPC85xx_CONFIG_H_ */