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git01.mediatek.com / filogic / uboot / 60d95d8e81bcff6f77952c2a99960dd0d0e4f976 / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: 53703f65665356c50a2c6e2b612da66c00f27b47 [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
26/* Number of TLB CAM entries we have on FSL Book-E chips */
27#if defined(CONFIG_E500MC)
28#define CONFIG_SYS_NUM_TLBCAMS 64
29#elif defined(CONFIG_E500)
30#define CONFIG_SYS_NUM_TLBCAMS 16
31#endif
32
33#if defined(CONFIG_MPC8536)
34#define CONFIG_MAX_CPUS 1
35#define CONFIG_SYS_FSL_NUM_LAWS 12
36#define CONFIG_SYS_FSL_SEC_COMPAT 2
37
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]38#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]39#define CONFIG_MAX_CPUS 1
40#define CONFIG_SYS_FSL_NUM_LAWS 8
41
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]42#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]43#define CONFIG_MAX_CPUS 1
44#define CONFIG_SYS_FSL_NUM_LAWS 8
45#define CONFIG_SYS_FSL_SEC_COMPAT 2
46
47#elif defined(CONFIG_MPC8544)
48#define CONFIG_MAX_CPUS 1
49#define CONFIG_SYS_FSL_NUM_LAWS 10
50#define CONFIG_SYS_FSL_SEC_COMPAT 2
51
52#elif defined(CONFIG_MPC8548)
53#define CONFIG_MAX_CPUS 1
54#define CONFIG_SYS_FSL_NUM_LAWS 10
55#define CONFIG_SYS_FSL_SEC_COMPAT 2
56
57#elif defined(CONFIG_MPC8555)
58#define CONFIG_MAX_CPUS 1
59#define CONFIG_SYS_FSL_NUM_LAWS 8
60#define CONFIG_SYS_FSL_SEC_COMPAT 2
61
62#elif defined(CONFIG_MPC8560)
63#define CONFIG_MAX_CPUS 1
64#define CONFIG_SYS_FSL_NUM_LAWS 8
65
66#elif defined(CONFIG_MPC8568)
67#define CONFIG_MAX_CPUS 1
68#define CONFIG_SYS_FSL_NUM_LAWS 10
69#define CONFIG_SYS_FSL_SEC_COMPAT 2
70
71#elif defined(CONFIG_MPC8569)
72#define CONFIG_MAX_CPUS 1
73#define CONFIG_SYS_FSL_NUM_LAWS 10
74#define CONFIG_SYS_FSL_SEC_COMPAT 2
75
76#elif defined(CONFIG_MPC8572)
77#define CONFIG_MAX_CPUS 2
78#define CONFIG_SYS_FSL_NUM_LAWS 12
79#define CONFIG_SYS_FSL_SEC_COMPAT 2
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]80#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]81#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]82
83#elif defined(CONFIG_P1010)
84#define CONFIG_MAX_CPUS 1
85#define CONFIG_SYS_FSL_NUM_LAWS 12
86#define CONFIG_TSECV2
87#define CONFIG_SYS_FSL_SEC_COMPAT 4
88
89#elif defined(CONFIG_P1011)
90#define CONFIG_MAX_CPUS 1
91#define CONFIG_SYS_FSL_NUM_LAWS 12
92#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]93#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]94#define CONFIG_SYS_FSL_SEC_COMPAT 2
95
96#elif defined(CONFIG_P1012)
97#define CONFIG_MAX_CPUS 1
98#define CONFIG_SYS_FSL_NUM_LAWS 12
99#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]100#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]101#define CONFIG_SYS_FSL_SEC_COMPAT 2
102
103#elif defined(CONFIG_P1013)
104#define CONFIG_MAX_CPUS 1
105#define CONFIG_SYS_FSL_NUM_LAWS 12
106#define CONFIG_TSECV2
107#define CONFIG_SYS_FSL_SEC_COMPAT 2
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]108#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
109#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
110#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]111
112#elif defined(CONFIG_P1014)
113#define CONFIG_MAX_CPUS 1
114#define CONFIG_SYS_FSL_NUM_LAWS 12
115#define CONFIG_TSECV2
116#define CONFIG_SYS_FSL_SEC_COMPAT 4
117
118#elif defined(CONFIG_P1020)
119#define CONFIG_MAX_CPUS 2
120#define CONFIG_SYS_FSL_NUM_LAWS 12
121#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]122#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]123#define CONFIG_SYS_FSL_SEC_COMPAT 2
124
125#elif defined(CONFIG_P1021)
126#define CONFIG_MAX_CPUS 2
127#define CONFIG_SYS_FSL_NUM_LAWS 12
128#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]129#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]130#define CONFIG_SYS_FSL_SEC_COMPAT 2
131
132#elif defined(CONFIG_P1022)
133#define CONFIG_MAX_CPUS 2
134#define CONFIG_SYS_FSL_NUM_LAWS 12
135#define CONFIG_TSECV2
136#define CONFIG_SYS_FSL_SEC_COMPAT 2
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]137#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
138#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
139#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]140
141#elif defined(CONFIG_P2010)
142#define CONFIG_MAX_CPUS 1
143#define CONFIG_SYS_FSL_NUM_LAWS 12
144#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]145#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]146#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]147
148#elif defined(CONFIG_P2020)
149#define CONFIG_MAX_CPUS 2
150#define CONFIG_SYS_FSL_NUM_LAWS 12
151#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]152#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]153#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]154
155#elif defined(CONFIG_PPC_P2040)
156#define CONFIG_MAX_CPUS 4
157#define CONFIG_SYS_FSL_NUM_LAWS 32
158#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame^]159#define CONFIG_SYS_NUM_FMAN 1
160#define CONFIG_SYS_NUM_FM1_DTSEC 5
161#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]162
163#elif defined(CONFIG_PPC_P3041)
164#define CONFIG_MAX_CPUS 4
165#define CONFIG_SYS_FSL_NUM_LAWS 32
166#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame^]167#define CONFIG_SYS_NUM_FMAN 1
168#define CONFIG_SYS_NUM_FM1_DTSEC 5
169#define CONFIG_SYS_NUM_FM1_10GEC 1
170#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]171
172#elif defined(CONFIG_PPC_P4040)
173#define CONFIG_MAX_CPUS 4
174#define CONFIG_SYS_FSL_NUM_LAWS 32
175#define CONFIG_SYS_FSL_SEC_COMPAT 4
176
177#elif defined(CONFIG_PPC_P4080)
178#define CONFIG_MAX_CPUS 8
179#define CONFIG_SYS_FSL_NUM_LAWS 32
180#define CONFIG_SYS_FSL_SEC_COMPAT 4
181#define CONFIG_SYS_NUM_FMAN 2
182#define CONFIG_SYS_NUM_FM1_DTSEC 4
183#define CONFIG_SYS_NUM_FM2_DTSEC 4
184#define CONFIG_SYS_NUM_FM1_10GEC 1
185#define CONFIG_SYS_NUM_FM2_10GEC 1
186#define CONFIG_NUM_DDR_CONTROLLERS 2
187#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
188#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]189#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]190#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
191#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
192#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
193#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
194#define CONFIG_SYS_P4080_ERRATUM_CPU22
195#define CONFIG_SYS_P4080_ERRATUM_SERDES8
196
197#elif defined(CONFIG_PPC_P5010)
198#define CONFIG_MAX_CPUS 1
199#define CONFIG_SYS_FSL_NUM_LAWS 32
200#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame^]201#define CONFIG_SYS_NUM_FMAN 1
202#define CONFIG_SYS_NUM_FM1_DTSEC 5
203#define CONFIG_SYS_NUM_FM1_10GEC 1
204#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]205
206#elif defined(CONFIG_PPC_P5020)
207#define CONFIG_MAX_CPUS 2
208#define CONFIG_SYS_FSL_NUM_LAWS 32
209#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame^]210#define CONFIG_SYS_NUM_FMAN 1
211#define CONFIG_SYS_NUM_FM1_DTSEC 5
212#define CONFIG_SYS_NUM_FM1_10GEC 1
213#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]214
215#else
216#error Processor type not defined for this platform
217#endif
218
219#endif /* _ASM_MPC85xx_CONFIG_H_ */