commit 9a7b5a300cc8ab464710ec9d87a2e897a7ed2d88
author Timur Tabi <timur@freescale.com> Tue Oct 23 10:48:09 2012 +0000
committer Andy Fleming <afleming@freescale.com> Tue Nov 27 18:28:05 2012 -0600
tree 78119cc9a53c66b1458bfede5794dd041aeda6d6
parent 80f535bbc85356c609d6d652b68d306890205b2c

powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC

The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h.  This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.

Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot.  It's a holdover from the SDK.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

arch/powerpc/include/asm/config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 03baaee..6666d3d 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -449,6 +449,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 
 #elif defined(CONFIG_PPC_P5040)
+#define CONFIG_SYS_PPC64
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
@@ -472,7 +473,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 #define CONFIG_SYS_FSL_ERRATUM_A004699
-#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000