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git01.mediatek.com / filogic / uboot / 9941a22e7b5518192bf0e2b3eb19ee7f68674c1c / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: cfa5448b5eb9242ea2b709b73590fb5fd34a363e [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +0000[diff] [blame]2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]30/* Number of TLB CAM entries we have on FSL Book-E chips */
31#if defined(CONFIG_E500MC)
32#define CONFIG_SYS_NUM_TLBCAMS 64
33#elif defined(CONFIG_E500)
34#define CONFIG_SYS_NUM_TLBCAMS 16
35#endif
36
37#if defined(CONFIG_MPC8536)
38#define CONFIG_MAX_CPUS 1
39#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000[diff] [blame]40#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]41#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]42#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]43
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]44#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]45#define CONFIG_MAX_CPUS 1
46#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]47#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]48
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]49#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]50#define CONFIG_MAX_CPUS 1
51#define CONFIG_SYS_FSL_NUM_LAWS 8
52#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]53#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]54
55#elif defined(CONFIG_MPC8544)
56#define CONFIG_MAX_CPUS 1
57#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000[diff] [blame]58#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]59#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]60#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]61
62#elif defined(CONFIG_MPC8548)
63#define CONFIG_MAX_CPUS 1
64#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000[diff] [blame]65#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]66#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]67#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala866c6fa2011-09-16 09:54:30 -0500[diff] [blame]68#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Galaf3339d62011-10-03 08:37:57 -0500[diff] [blame]69#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500[diff] [blame]70#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]71#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
72#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
73#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
74#define CONFIG_SYS_FSL_RMU
75#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]76
77#elif defined(CONFIG_MPC8555)
78#define CONFIG_MAX_CPUS 1
79#define CONFIG_SYS_FSL_NUM_LAWS 8
80#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]81#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]82
83#elif defined(CONFIG_MPC8560)
84#define CONFIG_MAX_CPUS 1
85#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]86#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]87
88#elif defined(CONFIG_MPC8568)
89#define CONFIG_MAX_CPUS 1
90#define CONFIG_SYS_FSL_NUM_LAWS 10
91#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]92#define QE_MURAM_SIZE 0x10000UL
93#define MAX_QE_RISC 2
94#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]95#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]96#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
97#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
98#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
99#define CONFIG_SYS_FSL_RMU
100#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]101
102#elif defined(CONFIG_MPC8569)
103#define CONFIG_MAX_CPUS 1
104#define CONFIG_SYS_FSL_NUM_LAWS 10
105#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]106#define QE_MURAM_SIZE 0x20000UL
107#define MAX_QE_RISC 4
108#define QE_NUM_OF_SNUM 46
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]109#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]110#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
111#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
112#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
113#define CONFIG_SYS_FSL_RMU
114#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]115
116#elif defined(CONFIG_MPC8572)
117#define CONFIG_MAX_CPUS 2
118#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000[diff] [blame]119#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]120#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]121#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]122#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]123#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]124
125#elif defined(CONFIG_P1010)
126#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]127#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]128#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]129#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]130#define CONFIG_TSECV2
131#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]132#define CONFIG_FSL_SATA_V2
133#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
134#define CONFIG_NUM_DDR_CONTROLLERS 1
135#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]136#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]137#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]138#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]139#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]140#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]141
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]142/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]143#elif defined(CONFIG_P1011)
144#define CONFIG_MAX_CPUS 1
145#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]146#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]147#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]148#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]149#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]150#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]151#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
152#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]153
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]154/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]155#elif defined(CONFIG_P1012)
156#define CONFIG_MAX_CPUS 1
157#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]158#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]159#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]160#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]161#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]162#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]163#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
164#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]165#define QE_MURAM_SIZE 0x6000UL
166#define MAX_QE_RISC 1
167#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]168
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]169/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]170#elif defined(CONFIG_P1013)
171#define CONFIG_MAX_CPUS 1
172#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]173#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]174#define CONFIG_TSECV2
175#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]176#define CONFIG_FSL_SATA_V2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]177#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]178#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
179#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
180#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]181
182#elif defined(CONFIG_P1014)
183#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]184#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]185#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]186#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]187#define CONFIG_TSECV2
188#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]189#define CONFIG_FSL_SATA_V2
190#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
191#define CONFIG_NUM_DDR_CONTROLLERS 1
192#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]193#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]194#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]195#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]196#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]197
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]198/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]199#elif defined(CONFIG_P1017)
200#define CONFIG_MAX_CPUS 1
201#define CONFIG_SYS_FSL_NUM_LAWS 12
202#define CONFIG_SYS_FSL_SEC_COMPAT 4
203#define CONFIG_SYS_NUM_FMAN 1
204#define CONFIG_SYS_NUM_FM1_DTSEC 2
205#define CONFIG_NUM_DDR_CONTROLLERS 1
206#define CONFIG_SYS_QMAN_NUM_PORTALS 3
207#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]208#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]209#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]210#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]211
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]212#elif defined(CONFIG_P1020)
213#define CONFIG_MAX_CPUS 2
214#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]215#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]216#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]217#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]218#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]219#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]220#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
221#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]222
223#elif defined(CONFIG_P1021)
224#define CONFIG_MAX_CPUS 2
225#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]226#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]227#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]228#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]229#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]230#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]231#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
232#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]233#define QE_MURAM_SIZE 0x6000UL
234#define MAX_QE_RISC 1
235#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]236
237#elif defined(CONFIG_P1022)
238#define CONFIG_MAX_CPUS 2
239#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]240#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]241#define CONFIG_TSECV2
242#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]243#define CONFIG_FSL_SATA_V2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]244#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]245#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
246#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
247#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]248
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]249#elif defined(CONFIG_P1023)
250#define CONFIG_MAX_CPUS 2
251#define CONFIG_SYS_FSL_NUM_LAWS 12
252#define CONFIG_SYS_FSL_SEC_COMPAT 4
253#define CONFIG_SYS_NUM_FMAN 1
254#define CONFIG_SYS_NUM_FM1_DTSEC 2
255#define CONFIG_NUM_DDR_CONTROLLERS 1
256#define CONFIG_SYS_QMAN_NUM_PORTALS 3
257#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]258#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]259#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]260#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]261
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]262/* P1024 is lower end variant of P1020 */
263#elif defined(CONFIG_P1024)
264#define CONFIG_MAX_CPUS 2
265#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]266#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]267#define CONFIG_TSECV2
268#define CONFIG_FSL_PCIE_DISABLE_ASPM
269#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]270#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]271#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
272#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
273
274/* P1025 is lower end variant of P1021 */
275#elif defined(CONFIG_P1025)
276#define CONFIG_MAX_CPUS 2
277#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]278#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]279#define CONFIG_TSECV2
280#define CONFIG_FSL_PCIE_DISABLE_ASPM
281#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]282#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]283#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
284#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]285#define QE_MURAM_SIZE 0x6000UL
286#define MAX_QE_RISC 1
287#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]288
289/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]290#elif defined(CONFIG_P2010)
291#define CONFIG_MAX_CPUS 1
292#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]293#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]294#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]295#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]296#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]297#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]298
299#elif defined(CONFIG_P2020)
300#define CONFIG_MAX_CPUS 2
301#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]302#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]303#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]304#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]305#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]306#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]307#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
308#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
309#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
310#define CONFIG_SYS_FSL_RMU
311#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]312
Scott Wooda1ef48c2012-08-14 10:14:51 +0000[diff] [blame]313#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]314#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]315#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]316#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]317#define CONFIG_SYS_FSL_NUM_LAWS 32
318#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]319#define CONFIG_FSL_SATA_V2
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]320#define CONFIG_SYS_NUM_FMAN 1
321#define CONFIG_SYS_NUM_FM1_DTSEC 5
322#define CONFIG_SYS_NUM_FM1_10GEC 1
323#define CONFIG_NUM_DDR_CONTROLLERS 1
324#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
325#define CONFIG_SYS_FSL_TBCLK_DIV 32
326#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]327#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]328#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
329#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]330#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]331#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9ed88112012-05-07 07:26:47 +0000[diff] [blame]332#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]333#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]334#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]335#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
336#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
337#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000[diff] [blame]338#define CONFIG_SYS_FSL_ERRATUM_A004510
339#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
340#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
341#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang712b6622012-09-28 21:26:19 +0000[diff] [blame]342#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]343
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]344#elif defined(CONFIG_PPC_P3041)
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]345#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]346#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]347#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]348#define CONFIG_SYS_FSL_NUM_LAWS 32
349#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]350#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]351#define CONFIG_SYS_NUM_FMAN 1
352#define CONFIG_SYS_NUM_FM1_DTSEC 5
353#define CONFIG_SYS_NUM_FM1_10GEC 1
354#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]355#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]356#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]357#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]358#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]359#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
360#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]361#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]362#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun53155532012-08-08 18:04:53 +0000[diff] [blame]363#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]364#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]365#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]366#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
367#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
368#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000[diff] [blame]369#define CONFIG_SYS_FSL_ERRATUM_A004510
370#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
371#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
372#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang712b6622012-09-28 21:26:19 +0000[diff] [blame]373#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]374
Scott Wooda1ef48c2012-08-14 10:14:51 +0000[diff] [blame]375#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]376#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]377#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]378#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]379#define CONFIG_SYS_FSL_NUM_LAWS 32
380#define CONFIG_SYS_FSL_SEC_COMPAT 4
381#define CONFIG_SYS_NUM_FMAN 2
382#define CONFIG_SYS_NUM_FM1_DTSEC 4
383#define CONFIG_SYS_NUM_FM2_DTSEC 4
384#define CONFIG_SYS_NUM_FM1_10GEC 1
385#define CONFIG_SYS_NUM_FM2_10GEC 1
386#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]387#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]388#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]389#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]390#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]391#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
392#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]393#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]394#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
395#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
396#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R6191183659922012-09-18 09:50:08 +0000[diff] [blame]397#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]398#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun9ed88112012-05-07 07:26:47 +0000[diff] [blame]399#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]400#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]401#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500[diff] [blame]402#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500[diff] [blame]403#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]404#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]405#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]406#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
407#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
408#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
409#define CONFIG_SYS_FSL_RMU
410#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood80806962012-08-14 10:14:53 +0000[diff] [blame]411#define CONFIG_SYS_FSL_ERRATUM_A004510
412#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
413#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gang712b6622012-09-28 21:26:19 +0000[diff] [blame]414#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]415
Scott Wooda1ef48c2012-08-14 10:14:51 +0000[diff] [blame]416#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]417#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]418#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]419#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]420#define CONFIG_SYS_FSL_NUM_LAWS 32
421#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]422#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]423#define CONFIG_SYS_NUM_FMAN 1
424#define CONFIG_SYS_NUM_FM1_DTSEC 5
425#define CONFIG_SYS_NUM_FM1_10GEC 1
426#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]427#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]428#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]429#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]430#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]431#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
432#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]433#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]434#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]435#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]436#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
437#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
438#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000[diff] [blame]439#define CONFIG_SYS_FSL_ERRATUM_A004510
440#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
441#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gang712b6622012-09-28 21:26:19 +0000[diff] [blame]442#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]443
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]444#elif defined(CONFIG_PPC_P5040)
445#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
446#define CONFIG_MAX_CPUS 4
447#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
448#define CONFIG_SYS_FSL_NUM_LAWS 32
449#define CONFIG_SYS_FSL_SEC_COMPAT 4
450#define CONFIG_SYS_NUM_FMAN 2
451#define CONFIG_SYS_NUM_FM1_DTSEC 5
452#define CONFIG_SYS_NUM_FM1_10GEC 1
453#define CONFIG_SYS_NUM_FM2_DTSEC 5
454#define CONFIG_SYS_NUM_FM2_10GEC 1
455#define CONFIG_NUM_DDR_CONTROLLERS 2
456#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
457#define CONFIG_SYS_FSL_TBCLK_DIV 16
458#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
459#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
460#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
461#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
462#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
463#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
464#define CONFIG_SYS_FSL_ERRATUM_USB138
465#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
466#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
467#define CONFIG_SYS_FSL_ERRATUM_A004699
468#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
469#define CONFIG_SYS_FSL_ERRATUM_A004510
470#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
471#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
472
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +0000[diff] [blame]473#elif defined(CONFIG_BSC9131)
474#define CONFIG_MAX_CPUS 1
475#define CONFIG_FSL_SDHC_V2_3
476#define CONFIG_SYS_FSL_NUM_LAWS 12
477#define CONFIG_TSECV2
478#define CONFIG_SYS_FSL_SEC_COMPAT 4
479#define CONFIG_NUM_DDR_CONTROLLERS 1
480#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
481#define CONFIG_NAND_FSL_IFC
482#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
483#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
484
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame^]485#elif defined(CONFIG_PPC_T4240)
486#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
487#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
488#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
489#define CONFIG_MAX_CPUS 12
490#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
491#define CONFIG_SYS_FSL_NUM_LAWS 32
492#define CONFIG_SYS_FSL_SRDS_3
493#define CONFIG_SYS_FSL_SRDS_4
494#define CONFIG_SYS_FSL_SEC_COMPAT 4
495#define CONFIG_SYS_NUM_FMAN 2
496#define CONFIG_SYS_NUM_FM1_DTSEC 8
497#define CONFIG_SYS_NUM_FM1_10GEC 2
498#define CONFIG_SYS_NUM_FM2_DTSEC 8
499#define CONFIG_SYS_NUM_FM2_10GEC 2
500#define CONFIG_NUM_DDR_CONTROLLERS 3
501#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
502#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
503#define CONFIG_SYS_FSL_TBCLK_DIV 16
504#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
505#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
506#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
507#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
508#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
509#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
510#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
511#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
512
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]513#else
514#error Processor type not defined for this platform
515#endif
516
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]517#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
518#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
519#endif
520
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]521#endif /* _ASM_MPC85xx_CONFIG_H_ */