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git01.mediatek.com / filogic / uboot / f3339d6ae2a6c7f96a5f9970d27973a6bf76050c / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: fc78c58d036445289d44ab47459994946716d683 [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]30/* Number of TLB CAM entries we have on FSL Book-E chips */
31#if defined(CONFIG_E500MC)
32#define CONFIG_SYS_NUM_TLBCAMS 64
33#elif defined(CONFIG_E500)
34#define CONFIG_SYS_NUM_TLBCAMS 16
35#endif
36
37#if defined(CONFIG_MPC8536)
38#define CONFIG_MAX_CPUS 1
39#define CONFIG_SYS_FSL_NUM_LAWS 12
40#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]41#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]42
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]43#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]44#define CONFIG_MAX_CPUS 1
45#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]46#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]47
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]48#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]49#define CONFIG_MAX_CPUS 1
50#define CONFIG_SYS_FSL_NUM_LAWS 8
51#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]52#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]53
54#elif defined(CONFIG_MPC8544)
55#define CONFIG_MAX_CPUS 1
56#define CONFIG_SYS_FSL_NUM_LAWS 10
57#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]58#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]59
60#elif defined(CONFIG_MPC8548)
61#define CONFIG_MAX_CPUS 1
62#define CONFIG_SYS_FSL_NUM_LAWS 10
63#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]64#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala866c6fa2011-09-16 09:54:30 -0500[diff] [blame]65#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Galaf3339d62011-10-03 08:37:57 -0500[diff] [blame^]66#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]67
68#elif defined(CONFIG_MPC8555)
69#define CONFIG_MAX_CPUS 1
70#define CONFIG_SYS_FSL_NUM_LAWS 8
71#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]72#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]73
74#elif defined(CONFIG_MPC8560)
75#define CONFIG_MAX_CPUS 1
76#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]77#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]78
79#elif defined(CONFIG_MPC8568)
80#define CONFIG_MAX_CPUS 1
81#define CONFIG_SYS_FSL_NUM_LAWS 10
82#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]83#define QE_MURAM_SIZE 0x10000UL
84#define MAX_QE_RISC 2
85#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]86#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]87
88#elif defined(CONFIG_MPC8569)
89#define CONFIG_MAX_CPUS 1
90#define CONFIG_SYS_FSL_NUM_LAWS 10
91#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]92#define QE_MURAM_SIZE 0x20000UL
93#define MAX_QE_RISC 4
94#define QE_NUM_OF_SNUM 46
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]95#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]96
97#elif defined(CONFIG_MPC8572)
98#define CONFIG_MAX_CPUS 2
99#define CONFIG_SYS_FSL_NUM_LAWS 12
100#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]101#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]102#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]103#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]104
105#elif defined(CONFIG_P1010)
106#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]107#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]108#define CONFIG_SYS_FSL_NUM_LAWS 12
109#define CONFIG_TSECV2
110#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]111#define CONFIG_FSL_SATA_V2
112#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
113#define CONFIG_NUM_DDR_CONTROLLERS 1
114#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]115#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]116#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]117#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]118#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]119#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]120
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]121/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]122#elif defined(CONFIG_P1011)
123#define CONFIG_MAX_CPUS 1
124#define CONFIG_SYS_FSL_NUM_LAWS 12
125#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]126#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]127#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]128#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]129#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
130#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]131
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]132/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]133#elif defined(CONFIG_P1012)
134#define CONFIG_MAX_CPUS 1
135#define CONFIG_SYS_FSL_NUM_LAWS 12
136#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]137#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]138#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]139#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]140#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
141#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]142#define QE_MURAM_SIZE 0x6000UL
143#define MAX_QE_RISC 1
144#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]145
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]146/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]147#elif defined(CONFIG_P1013)
148#define CONFIG_MAX_CPUS 1
149#define CONFIG_SYS_FSL_NUM_LAWS 12
150#define CONFIG_TSECV2
151#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]152#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]153#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
154#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
155#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]156
157#elif defined(CONFIG_P1014)
158#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]159#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]160#define CONFIG_SYS_FSL_NUM_LAWS 12
161#define CONFIG_TSECV2
162#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]163#define CONFIG_FSL_SATA_V2
164#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
165#define CONFIG_NUM_DDR_CONTROLLERS 1
166#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]167#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]168#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]169#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]170#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]171
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]172/* P1015 is single core version of P1024 */
173#elif defined(CONFIG_P1015)
174#define CONFIG_MAX_CPUS 1
175#define CONFIG_SYS_FSL_NUM_LAWS 12
176#define CONFIG_TSECV2
177#define CONFIG_FSL_PCIE_DISABLE_ASPM
178#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]179#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]180#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
181#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
182
183/* P1016 is single core version of P1025 */
184#elif defined(CONFIG_P1016)
185#define CONFIG_MAX_CPUS 1
186#define CONFIG_SYS_FSL_NUM_LAWS 12
187#define CONFIG_TSECV2
188#define CONFIG_FSL_PCIE_DISABLE_ASPM
189#define CONFIG_SYS_FSL_SEC_COMPAT 2
190#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
191#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]192#define QE_MURAM_SIZE 0x6000UL
193#define MAX_QE_RISC 1
194#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]195#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]196
197/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]198#elif defined(CONFIG_P1017)
199#define CONFIG_MAX_CPUS 1
200#define CONFIG_SYS_FSL_NUM_LAWS 12
201#define CONFIG_SYS_FSL_SEC_COMPAT 4
202#define CONFIG_SYS_NUM_FMAN 1
203#define CONFIG_SYS_NUM_FM1_DTSEC 2
204#define CONFIG_NUM_DDR_CONTROLLERS 1
205#define CONFIG_SYS_QMAN_NUM_PORTALS 3
206#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]207#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]208#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]209#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]210
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]211#elif defined(CONFIG_P1020)
212#define CONFIG_MAX_CPUS 2
213#define CONFIG_SYS_FSL_NUM_LAWS 12
214#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]215#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]216#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]217#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]218#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
219#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]220
221#elif defined(CONFIG_P1021)
222#define CONFIG_MAX_CPUS 2
223#define CONFIG_SYS_FSL_NUM_LAWS 12
224#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]225#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]226#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]227#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]228#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
229#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]230#define QE_MURAM_SIZE 0x6000UL
231#define MAX_QE_RISC 1
232#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]233
234#elif defined(CONFIG_P1022)
235#define CONFIG_MAX_CPUS 2
236#define CONFIG_SYS_FSL_NUM_LAWS 12
237#define CONFIG_TSECV2
238#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]239#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]240#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
241#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
242#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]243
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]244#elif defined(CONFIG_P1023)
245#define CONFIG_MAX_CPUS 2
246#define CONFIG_SYS_FSL_NUM_LAWS 12
247#define CONFIG_SYS_FSL_SEC_COMPAT 4
248#define CONFIG_SYS_NUM_FMAN 1
249#define CONFIG_SYS_NUM_FM1_DTSEC 2
250#define CONFIG_NUM_DDR_CONTROLLERS 1
251#define CONFIG_SYS_QMAN_NUM_PORTALS 3
252#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]253#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]254#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]255#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]256
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]257/* P1024 is lower end variant of P1020 */
258#elif defined(CONFIG_P1024)
259#define CONFIG_MAX_CPUS 2
260#define CONFIG_SYS_FSL_NUM_LAWS 12
261#define CONFIG_TSECV2
262#define CONFIG_FSL_PCIE_DISABLE_ASPM
263#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]264#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]265#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
266#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
267
268/* P1025 is lower end variant of P1021 */
269#elif defined(CONFIG_P1025)
270#define CONFIG_MAX_CPUS 2
271#define CONFIG_SYS_FSL_NUM_LAWS 12
272#define CONFIG_TSECV2
273#define CONFIG_FSL_PCIE_DISABLE_ASPM
274#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]275#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]276#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
277#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]278#define QE_MURAM_SIZE 0x6000UL
279#define MAX_QE_RISC 1
280#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]281
282/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]283#elif defined(CONFIG_P2010)
284#define CONFIG_MAX_CPUS 1
285#define CONFIG_SYS_FSL_NUM_LAWS 12
286#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]287#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]288#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]289#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]290
291#elif defined(CONFIG_P2020)
292#define CONFIG_MAX_CPUS 2
293#define CONFIG_SYS_FSL_NUM_LAWS 12
294#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]295#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]296#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]297#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]298
299#elif defined(CONFIG_PPC_P2040)
300#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]301#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]302#define CONFIG_SYS_FSL_NUM_LAWS 32
303#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]304#define CONFIG_SYS_NUM_FMAN 1
305#define CONFIG_SYS_NUM_FM1_DTSEC 5
306#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]307#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]308#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]309#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]310#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]311#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
312#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]313#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]314#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]315
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]316#elif defined(CONFIG_PPC_P2041)
317#define CONFIG_MAX_CPUS 4
318#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
319#define CONFIG_SYS_FSL_NUM_LAWS 32
320#define CONFIG_SYS_FSL_SEC_COMPAT 4
321#define CONFIG_SYS_NUM_FMAN 1
322#define CONFIG_SYS_NUM_FM1_DTSEC 5
323#define CONFIG_SYS_NUM_FM1_10GEC 1
324#define CONFIG_NUM_DDR_CONTROLLERS 1
325#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
326#define CONFIG_SYS_FSL_TBCLK_DIV 32
327#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]328#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]329#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
330#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]331#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]332#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
333
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]334#elif defined(CONFIG_PPC_P3041)
335#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]336#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]337#define CONFIG_SYS_FSL_NUM_LAWS 32
338#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]339#define CONFIG_SYS_NUM_FMAN 1
340#define CONFIG_SYS_NUM_FM1_DTSEC 5
341#define CONFIG_SYS_NUM_FM1_10GEC 1
342#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]343#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]344#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]345#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]346#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]347#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
348#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]349#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]350#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]351
352#elif defined(CONFIG_PPC_P4040)
353#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]354#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]355#define CONFIG_SYS_FSL_NUM_LAWS 32
356#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]357#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]358#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]359#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]360#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]361
362#elif defined(CONFIG_PPC_P4080)
363#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]364#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]365#define CONFIG_SYS_FSL_NUM_LAWS 32
366#define CONFIG_SYS_FSL_SEC_COMPAT 4
367#define CONFIG_SYS_NUM_FMAN 2
368#define CONFIG_SYS_NUM_FM1_DTSEC 4
369#define CONFIG_SYS_NUM_FM2_DTSEC 4
370#define CONFIG_SYS_NUM_FM1_10GEC 1
371#define CONFIG_SYS_NUM_FM2_10GEC 1
372#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]373#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]374#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]375#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]376#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]377#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
378#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]379#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]380#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
381#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
382#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
383#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
384#define CONFIG_SYS_P4080_ERRATUM_CPU22
385#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]386#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500[diff] [blame]387#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500[diff] [blame]388#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]389
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]390/* P5010 is single core version of P5020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]391#elif defined(CONFIG_PPC_P5010)
392#define CONFIG_MAX_CPUS 1
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]393#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]394#define CONFIG_SYS_FSL_NUM_LAWS 32
395#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]396#define CONFIG_SYS_NUM_FMAN 1
397#define CONFIG_SYS_NUM_FM1_DTSEC 5
398#define CONFIG_SYS_NUM_FM1_10GEC 1
399#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]400#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]401#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]402#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]403#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]404#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
405#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]406#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]407#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]408
409#elif defined(CONFIG_PPC_P5020)
410#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]411#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]412#define CONFIG_SYS_FSL_NUM_LAWS 32
413#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]414#define CONFIG_SYS_NUM_FMAN 1
415#define CONFIG_SYS_NUM_FM1_DTSEC 5
416#define CONFIG_SYS_NUM_FM1_10GEC 1
417#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]418#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]419#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]420#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]421#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]422#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
423#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]424#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]425#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]426
427#else
428#error Processor type not defined for this platform
429#endif
430
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]431#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
432#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
433#endif
434
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]435#endif /* _ASM_MPC85xx_CONFIG_H_ */