Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 78deaa17f3e84f670bd0d6a4d1c5a4f0c83df1eb / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: 191629b6284ad5332070d111fd067df4b3a71ce9 [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]30/* Number of TLB CAM entries we have on FSL Book-E chips */
31#if defined(CONFIG_E500MC)
32#define CONFIG_SYS_NUM_TLBCAMS 64
33#elif defined(CONFIG_E500)
34#define CONFIG_SYS_NUM_TLBCAMS 16
35#endif
36
37#if defined(CONFIG_MPC8536)
38#define CONFIG_MAX_CPUS 1
39#define CONFIG_SYS_FSL_NUM_LAWS 12
40#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]41#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]42
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]43#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]44#define CONFIG_MAX_CPUS 1
45#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]46#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]47
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]48#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]49#define CONFIG_MAX_CPUS 1
50#define CONFIG_SYS_FSL_NUM_LAWS 8
51#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]52#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]53
54#elif defined(CONFIG_MPC8544)
55#define CONFIG_MAX_CPUS 1
56#define CONFIG_SYS_FSL_NUM_LAWS 10
57#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]58#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]59
60#elif defined(CONFIG_MPC8548)
61#define CONFIG_MAX_CPUS 1
62#define CONFIG_SYS_FSL_NUM_LAWS 10
63#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]64#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala866c6fa2011-09-16 09:54:30 -0500[diff] [blame]65#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Galaf3339d62011-10-03 08:37:57 -0500[diff] [blame]66#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500[diff] [blame]67#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]68#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
69#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
70#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
71#define CONFIG_SYS_FSL_RMU
72#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]73
74#elif defined(CONFIG_MPC8555)
75#define CONFIG_MAX_CPUS 1
76#define CONFIG_SYS_FSL_NUM_LAWS 8
77#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]78#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]79
80#elif defined(CONFIG_MPC8560)
81#define CONFIG_MAX_CPUS 1
82#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]83#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]84
85#elif defined(CONFIG_MPC8568)
86#define CONFIG_MAX_CPUS 1
87#define CONFIG_SYS_FSL_NUM_LAWS 10
88#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]89#define QE_MURAM_SIZE 0x10000UL
90#define MAX_QE_RISC 2
91#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]92#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]93#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
94#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
95#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
96#define CONFIG_SYS_FSL_RMU
97#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]98
99#elif defined(CONFIG_MPC8569)
100#define CONFIG_MAX_CPUS 1
101#define CONFIG_SYS_FSL_NUM_LAWS 10
102#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]103#define QE_MURAM_SIZE 0x20000UL
104#define MAX_QE_RISC 4
105#define QE_NUM_OF_SNUM 46
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]106#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]107#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
108#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
109#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
110#define CONFIG_SYS_FSL_RMU
111#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]112
113#elif defined(CONFIG_MPC8572)
114#define CONFIG_MAX_CPUS 2
115#define CONFIG_SYS_FSL_NUM_LAWS 12
116#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]117#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]118#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]119#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]120
121#elif defined(CONFIG_P1010)
122#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]123#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]124#define CONFIG_SYS_FSL_NUM_LAWS 12
125#define CONFIG_TSECV2
126#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]127#define CONFIG_FSL_SATA_V2
128#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
129#define CONFIG_NUM_DDR_CONTROLLERS 1
130#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]131#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]132#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]133#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]134#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]135#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]136
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]137/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]138#elif defined(CONFIG_P1011)
139#define CONFIG_MAX_CPUS 1
140#define CONFIG_SYS_FSL_NUM_LAWS 12
141#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]142#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]143#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]144#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]145#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
146#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]147
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]148/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]149#elif defined(CONFIG_P1012)
150#define CONFIG_MAX_CPUS 1
151#define CONFIG_SYS_FSL_NUM_LAWS 12
152#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]153#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]154#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]155#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]156#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
157#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]158#define QE_MURAM_SIZE 0x6000UL
159#define MAX_QE_RISC 1
160#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]161
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]162/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]163#elif defined(CONFIG_P1013)
164#define CONFIG_MAX_CPUS 1
165#define CONFIG_SYS_FSL_NUM_LAWS 12
166#define CONFIG_TSECV2
167#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]168#define CONFIG_FSL_SATA_V2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]169#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]170#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
171#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
172#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]173
174#elif defined(CONFIG_P1014)
175#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]176#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]177#define CONFIG_SYS_FSL_NUM_LAWS 12
178#define CONFIG_TSECV2
179#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]180#define CONFIG_FSL_SATA_V2
181#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
182#define CONFIG_NUM_DDR_CONTROLLERS 1
183#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]184#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]185#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]186#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]187#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]188
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]189/* P1015 is single core version of P1024 */
190#elif defined(CONFIG_P1015)
191#define CONFIG_MAX_CPUS 1
192#define CONFIG_SYS_FSL_NUM_LAWS 12
193#define CONFIG_TSECV2
194#define CONFIG_FSL_PCIE_DISABLE_ASPM
195#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]196#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]197#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
198#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
199
200/* P1016 is single core version of P1025 */
201#elif defined(CONFIG_P1016)
202#define CONFIG_MAX_CPUS 1
203#define CONFIG_SYS_FSL_NUM_LAWS 12
204#define CONFIG_TSECV2
205#define CONFIG_FSL_PCIE_DISABLE_ASPM
206#define CONFIG_SYS_FSL_SEC_COMPAT 2
207#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
208#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]209#define QE_MURAM_SIZE 0x6000UL
210#define MAX_QE_RISC 1
211#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]212#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]213
214/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]215#elif defined(CONFIG_P1017)
216#define CONFIG_MAX_CPUS 1
217#define CONFIG_SYS_FSL_NUM_LAWS 12
218#define CONFIG_SYS_FSL_SEC_COMPAT 4
219#define CONFIG_SYS_NUM_FMAN 1
220#define CONFIG_SYS_NUM_FM1_DTSEC 2
221#define CONFIG_NUM_DDR_CONTROLLERS 1
222#define CONFIG_SYS_QMAN_NUM_PORTALS 3
223#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]224#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]225#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]226#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]227
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]228#elif defined(CONFIG_P1020)
229#define CONFIG_MAX_CPUS 2
230#define CONFIG_SYS_FSL_NUM_LAWS 12
231#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]232#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]233#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]234#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]235#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
236#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]237
238#elif defined(CONFIG_P1021)
239#define CONFIG_MAX_CPUS 2
240#define CONFIG_SYS_FSL_NUM_LAWS 12
241#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]242#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]243#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]244#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]245#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
246#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]247#define QE_MURAM_SIZE 0x6000UL
248#define MAX_QE_RISC 1
249#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]250
251#elif defined(CONFIG_P1022)
252#define CONFIG_MAX_CPUS 2
253#define CONFIG_SYS_FSL_NUM_LAWS 12
254#define CONFIG_TSECV2
255#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]256#define CONFIG_FSL_SATA_V2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]257#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]258#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
259#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
260#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]261
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]262#elif defined(CONFIG_P1023)
263#define CONFIG_MAX_CPUS 2
264#define CONFIG_SYS_FSL_NUM_LAWS 12
265#define CONFIG_SYS_FSL_SEC_COMPAT 4
266#define CONFIG_SYS_NUM_FMAN 1
267#define CONFIG_SYS_NUM_FM1_DTSEC 2
268#define CONFIG_NUM_DDR_CONTROLLERS 1
269#define CONFIG_SYS_QMAN_NUM_PORTALS 3
270#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]271#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]272#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]273#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]274
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]275/* P1024 is lower end variant of P1020 */
276#elif defined(CONFIG_P1024)
277#define CONFIG_MAX_CPUS 2
278#define CONFIG_SYS_FSL_NUM_LAWS 12
279#define CONFIG_TSECV2
280#define CONFIG_FSL_PCIE_DISABLE_ASPM
281#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]282#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]283#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
284#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
285
286/* P1025 is lower end variant of P1021 */
287#elif defined(CONFIG_P1025)
288#define CONFIG_MAX_CPUS 2
289#define CONFIG_SYS_FSL_NUM_LAWS 12
290#define CONFIG_TSECV2
291#define CONFIG_FSL_PCIE_DISABLE_ASPM
292#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]293#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]294#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
295#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]296#define QE_MURAM_SIZE 0x6000UL
297#define MAX_QE_RISC 1
298#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]299
300/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]301#elif defined(CONFIG_P2010)
302#define CONFIG_MAX_CPUS 1
303#define CONFIG_SYS_FSL_NUM_LAWS 12
304#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]305#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]306#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]307#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]308
309#elif defined(CONFIG_P2020)
310#define CONFIG_MAX_CPUS 2
311#define CONFIG_SYS_FSL_NUM_LAWS 12
312#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]313#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]314#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]315#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]316#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
317#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
318#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
319#define CONFIG_SYS_FSL_RMU
320#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]321
322#elif defined(CONFIG_PPC_P2040)
323#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]324#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]325#define CONFIG_SYS_FSL_NUM_LAWS 32
326#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]327#define CONFIG_SYS_NUM_FMAN 1
328#define CONFIG_SYS_NUM_FM1_DTSEC 5
329#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]330#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]331#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]332#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]333#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]334#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
335#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]336#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]337#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]338#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]339#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]340#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
341#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
342#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]343
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]344#elif defined(CONFIG_PPC_P2041)
345#define CONFIG_MAX_CPUS 4
346#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
347#define CONFIG_SYS_FSL_NUM_LAWS 32
348#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]349#define CONFIG_FSL_SATA_V2
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]350#define CONFIG_SYS_NUM_FMAN 1
351#define CONFIG_SYS_NUM_FM1_DTSEC 5
352#define CONFIG_SYS_NUM_FM1_10GEC 1
353#define CONFIG_NUM_DDR_CONTROLLERS 1
354#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
355#define CONFIG_SYS_FSL_TBCLK_DIV 32
356#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]357#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]358#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
359#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]360#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]361#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]362#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]363#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]364#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
365#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
366#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]367
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]368#elif defined(CONFIG_PPC_P3041)
369#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]370#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]371#define CONFIG_SYS_FSL_NUM_LAWS 32
372#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]373#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]374#define CONFIG_SYS_NUM_FMAN 1
375#define CONFIG_SYS_NUM_FM1_DTSEC 5
376#define CONFIG_SYS_NUM_FM1_10GEC 1
377#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]378#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]379#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]380#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]381#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]382#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
383#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]384#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]385#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]386#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]387#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]388#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
389#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
390#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]391
Shengzhou Liu8b033cf2011-08-31 17:48:18 +0800[diff] [blame]392#elif defined(CONFIG_PPC_P3060)
393#define CONFIG_MAX_CPUS 8
394#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
395#define CONFIG_SYS_FSL_NUM_LAWS 32
396#define CONFIG_SYS_FSL_SEC_COMPAT 4
397#define CONFIG_SYS_NUM_FMAN 2
398#define CONFIG_SYS_NUM_FM1_DTSEC 4
399#define CONFIG_SYS_NUM_FM2_DTSEC 4
400#define CONFIG_NUM_DDR_CONTROLLERS 1
401#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
402#define CONFIG_SYS_FSL_TBCLK_DIV 16
403#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
404#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
405#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]406#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]407#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
408#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
409#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Shengzhou Liu8b033cf2011-08-31 17:48:18 +0800[diff] [blame]410
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]411#elif defined(CONFIG_PPC_P4040)
412#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]413#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]414#define CONFIG_SYS_FSL_NUM_LAWS 32
415#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]416#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]417#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]418#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]419#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]420#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]421#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]422#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
423#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
424#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]425
426#elif defined(CONFIG_PPC_P4080)
427#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]428#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]429#define CONFIG_SYS_FSL_NUM_LAWS 32
430#define CONFIG_SYS_FSL_SEC_COMPAT 4
431#define CONFIG_SYS_NUM_FMAN 2
432#define CONFIG_SYS_NUM_FM1_DTSEC 4
433#define CONFIG_SYS_NUM_FM2_DTSEC 4
434#define CONFIG_SYS_NUM_FM1_10GEC 1
435#define CONFIG_SYS_NUM_FM2_10GEC 1
436#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]437#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]438#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]439#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]440#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]441#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
442#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]443#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]444#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
445#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
446#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
447#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
448#define CONFIG_SYS_P4080_ERRATUM_CPU22
449#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]450#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500[diff] [blame]451#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500[diff] [blame]452#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]453#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]454#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]455#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
456#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
457#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
458#define CONFIG_SYS_FSL_RMU
459#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]460
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]461/* P5010 is single core version of P5020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]462#elif defined(CONFIG_PPC_P5010)
463#define CONFIG_MAX_CPUS 1
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]464#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]465#define CONFIG_SYS_FSL_NUM_LAWS 32
466#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]467#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]468#define CONFIG_SYS_NUM_FMAN 1
469#define CONFIG_SYS_NUM_FM1_DTSEC 5
470#define CONFIG_SYS_NUM_FM1_10GEC 1
471#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]472#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]473#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]474#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]475#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]476#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
477#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]478#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]479#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]480#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]481#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
482#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
483#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]484
485#elif defined(CONFIG_PPC_P5020)
486#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]487#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]488#define CONFIG_SYS_FSL_NUM_LAWS 32
489#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600[diff] [blame]490#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]491#define CONFIG_SYS_NUM_FMAN 1
492#define CONFIG_SYS_NUM_FM1_DTSEC 5
493#define CONFIG_SYS_NUM_FM1_10GEC 1
494#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]495#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]496#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]497#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]498#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]499#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
500#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]501#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]502#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]503#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame^]504#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
505#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
506#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]507
508#else
509#error Processor type not defined for this platform
510#endif
511
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]512#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
513#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
514#endif
515
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]516#endif /* _ASM_MPC85xx_CONFIG_H_ */