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git01.mediatek.com / filogic / uboot / 248865e0205964aadf7513eee91c309a30b92efe / . / arch / powerpc / include / asm / config_mpc85xx.h
blob: f957fa3758b09dc1328585f512a83f2a9a32d731 [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]1/*
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +0000[diff] [blame]2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]26#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
York Sunf066a042012-10-28 08:12:54 +0000[diff] [blame]30/*
31 * This macro should be removed when we no longer care about backwards
32 * compatibility with older operating systems.
33 */
34#define CONFIG_PPC_SPINTABLE_COMPATIBLE
35
York Sun7d69ea32012-10-08 07:44:22 +0000[diff] [blame]36#define FSL_DDR_VER_4_7 47
37
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]38/* Number of TLB CAM entries we have on FSL Book-E chips */
39#if defined(CONFIG_E500MC)
40#define CONFIG_SYS_NUM_TLBCAMS 64
41#elif defined(CONFIG_E500)
42#define CONFIG_SYS_NUM_TLBCAMS 16
43#endif
44
45#if defined(CONFIG_MPC8536)
46#define CONFIG_MAX_CPUS 1
47#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000[diff] [blame]48#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]49#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]50#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]51
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]52#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]53#define CONFIG_MAX_CPUS 1
54#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]55#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]56
Wolfgang Denka4de8352011-02-02 22:36:10 +0100[diff] [blame]57#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]58#define CONFIG_MAX_CPUS 1
59#define CONFIG_SYS_FSL_NUM_LAWS 8
60#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]61#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]62
63#elif defined(CONFIG_MPC8544)
64#define CONFIG_MAX_CPUS 1
65#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000[diff] [blame]66#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]67#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]68#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]69
70#elif defined(CONFIG_MPC8548)
71#define CONFIG_MAX_CPUS 1
72#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000[diff] [blame]73#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]74#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]75#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala866c6fa2011-09-16 09:54:30 -0500[diff] [blame]76#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Galaf3339d62011-10-03 08:37:57 -0500[diff] [blame]77#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoc8caa8a2011-10-03 08:38:50 -0500[diff] [blame]78#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]79#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
80#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
81#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
82#define CONFIG_SYS_FSL_RMU
83#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]84
85#elif defined(CONFIG_MPC8555)
86#define CONFIG_MAX_CPUS 1
87#define CONFIG_SYS_FSL_NUM_LAWS 8
88#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]89#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]90
91#elif defined(CONFIG_MPC8560)
92#define CONFIG_MAX_CPUS 1
93#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]94#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]95
96#elif defined(CONFIG_MPC8568)
97#define CONFIG_MAX_CPUS 1
98#define CONFIG_SYS_FSL_NUM_LAWS 10
99#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]100#define QE_MURAM_SIZE 0x10000UL
101#define MAX_QE_RISC 2
102#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]103#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]104#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
105#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
106#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
107#define CONFIG_SYS_FSL_RMU
108#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]109
110#elif defined(CONFIG_MPC8569)
111#define CONFIG_MAX_CPUS 1
112#define CONFIG_SYS_FSL_NUM_LAWS 10
113#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600[diff] [blame]114#define QE_MURAM_SIZE 0x20000UL
115#define MAX_QE_RISC 4
116#define QE_NUM_OF_SNUM 46
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]117#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]118#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
119#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
120#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
121#define CONFIG_SYS_FSL_RMU
122#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]123
124#elif defined(CONFIG_MPC8572)
125#define CONFIG_MAX_CPUS 2
126#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000[diff] [blame]127#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]128#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]129#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9aa857b2011-01-25 21:51:27 -0800[diff] [blame]130#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800[diff] [blame]131#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]132
133#elif defined(CONFIG_P1010)
134#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]135#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]136#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]137#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]138#define CONFIG_TSECV2
139#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]140#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
141#define CONFIG_NUM_DDR_CONTROLLERS 1
142#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]143#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]144#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]145#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]146#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]147#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]148
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]149/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]150#elif defined(CONFIG_P1011)
151#define CONFIG_MAX_CPUS 1
152#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]153#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]154#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]155#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]156#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]157#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]158#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
159#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]160
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]161/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]162#elif defined(CONFIG_P1012)
163#define CONFIG_MAX_CPUS 1
164#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]165#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]166#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]167#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]168#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]169#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]170#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
171#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]172#define QE_MURAM_SIZE 0x6000UL
173#define MAX_QE_RISC 1
174#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]175
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]176/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]177#elif defined(CONFIG_P1013)
178#define CONFIG_MAX_CPUS 1
179#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]180#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]181#define CONFIG_TSECV2
182#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]183#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]184#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
185#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
186#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]187
188#elif defined(CONFIG_P1014)
189#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530[diff] [blame]190#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]191#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]192#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]193#define CONFIG_TSECV2
194#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530[diff] [blame]195#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
196#define CONFIG_NUM_DDR_CONTROLLERS 1
197#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530[diff] [blame]198#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500[diff] [blame]199#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530[diff] [blame]200#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530[diff] [blame]201#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]202
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]203/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]204#elif defined(CONFIG_P1017)
205#define CONFIG_MAX_CPUS 1
206#define CONFIG_SYS_FSL_NUM_LAWS 12
207#define CONFIG_SYS_FSL_SEC_COMPAT 4
208#define CONFIG_SYS_NUM_FMAN 1
209#define CONFIG_SYS_NUM_FM1_DTSEC 2
210#define CONFIG_NUM_DDR_CONTROLLERS 1
211#define CONFIG_SYS_QMAN_NUM_PORTALS 3
212#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]213#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]214#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]215#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]216
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]217#elif defined(CONFIG_P1020)
218#define CONFIG_MAX_CPUS 2
219#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]220#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]221#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]222#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]223#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]224#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]225#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
226#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]227
228#elif defined(CONFIG_P1021)
229#define CONFIG_MAX_CPUS 2
230#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]231#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]232#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000[diff] [blame]233#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]234#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]235#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]236#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
237#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]238#define QE_MURAM_SIZE 0x6000UL
239#define MAX_QE_RISC 1
240#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]241
242#elif defined(CONFIG_P1022)
243#define CONFIG_MAX_CPUS 2
244#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]245#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]246#define CONFIG_TSECV2
247#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]248#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600[diff] [blame]249#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
250#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
251#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]252
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]253#elif defined(CONFIG_P1023)
254#define CONFIG_MAX_CPUS 2
255#define CONFIG_SYS_FSL_NUM_LAWS 12
256#define CONFIG_SYS_FSL_SEC_COMPAT 4
257#define CONFIG_SYS_NUM_FMAN 1
258#define CONFIG_SYS_NUM_FM1_DTSEC 2
259#define CONFIG_NUM_DDR_CONTROLLERS 1
260#define CONFIG_SYS_QMAN_NUM_PORTALS 3
261#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]262#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]263#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]264#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600[diff] [blame]265
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]266/* P1024 is lower end variant of P1020 */
267#elif defined(CONFIG_P1024)
268#define CONFIG_MAX_CPUS 2
269#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]270#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]271#define CONFIG_TSECV2
272#define CONFIG_FSL_PCIE_DISABLE_ASPM
273#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]274#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]275#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
276#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
277
278/* P1025 is lower end variant of P1021 */
279#elif defined(CONFIG_P1025)
280#define CONFIG_MAX_CPUS 2
281#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]282#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]283#define CONFIG_TSECV2
284#define CONFIG_FSL_PCIE_DISABLE_ASPM
285#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]286#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]287#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
288#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600[diff] [blame]289#define QE_MURAM_SIZE 0x6000UL
290#define MAX_QE_RISC 1
291#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600[diff] [blame]292
293/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]294#elif defined(CONFIG_P2010)
295#define CONFIG_MAX_CPUS 1
296#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]297#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]298#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]299#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]300#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]301#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]302
303#elif defined(CONFIG_P2020)
304#define CONFIG_MAX_CPUS 2
305#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000[diff] [blame]306#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]307#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]308#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600[diff] [blame]309#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600[diff] [blame]310#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]311#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
312#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
313#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
314#define CONFIG_SYS_FSL_RMU
315#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]316
Scott Wooda1ef48c2012-08-14 10:14:51 +0000[diff] [blame]317#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]318#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]319#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]320#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]321#define CONFIG_SYS_FSL_NUM_LAWS 32
322#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]323#define CONFIG_SYS_NUM_FMAN 1
324#define CONFIG_SYS_NUM_FM1_DTSEC 5
325#define CONFIG_SYS_NUM_FM1_10GEC 1
326#define CONFIG_NUM_DDR_CONTROLLERS 1
327#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
328#define CONFIG_SYS_FSL_TBCLK_DIV 32
329#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]330#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]331#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
332#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]333#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]334#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9ed88112012-05-07 07:26:47 +0000[diff] [blame]335#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]336#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]337#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang558359a2012-10-14 20:55:17 +0000[diff] [blame]338#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]339#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
340#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
341#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000[diff] [blame]342#define CONFIG_SYS_FSL_ERRATUM_A004510
343#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
344#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
345#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang712b6622012-09-28 21:26:19 +0000[diff] [blame]346#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabie3ab8c12012-10-25 12:40:00 +0000[diff] [blame]347#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala619541b2011-05-13 01:16:07 -0500[diff] [blame]348
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]349#elif defined(CONFIG_PPC_P3041)
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]350#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]351#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]352#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]353#define CONFIG_SYS_FSL_NUM_LAWS 32
354#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]355#define CONFIG_SYS_NUM_FMAN 1
356#define CONFIG_SYS_NUM_FM1_DTSEC 5
357#define CONFIG_SYS_NUM_FM1_10GEC 1
358#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]359#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]360#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]361#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]362#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]363#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
364#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]365#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]366#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun53155532012-08-08 18:04:53 +0000[diff] [blame]367#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]368#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]369#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang558359a2012-10-14 20:55:17 +0000[diff] [blame]370#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]371#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
372#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
373#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000[diff] [blame]374#define CONFIG_SYS_FSL_ERRATUM_A004510
375#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
376#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
377#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang712b6622012-09-28 21:26:19 +0000[diff] [blame]378#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabie3ab8c12012-10-25 12:40:00 +0000[diff] [blame]379#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]380
Scott Wooda1ef48c2012-08-14 10:14:51 +0000[diff] [blame]381#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]382#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]383#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]384#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]385#define CONFIG_SYS_FSL_NUM_LAWS 32
386#define CONFIG_SYS_FSL_SEC_COMPAT 4
387#define CONFIG_SYS_NUM_FMAN 2
388#define CONFIG_SYS_NUM_FM1_DTSEC 4
389#define CONFIG_SYS_NUM_FM2_DTSEC 4
390#define CONFIG_SYS_NUM_FM1_10GEC 1
391#define CONFIG_SYS_NUM_FM2_10GEC 1
392#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]393#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]394#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]395#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]396#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]397#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
398#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000[diff] [blame]399#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]400#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
401#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
402#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R6191183659922012-09-18 09:50:08 +0000[diff] [blame]403#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]404#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun9ed88112012-05-07 07:26:47 +0000[diff] [blame]405#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]406#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]407#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500[diff] [blame]408#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500[diff] [blame]409#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala945e59a2011-11-22 06:51:15 -0600[diff] [blame]410#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]411#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang558359a2012-10-14 20:55:17 +0000[diff] [blame]412#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]413#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
414#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
415#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
416#define CONFIG_SYS_FSL_RMU
417#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood80806962012-08-14 10:14:53 +0000[diff] [blame]418#define CONFIG_SYS_FSL_ERRATUM_A004510
419#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
420#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gang712b6622012-09-28 21:26:19 +0000[diff] [blame]421#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabie3ab8c12012-10-25 12:40:00 +0000[diff] [blame]422#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabic5355dd2012-11-01 08:20:23 +0000[diff] [blame]423#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chenc48234e2012-11-26 23:49:45 +0000[diff] [blame]424#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]425
Scott Wooda1ef48c2012-08-14 10:14:51 +0000[diff] [blame]426#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sun2394a0f2012-10-08 07:44:30 +0000[diff] [blame]427#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]428#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]429#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600[diff] [blame]430#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]431#define CONFIG_SYS_FSL_NUM_LAWS 32
432#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala60d95d82011-01-25 12:42:32 -0600[diff] [blame]433#define CONFIG_SYS_NUM_FMAN 1
434#define CONFIG_SYS_NUM_FM1_DTSEC 5
435#define CONFIG_SYS_NUM_FM1_10GEC 1
436#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600[diff] [blame]437#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600[diff] [blame]438#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500[diff] [blame]439#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]440#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500[diff] [blame]441#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
442#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500[diff] [blame]443#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800[diff] [blame]444#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sundf2be192011-11-20 10:01:35 -0800[diff] [blame]445#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang558359a2012-10-14 20:55:17 +0000[diff] [blame]446#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang78deaa12012-03-08 00:33:14 +0000[diff] [blame]447#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
448#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
449#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000[diff] [blame]450#define CONFIG_SYS_FSL_ERRATUM_A004510
451#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
452#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gang712b6622012-09-28 21:26:19 +0000[diff] [blame]453#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]454
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]455#elif defined(CONFIG_PPC_P5040)
Timur Tabi9a7b5a32012-10-23 10:48:09 +0000[diff] [blame]456#define CONFIG_SYS_PPC64
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]457#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
458#define CONFIG_MAX_CPUS 4
459#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
460#define CONFIG_SYS_FSL_NUM_LAWS 32
461#define CONFIG_SYS_FSL_SEC_COMPAT 4
462#define CONFIG_SYS_NUM_FMAN 2
463#define CONFIG_SYS_NUM_FM1_DTSEC 5
464#define CONFIG_SYS_NUM_FM1_10GEC 1
465#define CONFIG_SYS_NUM_FM2_DTSEC 5
466#define CONFIG_SYS_NUM_FM2_10GEC 1
467#define CONFIG_NUM_DDR_CONTROLLERS 2
468#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
469#define CONFIG_SYS_FSL_TBCLK_DIV 16
470#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
471#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
472#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
473#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
474#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
475#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
476#define CONFIG_SYS_FSL_ERRATUM_USB138
477#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
478#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
479#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabid5e13882012-10-05 11:09:19 +0000[diff] [blame]480#define CONFIG_SYS_FSL_ERRATUM_A004510
481#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
482#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
483
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +0000[diff] [blame]484#elif defined(CONFIG_BSC9131)
485#define CONFIG_MAX_CPUS 1
486#define CONFIG_FSL_SDHC_V2_3
487#define CONFIG_SYS_FSL_NUM_LAWS 12
488#define CONFIG_TSECV2
489#define CONFIG_SYS_FSL_SEC_COMPAT 4
490#define CONFIG_NUM_DDR_CONTROLLERS 1
491#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
492#define CONFIG_NAND_FSL_IFC
493#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
494#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
495
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]496#elif defined(CONFIG_PPC_T4240)
York Sun2394a0f2012-10-08 07:44:30 +0000[diff] [blame]497#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]498#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
499#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
500#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
501#define CONFIG_MAX_CPUS 12
502#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
503#define CONFIG_SYS_FSL_NUM_LAWS 32
504#define CONFIG_SYS_FSL_SRDS_3
505#define CONFIG_SYS_FSL_SRDS_4
506#define CONFIG_SYS_FSL_SEC_COMPAT 4
507#define CONFIG_SYS_NUM_FMAN 2
508#define CONFIG_SYS_NUM_FM1_DTSEC 8
509#define CONFIG_SYS_NUM_FM1_10GEC 2
510#define CONFIG_SYS_NUM_FM2_DTSEC 8
511#define CONFIG_SYS_NUM_FM2_10GEC 2
512#define CONFIG_NUM_DDR_CONTROLLERS 3
513#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zangbafd8032012-10-08 07:44:21 +0000[diff] [blame]514#define CONFIG_SYS_FMAN_V3
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]515#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
516#define CONFIG_SYS_FSL_TBCLK_DIV 16
517#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
518#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
519#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
520#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
521#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
522#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
523#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
York Suna28496f2012-10-08 07:44:25 +0000[diff] [blame]524#define CONFIG_SYS_FSL_ERRATUM_A004468
York Sun6995a022012-10-08 07:44:26 +0000[diff] [blame]525#define CONFIG_SYS_FSL_ERRATUM_A_004934
York Sun9941a222012-10-08 07:44:19 +0000[diff] [blame]526#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
527
Poonam Aggrwal248865e2012-12-23 19:24:16 +0000[diff] [blame^]528#elif defined(CONFIG_PPC_B4420)
529#define CONFIG_SYS_PPC64 /* 64-bit core */
530#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
531#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
532#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
533#define CONFIG_MAX_CPUS 2
534#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
535#define CONFIG_SYS_FSL_NUM_LAWS 32
536#define CONFIG_SYS_FSL_SEC_COMPAT 4
537#define CONFIG_SYS_NUM_FMAN 1
538#define CONFIG_SYS_NUM_FM1_DTSEC 4
539#define CONFIG_NUM_DDR_CONTROLLERS 1
540#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
541#define CONFIG_SYS_FMAN_V3
542#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
543#define CONFIG_SYS_FSL_TBCLK_DIV 16
544#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
545#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
546#define CONFIG_SYS_FSL_ERRATUM_A_004934
547#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
548
York Sunbcf7b3d2012-10-08 07:44:20 +0000[diff] [blame]549#elif defined(CONFIG_PPC_B4860)
York Sun2394a0f2012-10-08 07:44:30 +0000[diff] [blame]550#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sunbcf7b3d2012-10-08 07:44:20 +0000[diff] [blame]551#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
552#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
553#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
554#define CONFIG_MAX_CPUS 4
555#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
556#define CONFIG_SYS_FSL_NUM_LAWS 32
557#define CONFIG_SYS_FSL_SEC_COMPAT 4
558#define CONFIG_SYS_NUM_FMAN 1
559#define CONFIG_SYS_NUM_FM1_DTSEC 6
560#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwal1c859552012-12-23 19:22:33 +0000[diff] [blame]561#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sunbcf7b3d2012-10-08 07:44:20 +0000[diff] [blame]562#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zangbafd8032012-10-08 07:44:21 +0000[diff] [blame]563#define CONFIG_SYS_FMAN_V3
York Sunbcf7b3d2012-10-08 07:44:20 +0000[diff] [blame]564#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
565#define CONFIG_SYS_FSL_TBCLK_DIV 16
566#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
567#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
568#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
569#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
570#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
571#define CONFIG_SYS_FSL_ERRATUM_A_004934
572#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
573
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]574#else
575#error Processor type not defined for this platform
576#endif
577
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]578#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
579#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
580#endif
581
Kumar Galafe137112011-01-19 03:05:26 -0600[diff] [blame]582#endif /* _ASM_MPC85xx_CONFIG_H_ */