blob: d1c1e0681acab512c332c450e5184c55bc71d126 [file] [log] [blame]
Kumar Galafe137112011-01-19 03:05:26 -06001/*
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +00002 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Galafe137112011-01-19 03:05:26 -06003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_MPC85xx_CONFIG_H_
22#define _ASM_MPC85xx_CONFIG_H_
23
24/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
25
Timur Tabid8f341c2011-08-04 18:03:41 -050026#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
27#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
28#endif
29
York Sunf066a042012-10-28 08:12:54 +000030/*
31 * This macro should be removed when we no longer care about backwards
32 * compatibility with older operating systems.
33 */
34#define CONFIG_PPC_SPINTABLE_COMPATIBLE
35
York Sun7d69ea32012-10-08 07:44:22 +000036#define FSL_DDR_VER_4_7 47
37
Kumar Galafe137112011-01-19 03:05:26 -060038/* Number of TLB CAM entries we have on FSL Book-E chips */
39#if defined(CONFIG_E500MC)
40#define CONFIG_SYS_NUM_TLBCAMS 64
41#elif defined(CONFIG_E500)
42#define CONFIG_SYS_NUM_TLBCAMS 16
43#endif
44
45#if defined(CONFIG_MPC8536)
46#define CONFIG_MAX_CPUS 1
47#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +000048#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Galafe137112011-01-19 03:05:26 -060049#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -050050#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -060051
Wolfgang Denka4de8352011-02-02 22:36:10 +010052#elif defined(CONFIG_MPC8540)
Kumar Galafe137112011-01-19 03:05:26 -060053#define CONFIG_MAX_CPUS 1
54#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -050055#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -060056
Wolfgang Denka4de8352011-02-02 22:36:10 +010057#elif defined(CONFIG_MPC8541)
Kumar Galafe137112011-01-19 03:05:26 -060058#define CONFIG_MAX_CPUS 1
59#define CONFIG_SYS_FSL_NUM_LAWS 8
60#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -050061#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -060062
63#elif defined(CONFIG_MPC8544)
64#define CONFIG_MAX_CPUS 1
65#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +000066#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Galafe137112011-01-19 03:05:26 -060067#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -050068#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -060069
70#elif defined(CONFIG_MPC8548)
71#define CONFIG_MAX_CPUS 1
72#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +000073#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Galafe137112011-01-19 03:05:26 -060074#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -050075#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala866c6fa2011-09-16 09:54:30 -050076#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Galaf3339d62011-10-03 08:37:57 -050077#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhaoc8caa8a2011-10-03 08:38:50 -050078#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang78deaa12012-03-08 00:33:14 +000079#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
80#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
81#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
82#define CONFIG_SYS_FSL_RMU
83#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -060084
85#elif defined(CONFIG_MPC8555)
86#define CONFIG_MAX_CPUS 1
87#define CONFIG_SYS_FSL_NUM_LAWS 8
88#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -050089#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -060090
91#elif defined(CONFIG_MPC8560)
92#define CONFIG_MAX_CPUS 1
93#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabid8f341c2011-08-04 18:03:41 -050094#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galafe137112011-01-19 03:05:26 -060095
96#elif defined(CONFIG_MPC8568)
97#define CONFIG_MAX_CPUS 1
98#define CONFIG_SYS_FSL_NUM_LAWS 10
99#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600100#define QE_MURAM_SIZE 0x10000UL
101#define MAX_QE_RISC 2
102#define QE_NUM_OF_SNUM 28
Timur Tabid8f341c2011-08-04 18:03:41 -0500103#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000104#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
105#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
106#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
107#define CONFIG_SYS_FSL_RMU
108#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600109
110#elif defined(CONFIG_MPC8569)
111#define CONFIG_MAX_CPUS 1
112#define CONFIG_SYS_FSL_NUM_LAWS 10
113#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala52bd8152011-01-31 23:09:25 -0600114#define QE_MURAM_SIZE 0x20000UL
115#define MAX_QE_RISC 4
116#define QE_NUM_OF_SNUM 46
Timur Tabid8f341c2011-08-04 18:03:41 -0500117#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang78deaa12012-03-08 00:33:14 +0000118#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
119#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
120#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
121#define CONFIG_SYS_FSL_RMU
122#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600123
124#elif defined(CONFIG_MPC8572)
125#define CONFIG_MAX_CPUS 2
126#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha826cf622012-08-15 04:12:43 +0000127#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600128#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500129#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun9aa857b2011-01-25 21:51:27 -0800130#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sunc8fc9592011-01-25 22:05:49 -0800131#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Galafe137112011-01-19 03:05:26 -0600132
133#elif defined(CONFIG_P1010)
134#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530135#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600136#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000137#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Galafe137112011-01-19 03:05:26 -0600138#define CONFIG_TSECV2
139#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530140#define CONFIG_FSL_SATA_V2
141#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
142#define CONFIG_NUM_DDR_CONTROLLERS 1
143#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala179b1b22011-05-20 00:39:21 -0500144#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530145#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500146#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530147#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530148#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600149
Kumar Galae4e69252011-02-05 13:45:07 -0600150/* P1011 is single core version of P1020 */
Kumar Galafe137112011-01-19 03:05:26 -0600151#elif defined(CONFIG_P1011)
152#define CONFIG_MAX_CPUS 1
153#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000154#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600155#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000156#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600157#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500158#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600159#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
160#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600161
Kumar Galae4e69252011-02-05 13:45:07 -0600162/* P1012 is single core version of P1021 */
Kumar Galafe137112011-01-19 03:05:26 -0600163#elif defined(CONFIG_P1012)
164#define CONFIG_MAX_CPUS 1
165#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000166#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600167#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000168#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600169#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500170#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600171#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
172#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600173#define QE_MURAM_SIZE 0x6000UL
174#define MAX_QE_RISC 1
175#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600176
Kumar Galae4e69252011-02-05 13:45:07 -0600177/* P1013 is single core version of P1022 */
Kumar Galafe137112011-01-19 03:05:26 -0600178#elif defined(CONFIG_P1013)
179#define CONFIG_MAX_CPUS 1
180#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000181#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600182#define CONFIG_TSECV2
183#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi293935c2011-11-21 17:10:22 -0600184#define CONFIG_FSL_SATA_V2
Timur Tabid8f341c2011-08-04 18:03:41 -0500185#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600186#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
187#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
188#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600189
190#elif defined(CONFIG_P1014)
191#define CONFIG_MAX_CPUS 1
Priyanka Jain02449632011-02-09 09:24:10 +0530192#define CONFIG_FSL_SDHC_V2_3
Kumar Galafe137112011-01-19 03:05:26 -0600193#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000194#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Galafe137112011-01-19 03:05:26 -0600195#define CONFIG_TSECV2
196#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal7373c592011-02-06 11:31:44 +0530197#define CONFIG_FSL_SATA_V2
198#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
199#define CONFIG_NUM_DDR_CONTROLLERS 1
200#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh3fb68ee2011-03-23 15:20:43 +0530201#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwalc7664a42011-06-30 03:00:28 -0500202#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwalaf54a5f2011-06-29 16:32:52 +0530203#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal46b86ca2011-07-07 20:36:47 +0530204#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Galafe137112011-01-19 03:05:26 -0600205
Kumar Galae4e69252011-02-05 13:45:07 -0600206/* P1017 is single core version of P1023 */
Roy Zang1de20b02011-02-03 22:14:19 -0600207#elif defined(CONFIG_P1017)
208#define CONFIG_MAX_CPUS 1
209#define CONFIG_SYS_FSL_NUM_LAWS 12
210#define CONFIG_SYS_FSL_SEC_COMPAT 4
211#define CONFIG_SYS_NUM_FMAN 1
212#define CONFIG_SYS_NUM_FM1_DTSEC 2
213#define CONFIG_NUM_DDR_CONTROLLERS 1
214#define CONFIG_SYS_QMAN_NUM_PORTALS 3
215#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600216#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500217#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500218#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600219
Kumar Galafe137112011-01-19 03:05:26 -0600220#elif defined(CONFIG_P1020)
221#define CONFIG_MAX_CPUS 2
222#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000223#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600224#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000225#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600226#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500227#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600228#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
229#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Galafe137112011-01-19 03:05:26 -0600230
231#elif defined(CONFIG_P1021)
232#define CONFIG_MAX_CPUS 2
233#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000234#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600235#define CONFIG_TSECV2
Prabhakar Kushwaha1c48e772011-02-01 15:55:58 +0000236#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Galafe137112011-01-19 03:05:26 -0600237#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500238#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600239#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
240#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600241#define QE_MURAM_SIZE 0x6000UL
242#define MAX_QE_RISC 1
243#define QE_NUM_OF_SNUM 28
Kumar Galafe137112011-01-19 03:05:26 -0600244
245#elif defined(CONFIG_P1022)
246#define CONFIG_MAX_CPUS 2
247#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000248#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600249#define CONFIG_TSECV2
250#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi293935c2011-11-21 17:10:22 -0600251#define CONFIG_FSL_SATA_V2
Timur Tabid8f341c2011-08-04 18:03:41 -0500252#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang7cd05902011-01-30 17:06:20 -0600253#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
254#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
255#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Galafe137112011-01-19 03:05:26 -0600256
Roy Zang1de20b02011-02-03 22:14:19 -0600257#elif defined(CONFIG_P1023)
258#define CONFIG_MAX_CPUS 2
259#define CONFIG_SYS_FSL_NUM_LAWS 12
260#define CONFIG_SYS_FSL_SEC_COMPAT 4
261#define CONFIG_SYS_NUM_FMAN 1
262#define CONFIG_SYS_NUM_FM1_DTSEC 2
263#define CONFIG_NUM_DDR_CONTROLLERS 1
264#define CONFIG_SYS_QMAN_NUM_PORTALS 3
265#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Galad80dfe42011-02-04 00:43:34 -0600266#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala179b1b22011-05-20 00:39:21 -0500267#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500268#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang1de20b02011-02-03 22:14:19 -0600269
Kumar Galae4e69252011-02-05 13:45:07 -0600270/* P1024 is lower end variant of P1020 */
271#elif defined(CONFIG_P1024)
272#define CONFIG_MAX_CPUS 2
273#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000274#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galae4e69252011-02-05 13:45:07 -0600275#define CONFIG_TSECV2
276#define CONFIG_FSL_PCIE_DISABLE_ASPM
277#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500278#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600279#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
280#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
281
282/* P1025 is lower end variant of P1021 */
283#elif defined(CONFIG_P1025)
284#define CONFIG_MAX_CPUS 2
285#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000286#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galae4e69252011-02-05 13:45:07 -0600287#define CONFIG_TSECV2
288#define CONFIG_FSL_PCIE_DISABLE_ASPM
289#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500290#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Galae4e69252011-02-05 13:45:07 -0600291#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
292#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang8cb2af72011-02-11 01:25:30 -0600293#define QE_MURAM_SIZE 0x6000UL
294#define MAX_QE_RISC 1
295#define QE_NUM_OF_SNUM 28
Kumar Galae4e69252011-02-05 13:45:07 -0600296
297/* P2010 is single core version of P2020 */
Kumar Galafe137112011-01-19 03:05:26 -0600298#elif defined(CONFIG_P2010)
299#define CONFIG_MAX_CPUS 1
300#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000301#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600302#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500303#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600304#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600305#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Galafe137112011-01-19 03:05:26 -0600306
307#elif defined(CONFIG_P2020)
308#define CONFIG_MAX_CPUS 2
309#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha3d42a962012-04-29 23:57:12 +0000310#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Galafe137112011-01-19 03:05:26 -0600311#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabid8f341c2011-08-04 18:03:41 -0500312#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala7b5b4802011-01-26 01:43:15 -0600313#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala9a878d52011-01-29 15:36:10 -0600314#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang78deaa12012-03-08 00:33:14 +0000315#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
316#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
317#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
318#define CONFIG_SYS_FSL_RMU
319#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Galafe137112011-01-19 03:05:26 -0600320
Scott Wooda1ef48c2012-08-14 10:14:51 +0000321#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sun7e0edbd2012-10-08 07:44:15 +0000322#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600323#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600324#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600325#define CONFIG_SYS_FSL_NUM_LAWS 32
326#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600327#define CONFIG_FSL_SATA_V2
Kumar Gala619541b2011-05-13 01:16:07 -0500328#define CONFIG_SYS_NUM_FMAN 1
329#define CONFIG_SYS_NUM_FM1_DTSEC 5
330#define CONFIG_SYS_NUM_FM1_10GEC 1
331#define CONFIG_NUM_DDR_CONTROLLERS 1
332#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
333#define CONFIG_SYS_FSL_TBCLK_DIV 32
334#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500335#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala619541b2011-05-13 01:16:07 -0500336#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
337#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500338#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala619541b2011-05-13 01:16:07 -0500339#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun9ed88112012-05-07 07:26:47 +0000340#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600341#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800342#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang558359a2012-10-14 20:55:17 +0000343#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang78deaa12012-03-08 00:33:14 +0000344#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
345#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
346#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000347#define CONFIG_SYS_FSL_ERRATUM_A004510
348#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
349#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
350#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang712b6622012-09-28 21:26:19 +0000351#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabie3ab8c12012-10-25 12:40:00 +0000352#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala619541b2011-05-13 01:16:07 -0500353
Kumar Galafe137112011-01-19 03:05:26 -0600354#elif defined(CONFIG_PPC_P3041)
York Sun7e0edbd2012-10-08 07:44:15 +0000355#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600356#define CONFIG_MAX_CPUS 4
Kumar Gala3842bb52011-02-16 02:03:29 -0600357#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600358#define CONFIG_SYS_FSL_NUM_LAWS 32
359#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600360#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600361#define CONFIG_SYS_NUM_FMAN 1
362#define CONFIG_SYS_NUM_FM1_DTSEC 5
363#define CONFIG_SYS_NUM_FM1_10GEC 1
364#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Galad80dfe42011-02-04 00:43:34 -0600365#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600366#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500367#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500368#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500369#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
370#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500371#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800372#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun53155532012-08-08 18:04:53 +0000373#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala945e59a2011-11-22 06:51:15 -0600374#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800375#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang558359a2012-10-14 20:55:17 +0000376#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang78deaa12012-03-08 00:33:14 +0000377#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
378#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
379#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000380#define CONFIG_SYS_FSL_ERRATUM_A004510
381#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
382#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
383#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang712b6622012-09-28 21:26:19 +0000384#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabie3ab8c12012-10-25 12:40:00 +0000385#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Galafe137112011-01-19 03:05:26 -0600386
Scott Wooda1ef48c2012-08-14 10:14:51 +0000387#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sun7e0edbd2012-10-08 07:44:15 +0000388#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600389#define CONFIG_MAX_CPUS 8
Kumar Gala3842bb52011-02-16 02:03:29 -0600390#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Galafe137112011-01-19 03:05:26 -0600391#define CONFIG_SYS_FSL_NUM_LAWS 32
392#define CONFIG_SYS_FSL_SEC_COMPAT 4
393#define CONFIG_SYS_NUM_FMAN 2
394#define CONFIG_SYS_NUM_FM1_DTSEC 4
395#define CONFIG_SYS_NUM_FM2_DTSEC 4
396#define CONFIG_SYS_NUM_FM1_10GEC 1
397#define CONFIG_SYS_NUM_FM2_10GEC 1
398#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600399#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600400#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala179b1b22011-05-20 00:39:21 -0500401#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabid8f341c2011-08-04 18:03:41 -0500402#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Galafe137112011-01-19 03:05:26 -0600403#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
404#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun922f40f2011-01-10 12:03:01 +0000405#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Galafe137112011-01-19 03:05:26 -0600406#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
407#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
408#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R6191183659922012-09-18 09:50:08 +0000409#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Galafe137112011-01-19 03:05:26 -0600410#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun9ed88112012-05-07 07:26:47 +0000411#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Galafe137112011-01-19 03:05:26 -0600412#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medveb01c81f2010-08-31 22:57:38 -0500413#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi6a62dc42011-04-18 17:16:00 -0500414#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi90f381d2011-04-01 13:19:36 -0500415#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala945e59a2011-11-22 06:51:15 -0600416#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sundf2be192011-11-20 10:01:35 -0800417#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang558359a2012-10-14 20:55:17 +0000418#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang78deaa12012-03-08 00:33:14 +0000419#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
420#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
421#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
422#define CONFIG_SYS_FSL_RMU
423#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood80806962012-08-14 10:14:53 +0000424#define CONFIG_SYS_FSL_ERRATUM_A004510
425#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
426#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gang712b6622012-09-28 21:26:19 +0000427#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabie3ab8c12012-10-25 12:40:00 +0000428#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Galafe137112011-01-19 03:05:26 -0600429
Scott Wooda1ef48c2012-08-14 10:14:51 +0000430#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sun2394a0f2012-10-08 07:44:30 +0000431#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun7e0edbd2012-10-08 07:44:15 +0000432#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
Kumar Galafe137112011-01-19 03:05:26 -0600433#define CONFIG_MAX_CPUS 2
Kumar Gala3842bb52011-02-16 02:03:29 -0600434#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Galafe137112011-01-19 03:05:26 -0600435#define CONFIG_SYS_FSL_NUM_LAWS 32
436#define CONFIG_SYS_FSL_SEC_COMPAT 4
Timur Tabi293935c2011-11-21 17:10:22 -0600437#define CONFIG_FSL_SATA_V2
Kumar Gala60d95d82011-01-25 12:42:32 -0600438#define CONFIG_SYS_NUM_FMAN 1
439#define CONFIG_SYS_NUM_FM1_DTSEC 5
440#define CONFIG_SYS_NUM_FM1_10GEC 1
441#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Galad80dfe42011-02-04 00:43:34 -0600442#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Galaf4fb90f2011-02-18 05:40:54 -0600443#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala179b1b22011-05-20 00:39:21 -0500444#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabid8f341c2011-08-04 18:03:41 -0500445#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang6d6a0e12011-04-13 00:08:51 -0500446#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
447#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Galaa49034f2011-04-13 00:19:10 -0500448#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu32276202011-04-19 15:28:41 +0800449#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sundf2be192011-11-20 10:01:35 -0800450#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang558359a2012-10-14 20:55:17 +0000451#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
Liu Gang78deaa12012-03-08 00:33:14 +0000452#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
453#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
454#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood80806962012-08-14 10:14:53 +0000455#define CONFIG_SYS_FSL_ERRATUM_A004510
456#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
457#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gang712b6622012-09-28 21:26:19 +0000458#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Galafe137112011-01-19 03:05:26 -0600459
Timur Tabid5e13882012-10-05 11:09:19 +0000460#elif defined(CONFIG_PPC_P5040)
Timur Tabi9a7b5a32012-10-23 10:48:09 +0000461#define CONFIG_SYS_PPC64
Timur Tabid5e13882012-10-05 11:09:19 +0000462#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
463#define CONFIG_MAX_CPUS 4
464#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
465#define CONFIG_SYS_FSL_NUM_LAWS 32
466#define CONFIG_SYS_FSL_SEC_COMPAT 4
467#define CONFIG_SYS_NUM_FMAN 2
468#define CONFIG_SYS_NUM_FM1_DTSEC 5
469#define CONFIG_SYS_NUM_FM1_10GEC 1
470#define CONFIG_SYS_NUM_FM2_DTSEC 5
471#define CONFIG_SYS_NUM_FM2_10GEC 1
472#define CONFIG_NUM_DDR_CONTROLLERS 2
473#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
474#define CONFIG_SYS_FSL_TBCLK_DIV 16
475#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
476#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
477#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
478#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
479#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
480#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
481#define CONFIG_SYS_FSL_ERRATUM_USB138
482#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
483#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
484#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabid5e13882012-10-05 11:09:19 +0000485#define CONFIG_SYS_FSL_ERRATUM_A004510
486#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
487#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
488
Prabhakar Kushwahabeebb882012-04-24 20:16:49 +0000489#elif defined(CONFIG_BSC9131)
490#define CONFIG_MAX_CPUS 1
491#define CONFIG_FSL_SDHC_V2_3
492#define CONFIG_SYS_FSL_NUM_LAWS 12
493#define CONFIG_TSECV2
494#define CONFIG_SYS_FSL_SEC_COMPAT 4
495#define CONFIG_NUM_DDR_CONTROLLERS 1
496#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
497#define CONFIG_NAND_FSL_IFC
498#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
499#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
500
York Sun9941a222012-10-08 07:44:19 +0000501#elif defined(CONFIG_PPC_T4240)
York Sun2394a0f2012-10-08 07:44:30 +0000502#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun9941a222012-10-08 07:44:19 +0000503#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
504#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
505#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
506#define CONFIG_MAX_CPUS 12
507#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
508#define CONFIG_SYS_FSL_NUM_LAWS 32
509#define CONFIG_SYS_FSL_SRDS_3
510#define CONFIG_SYS_FSL_SRDS_4
511#define CONFIG_SYS_FSL_SEC_COMPAT 4
512#define CONFIG_SYS_NUM_FMAN 2
513#define CONFIG_SYS_NUM_FM1_DTSEC 8
514#define CONFIG_SYS_NUM_FM1_10GEC 2
515#define CONFIG_SYS_NUM_FM2_DTSEC 8
516#define CONFIG_SYS_NUM_FM2_10GEC 2
517#define CONFIG_NUM_DDR_CONTROLLERS 3
518#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zangbafd8032012-10-08 07:44:21 +0000519#define CONFIG_SYS_FMAN_V3
York Sun9941a222012-10-08 07:44:19 +0000520#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
521#define CONFIG_SYS_FSL_TBCLK_DIV 16
522#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
523#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
524#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
525#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
526#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
527#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
528#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
York Suna28496f2012-10-08 07:44:25 +0000529#define CONFIG_SYS_FSL_ERRATUM_A004468
York Sun6995a022012-10-08 07:44:26 +0000530#define CONFIG_SYS_FSL_ERRATUM_A_004934
York Sun9941a222012-10-08 07:44:19 +0000531#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
532
York Sunbcf7b3d2012-10-08 07:44:20 +0000533#elif defined(CONFIG_PPC_B4860)
York Sun2394a0f2012-10-08 07:44:30 +0000534#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sunbcf7b3d2012-10-08 07:44:20 +0000535#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
536#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
537#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
538#define CONFIG_MAX_CPUS 4
539#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
540#define CONFIG_SYS_FSL_NUM_LAWS 32
541#define CONFIG_SYS_FSL_SEC_COMPAT 4
542#define CONFIG_SYS_NUM_FMAN 1
543#define CONFIG_SYS_NUM_FM1_DTSEC 6
544#define CONFIG_SYS_NUM_FM1_10GEC 2
545#define CONFIG_NUM_DDR_CONTROLLERS 1
546#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Roy Zangbafd8032012-10-08 07:44:21 +0000547#define CONFIG_SYS_FMAN_V3
York Sunbcf7b3d2012-10-08 07:44:20 +0000548#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
549#define CONFIG_SYS_FSL_TBCLK_DIV 16
550#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
551#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
552#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
553#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
554#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
555#define CONFIG_SYS_FSL_ERRATUM_A_004934
556#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
557
Kumar Galafe137112011-01-19 03:05:26 -0600558#else
559#error Processor type not defined for this platform
560#endif
561
Timur Tabid8f341c2011-08-04 18:03:41 -0500562#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
563#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
564#endif
565
Kumar Galafe137112011-01-19 03:05:26 -0600566#endif /* _ASM_MPC85xx_CONFIG_H_ */