Blame - arch/powerpc/include/asm/config_mpc85xx.h - filogic/uboot

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Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	1	/*
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	3	*
Wolfgang Denk	d79de1d	2013-07-08 09:37:19 +0200	[diff] [blame]	4	* SPDX-License-Identifier: GPL-2.0+
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	5	*/
				6
				7	#ifndef _ASM_MPC85xx_CONFIG_H_
				8	#define _ASM_MPC85xx_CONFIG_H_
				9
				10	/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
				11
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	12	#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
				13	#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
				14	#endif
				15
York Sun	f066a04	2012-10-28 08:12:54 +0000	[diff] [blame]	16	/*
				17	* This macro should be removed when we no longer care about backwards
				18	* compatibility with older operating systems.
				19	*/
				20	#define CONFIG_PPC_SPINTABLE_COMPATIBLE
				21
York Sun	7d69ea3	2012-10-08 07:44:22 +0000	[diff] [blame]	22	#define FSL_DDR_VER_4_7 47
				23
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	24	/* Number of TLB CAM entries we have on FSL Book-E chips */
				25	#if defined(CONFIG_E500MC)
				26	#define CONFIG_SYS_NUM_TLBCAMS 64
				27	#elif defined(CONFIG_E500)
				28	#define CONFIG_SYS_NUM_TLBCAMS 16
				29	#endif
				30
				31	#if defined(CONFIG_MPC8536)
				32	#define CONFIG_MAX_CPUS 1
				33	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	826cf62	2012-08-15 04:12:43 +0000	[diff] [blame]	34	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	35	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	36	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	37
Wolfgang Denk	a4de835	2011-02-02 22:36:10 +0100	[diff] [blame]	38	#elif defined(CONFIG_MPC8540)
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	39	#define CONFIG_MAX_CPUS 1
				40	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	41	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	42
Wolfgang Denk	a4de835	2011-02-02 22:36:10 +0100	[diff] [blame]	43	#elif defined(CONFIG_MPC8541)
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	44	#define CONFIG_MAX_CPUS 1
				45	#define CONFIG_SYS_FSL_NUM_LAWS 8
				46	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	47	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	48
				49	#elif defined(CONFIG_MPC8544)
				50	#define CONFIG_MAX_CPUS 1
				51	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	826cf62	2012-08-15 04:12:43 +0000	[diff] [blame]	52	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	53	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	54	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	55
				56	#elif defined(CONFIG_MPC8548)
				57	#define CONFIG_MAX_CPUS 1
				58	#define CONFIG_SYS_FSL_NUM_LAWS 10
Prabhakar Kushwaha	826cf62	2012-08-15 04:12:43 +0000	[diff] [blame]	59	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	60	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	61	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	866c6fa	2011-09-16 09:54:30 -0500	[diff] [blame]	62	#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
Kumar Gala	f3339d6	2011-10-03 08:37:57 -0500	[diff] [blame]	63	#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
chenhui zhao	c8caa8a	2011-10-03 08:38:50 -0500	[diff] [blame]	64	#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	65	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				66	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				67	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				68	#define CONFIG_SYS_FSL_RMU
				69	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	70
				71	#elif defined(CONFIG_MPC8555)
				72	#define CONFIG_MAX_CPUS 1
				73	#define CONFIG_SYS_FSL_NUM_LAWS 8
				74	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	75	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	76
				77	#elif defined(CONFIG_MPC8560)
				78	#define CONFIG_MAX_CPUS 1
				79	#define CONFIG_SYS_FSL_NUM_LAWS 8
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	80	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	81
				82	#elif defined(CONFIG_MPC8568)
				83	#define CONFIG_MAX_CPUS 1
				84	#define CONFIG_SYS_FSL_NUM_LAWS 10
				85	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	52bd815	2011-01-31 23:09:25 -0600	[diff] [blame]	86	#define QE_MURAM_SIZE 0x10000UL
				87	#define MAX_QE_RISC 2
				88	#define QE_NUM_OF_SNUM 28
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	89	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	90	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				91	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				92	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				93	#define CONFIG_SYS_FSL_RMU
				94	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	95
				96	#elif defined(CONFIG_MPC8569)
				97	#define CONFIG_MAX_CPUS 1
				98	#define CONFIG_SYS_FSL_NUM_LAWS 10
				99	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Kumar Gala	52bd815	2011-01-31 23:09:25 -0600	[diff] [blame]	100	#define QE_MURAM_SIZE 0x20000UL
				101	#define MAX_QE_RISC 4
				102	#define QE_NUM_OF_SNUM 46
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	103	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	104	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
				105	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				106	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				107	#define CONFIG_SYS_FSL_RMU
				108	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	109
				110	#elif defined(CONFIG_MPC8572)
				111	#define CONFIG_MAX_CPUS 2
				112	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	826cf62	2012-08-15 04:12:43 +0000	[diff] [blame]	113	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	114	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	115	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
York Sun	9aa857b	2011-01-25 21:51:27 -0800	[diff] [blame]	116	#define CONFIG_SYS_FSL_ERRATUM_DDR_115
York Sun	c8fc959	2011-01-25 22:05:49 -0800	[diff] [blame]	117	#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	118
				119	#elif defined(CONFIG_P1010)
				120	#define CONFIG_MAX_CPUS 1
Priyanka Jain	0244963	2011-02-09 09:24:10 +0530	[diff] [blame]	121	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	122	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	123	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	124	#define CONFIG_TSECV2
				125	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	7373c59	2011-02-06 11:31:44 +0530	[diff] [blame]	126	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				127	#define CONFIG_NUM_DDR_CONTROLLERS 1
Mingkai Hu	6f024c9	2013-05-16 10:18:13 +0800	[diff] [blame]	128	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal	7373c59	2011-02-06 11:31:44 +0530	[diff] [blame]	129	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	130	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Ramneek Mehresh	3fb68ee	2011-03-23 15:20:43 +0530	[diff] [blame]	131	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	c7664a4	2011-06-30 03:00:28 -0500	[diff] [blame]	132	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	af54a5f	2011-06-29 16:32:52 +0530	[diff] [blame]	133	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Shengzhou Liu	097be70	2013-08-15 09:31:47 +0800	[diff] [blame^]	134	#define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
Poonam Aggrwal	46b86ca	2011-07-07 20:36:47 +0530	[diff] [blame]	135	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	136
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	137	/* P1011 is single core version of P1020 */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	138	#elif defined(CONFIG_P1011)
				139	#define CONFIG_MAX_CPUS 1
				140	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	141	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	142	#define CONFIG_TSECV2
Prabhakar Kushwaha	1c48e77	2011-02-01 15:55:58 +0000	[diff] [blame]	143	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	144	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	145	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	146	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				147	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	148
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	149	/* P1012 is single core version of P1021 */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	150	#elif defined(CONFIG_P1012)
				151	#define CONFIG_MAX_CPUS 1
				152	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	153	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	154	#define CONFIG_TSECV2
Prabhakar Kushwaha	1c48e77	2011-02-01 15:55:58 +0000	[diff] [blame]	155	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	156	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	157	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	158	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				159	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	8cb2af7	2011-02-11 01:25:30 -0600	[diff] [blame]	160	#define QE_MURAM_SIZE 0x6000UL
				161	#define MAX_QE_RISC 1
				162	#define QE_NUM_OF_SNUM 28
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	163
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	164	/* P1013 is single core version of P1022 */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	165	#elif defined(CONFIG_P1013)
				166	#define CONFIG_MAX_CPUS 1
				167	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	168	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	169	#define CONFIG_TSECV2
				170	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	171	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	7cd0590	2011-01-30 17:06:20 -0600	[diff] [blame]	172	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				173	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				174	#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	175
				176	#elif defined(CONFIG_P1014)
				177	#define CONFIG_MAX_CPUS 1
Priyanka Jain	0244963	2011-02-09 09:24:10 +0530	[diff] [blame]	178	#define CONFIG_FSL_SDHC_V2_3
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	179	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	180	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	181	#define CONFIG_TSECV2
				182	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Poonam Aggrwal	7373c59	2011-02-06 11:31:44 +0530	[diff] [blame]	183	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				184	#define CONFIG_NUM_DDR_CONTROLLERS 1
				185	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Ramneek Mehresh	3fb68ee	2011-03-23 15:20:43 +0530	[diff] [blame]	186	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Poonam Aggrwal	c7664a4	2011-06-30 03:00:28 -0500	[diff] [blame]	187	#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
Poonam Aggrwal	af54a5f	2011-06-29 16:32:52 +0530	[diff] [blame]	188	#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
Poonam Aggrwal	46b86ca	2011-07-07 20:36:47 +0530	[diff] [blame]	189	#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	190
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	191	/* P1017 is single core version of P1023 */
Roy Zang	1de20b0	2011-02-03 22:14:19 -0600	[diff] [blame]	192	#elif defined(CONFIG_P1017)
				193	#define CONFIG_MAX_CPUS 1
				194	#define CONFIG_SYS_FSL_NUM_LAWS 12
				195	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				196	#define CONFIG_SYS_NUM_FMAN 1
				197	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				198	#define CONFIG_NUM_DDR_CONTROLLERS 1
				199	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				200	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	201	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	202	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	203	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang	1de20b0	2011-02-03 22:14:19 -0600	[diff] [blame]	204
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	205	#elif defined(CONFIG_P1020)
				206	#define CONFIG_MAX_CPUS 2
				207	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	208	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	209	#define CONFIG_TSECV2
Prabhakar Kushwaha	1c48e77	2011-02-01 15:55:58 +0000	[diff] [blame]	210	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	211	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	212	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	213	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				214	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	215
				216	#elif defined(CONFIG_P1021)
				217	#define CONFIG_MAX_CPUS 2
				218	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	219	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	220	#define CONFIG_TSECV2
Prabhakar Kushwaha	1c48e77	2011-02-01 15:55:58 +0000	[diff] [blame]	221	#define CONFIG_FSL_PCIE_DISABLE_ASPM
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	222	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	223	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	224	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				225	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	8cb2af7	2011-02-11 01:25:30 -0600	[diff] [blame]	226	#define QE_MURAM_SIZE 0x6000UL
				227	#define MAX_QE_RISC 1
				228	#define QE_NUM_OF_SNUM 28
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	229
				230	#elif defined(CONFIG_P1022)
				231	#define CONFIG_MAX_CPUS 2
				232	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	233	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	234	#define CONFIG_TSECV2
				235	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	236	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Jiang Yutang	7cd0590	2011-01-30 17:06:20 -0600	[diff] [blame]	237	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				238	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				239	#define CONFIG_FSL_SATA_ERRATUM_A001
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	240
Roy Zang	1de20b0	2011-02-03 22:14:19 -0600	[diff] [blame]	241	#elif defined(CONFIG_P1023)
				242	#define CONFIG_MAX_CPUS 2
				243	#define CONFIG_SYS_FSL_NUM_LAWS 12
				244	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				245	#define CONFIG_SYS_NUM_FMAN 1
				246	#define CONFIG_SYS_NUM_FM1_DTSEC 2
				247	#define CONFIG_NUM_DDR_CONTROLLERS 1
				248	#define CONFIG_SYS_QMAN_NUM_PORTALS 3
				249	#define CONFIG_SYS_BMAN_NUM_PORTALS 3
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	250	#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	251	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	252	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
Roy Zang	1de20b0	2011-02-03 22:14:19 -0600	[diff] [blame]	253
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	254	/* P1024 is lower end variant of P1020 */
				255	#elif defined(CONFIG_P1024)
				256	#define CONFIG_MAX_CPUS 2
				257	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	258	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	259	#define CONFIG_TSECV2
				260	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				261	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	262	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	263	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				264	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				265
				266	/* P1025 is lower end variant of P1021 */
				267	#elif defined(CONFIG_P1025)
				268	#define CONFIG_MAX_CPUS 2
				269	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	270	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	271	#define CONFIG_TSECV2
				272	#define CONFIG_FSL_PCIE_DISABLE_ASPM
				273	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	274	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	275	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				276	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Haiying Wang	8cb2af7	2011-02-11 01:25:30 -0600	[diff] [blame]	277	#define QE_MURAM_SIZE 0x6000UL
				278	#define MAX_QE_RISC 1
				279	#define QE_NUM_OF_SNUM 28
Kumar Gala	e4e6925	2011-02-05 13:45:07 -0600	[diff] [blame]	280
				281	/* P2010 is single core version of P2020 */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	282	#elif defined(CONFIG_P2010)
				283	#define CONFIG_MAX_CPUS 1
				284	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	285	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	286	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	287	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	7b5b480	2011-01-26 01:43:15 -0600	[diff] [blame]	288	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	9a878d5	2011-01-29 15:36:10 -0600	[diff] [blame]	289	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	290
				291	#elif defined(CONFIG_P2020)
				292	#define CONFIG_MAX_CPUS 2
				293	#define CONFIG_SYS_FSL_NUM_LAWS 12
Prabhakar Kushwaha	3d42a96	2012-04-29 23:57:12 +0000	[diff] [blame]	294	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	295	#define CONFIG_SYS_FSL_SEC_COMPAT 2
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	296	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
Kumar Gala	7b5b480	2011-01-26 01:43:15 -0600	[diff] [blame]	297	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Kumar Gala	9a878d5	2011-01-29 15:36:10 -0600	[diff] [blame]	298	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	299	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				300	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				301	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				302	#define CONFIG_SYS_FSL_RMU
				303	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	304
Scott Wood	a1ef48c	2012-08-14 10:14:51 +0000	[diff] [blame]	305	#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
York Sun	7e0edbd	2012-10-08 07:44:15 +0000	[diff] [blame]	306	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	307	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	308	#define CONFIG_MAX_CPUS 4
Kumar Gala	3842bb5	2011-02-16 02:03:29 -0600	[diff] [blame]	309	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	310	#define CONFIG_SYS_FSL_NUM_LAWS 32
				311	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	619541b	2011-05-13 01:16:07 -0500	[diff] [blame]	312	#define CONFIG_SYS_NUM_FMAN 1
				313	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				314	#define CONFIG_SYS_NUM_FM1_10GEC 1
				315	#define CONFIG_NUM_DDR_CONTROLLERS 1
				316	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				317	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				318	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	319	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	619541b	2011-05-13 01:16:07 -0500	[diff] [blame]	320	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				321	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	a49034f	2011-04-13 00:19:10 -0500	[diff] [blame]	322	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Kumar Gala	619541b	2011-05-13 01:16:07 -0500	[diff] [blame]	323	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	9ed8811	2012-05-07 07:26:47 +0000	[diff] [blame]	324	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	cf4f493	2013-03-11 17:56:34 +0000	[diff] [blame]	325	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	945e59a	2011-11-22 06:51:15 -0600	[diff] [blame]	326	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	52db64b	2013-03-25 07:30:11 +0000	[diff] [blame]	327	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	df2be19	2011-11-20 10:01:35 -0800	[diff] [blame]	328	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	329	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				330	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				331	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	8080696	2012-08-14 10:14:53 +0000	[diff] [blame]	332	#define CONFIG_SYS_FSL_ERRATUM_A004510
				333	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				334	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				335	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	712b662	2012-09-28 21:26:19 +0000	[diff] [blame]	336	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	e3ab8c1	2012-10-25 12:40:00 +0000	[diff] [blame]	337	#define CONFIG_SYS_FSL_ERRATUM_A004849
Kumar Gala	619541b	2011-05-13 01:16:07 -0500	[diff] [blame]	338
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	339	#elif defined(CONFIG_PPC_P3041)
York Sun	7e0edbd	2012-10-08 07:44:15 +0000	[diff] [blame]	340	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	341	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	342	#define CONFIG_MAX_CPUS 4
Kumar Gala	3842bb5	2011-02-16 02:03:29 -0600	[diff] [blame]	343	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	344	#define CONFIG_SYS_FSL_NUM_LAWS 32
				345	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	60d95d8	2011-01-25 12:42:32 -0600	[diff] [blame]	346	#define CONFIG_SYS_NUM_FMAN 1
				347	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				348	#define CONFIG_SYS_NUM_FM1_10GEC 1
				349	#define CONFIG_NUM_DDR_CONTROLLERS 1
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	350	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	f4fb90f	2011-02-18 05:40:54 -0600	[diff] [blame]	351	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	352	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	353	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	6d6a0e1	2011-04-13 00:08:51 -0500	[diff] [blame]	354	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				355	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	a49034f	2011-04-13 00:19:10 -0500	[diff] [blame]	356	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3227620	2011-04-19 15:28:41 +0800	[diff] [blame]	357	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
York Sun	5315553	2012-08-08 18:04:53 +0000	[diff] [blame]	358	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Xulei	cf4f493	2013-03-11 17:56:34 +0000	[diff] [blame]	359	#define CONFIG_SYS_FSL_ERRATUM_USB14
Kumar Gala	945e59a	2011-11-22 06:51:15 -0600	[diff] [blame]	360	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	52db64b	2013-03-25 07:30:11 +0000	[diff] [blame]	361	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	df2be19	2011-11-20 10:01:35 -0800	[diff] [blame]	362	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	363	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				364	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				365	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	8080696	2012-08-14 10:14:53 +0000	[diff] [blame]	366	#define CONFIG_SYS_FSL_ERRATUM_A004510
				367	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				368	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
				369	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
Liu Gang	712b662	2012-09-28 21:26:19 +0000	[diff] [blame]	370	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	e3ab8c1	2012-10-25 12:40:00 +0000	[diff] [blame]	371	#define CONFIG_SYS_FSL_ERRATUM_A004849
York Sun	cca41c5	2013-06-25 11:37:49 -0700	[diff] [blame]	372	#define CONFIG_SYS_FSL_ERRATUM_A005812
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	373
Scott Wood	a1ef48c	2012-08-14 10:14:51 +0000	[diff] [blame]	374	#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
York Sun	7e0edbd	2012-10-08 07:44:15 +0000	[diff] [blame]	375	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	376	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	377	#define CONFIG_MAX_CPUS 8
Kumar Gala	3842bb5	2011-02-16 02:03:29 -0600	[diff] [blame]	378	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	379	#define CONFIG_SYS_FSL_NUM_LAWS 32
				380	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				381	#define CONFIG_SYS_NUM_FMAN 2
				382	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				383	#define CONFIG_SYS_NUM_FM2_DTSEC 4
				384	#define CONFIG_SYS_NUM_FM1_10GEC 1
				385	#define CONFIG_SYS_NUM_FM2_10GEC 1
				386	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	387	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	f4fb90f	2011-02-18 05:40:54 -0600	[diff] [blame]	388	#define CONFIG_SYS_FSL_TBCLK_DIV 16
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	389	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	390	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	391	#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
				392	#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
York Sun	922f40f	2011-01-10 12:03:01 +0000	[diff] [blame]	393	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	394	#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
				395	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				396	#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
Zang Roy-R61911	8365992	2012-09-18 09:50:08 +0000	[diff] [blame]	397	#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	398	#define CONFIG_SYS_P4080_ERRATUM_CPU22
York Sun	9ed8811	2012-05-07 07:26:47 +0000	[diff] [blame]	399	#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	400	#define CONFIG_SYS_P4080_ERRATUM_SERDES8
Emil Medve	b01c81f	2010-08-31 22:57:38 -0500	[diff] [blame]	401	#define CONFIG_SYS_P4080_ERRATUM_SERDES9
Timur Tabi	6a62dc4	2011-04-18 17:16:00 -0500	[diff] [blame]	402	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
Timur Tabi	90f381d	2011-04-01 13:19:36 -0500	[diff] [blame]	403	#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
Kumar Gala	945e59a	2011-11-22 06:51:15 -0600	[diff] [blame]	404	#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
York Sun	df2be19	2011-11-20 10:01:35 -0800	[diff] [blame]	405	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	406	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				407	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				408	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				409	#define CONFIG_SYS_FSL_RMU
				410	#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
Scott Wood	8080696	2012-08-14 10:14:53 +0000	[diff] [blame]	411	#define CONFIG_SYS_FSL_ERRATUM_A004510
				412	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
				413	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
Liu Gang	712b662	2012-09-28 21:26:19 +0000	[diff] [blame]	414	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Timur Tabi	e3ab8c1	2012-10-25 12:40:00 +0000	[diff] [blame]	415	#define CONFIG_SYS_FSL_ERRATUM_A004849
Timur Tabi	c5355dd	2012-11-01 08:20:23 +0000	[diff] [blame]	416	#define CONFIG_SYS_FSL_ERRATUM_A004580
Yuanquan Chen	c48234e	2012-11-26 23:49:45 +0000	[diff] [blame]	417	#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
York Sun	cca41c5	2013-06-25 11:37:49 -0700	[diff] [blame]	418	#define CONFIG_SYS_FSL_ERRATUM_A005812
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	419
Scott Wood	a1ef48c	2012-08-14 10:14:51 +0000	[diff] [blame]	420	#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
York Sun	2394a0f	2012-10-08 07:44:30 +0000	[diff] [blame]	421	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	7e0edbd	2012-10-08 07:44:15 +0000	[diff] [blame]	422	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	423	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	424	#define CONFIG_MAX_CPUS 2
Kumar Gala	3842bb5	2011-02-16 02:03:29 -0600	[diff] [blame]	425	#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	426	#define CONFIG_SYS_FSL_NUM_LAWS 32
				427	#define CONFIG_SYS_FSL_SEC_COMPAT 4
Kumar Gala	60d95d8	2011-01-25 12:42:32 -0600	[diff] [blame]	428	#define CONFIG_SYS_NUM_FMAN 1
				429	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				430	#define CONFIG_SYS_NUM_FM1_10GEC 1
				431	#define CONFIG_NUM_DDR_CONTROLLERS 2
Kumar Gala	d80dfe4	2011-02-04 00:43:34 -0600	[diff] [blame]	432	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
Kumar Gala	f4fb90f	2011-02-18 05:40:54 -0600	[diff] [blame]	433	#define CONFIG_SYS_FSL_TBCLK_DIV 32
Kumar Gala	179b1b2	2011-05-20 00:39:21 -0500	[diff] [blame]	434	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	435	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
Roy Zang	6d6a0e1	2011-04-13 00:08:51 -0500	[diff] [blame]	436	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				437	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
Kumar Gala	a49034f	2011-04-13 00:19:10 -0500	[diff] [blame]	438	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
Lei Xu	3227620	2011-04-19 15:28:41 +0800	[diff] [blame]	439	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	cf4f493	2013-03-11 17:56:34 +0000	[diff] [blame]	440	#define CONFIG_SYS_FSL_ERRATUM_USB14
York Sun	52db64b	2013-03-25 07:30:11 +0000	[diff] [blame]	441	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
York Sun	df2be19	2011-11-20 10:01:35 -0800	[diff] [blame]	442	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
Liu Gang	78deaa1	2012-03-08 00:33:14 +0000	[diff] [blame]	443	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				444	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				445	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Scott Wood	8080696	2012-08-14 10:14:53 +0000	[diff] [blame]	446	#define CONFIG_SYS_FSL_ERRATUM_A004510
				447	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				448	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
Liu Gang	712b662	2012-09-28 21:26:19 +0000	[diff] [blame]	449	#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	450
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	451	#elif defined(CONFIG_PPC_P5040)
Timur Tabi	9a7b5a3	2012-10-23 10:48:09 +0000	[diff] [blame]	452	#define CONFIG_SYS_PPC64
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	453	#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
York Sun	544f881	2013-06-25 11:37:39 -0700	[diff] [blame]	454	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	455	#define CONFIG_MAX_CPUS 4
				456	#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
				457	#define CONFIG_SYS_FSL_NUM_LAWS 32
				458	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				459	#define CONFIG_SYS_NUM_FMAN 2
				460	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				461	#define CONFIG_SYS_NUM_FM1_10GEC 1
				462	#define CONFIG_SYS_NUM_FM2_DTSEC 5
				463	#define CONFIG_SYS_NUM_FM2_10GEC 1
				464	#define CONFIG_NUM_DDR_CONTROLLERS 2
				465	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				466	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				467	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				468	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				469	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				470	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				471	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				472	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
Xulei	cf4f493	2013-03-11 17:56:34 +0000	[diff] [blame]	473	#define CONFIG_SYS_FSL_ERRATUM_USB14
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	474	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
				475	#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
				476	#define CONFIG_SYS_FSL_ERRATUM_A004699
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	477	#define CONFIG_SYS_FSL_ERRATUM_A004510
				478	#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
				479	#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
York Sun	cca41c5	2013-06-25 11:37:49 -0700	[diff] [blame]	480	#define CONFIG_SYS_FSL_ERRATUM_A005812
Timur Tabi	d5e1388	2012-10-05 11:09:19 +0000	[diff] [blame]	481
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	482	#elif defined(CONFIG_BSC9131)
				483	#define CONFIG_MAX_CPUS 1
				484	#define CONFIG_FSL_SDHC_V2_3
				485	#define CONFIG_SYS_FSL_NUM_LAWS 12
				486	#define CONFIG_TSECV2
				487	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				488	#define CONFIG_NUM_DDR_CONTROLLERS 1
Priyanka Jain	f81e8b2	2013-04-04 09:31:54 +0530	[diff] [blame]	489	#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
				490	#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
Mingkai Hu	6f024c9	2013-05-16 10:18:13 +0800	[diff] [blame]	491	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	492	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				493	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	beebb88	2012-04-24 20:16:49 +0000	[diff] [blame]	494	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				495
Prabhakar Kushwaha	92543c2	2013-01-23 17:59:57 +0000	[diff] [blame]	496	#elif defined(CONFIG_BSC9132)
				497	#define CONFIG_MAX_CPUS 2
				498	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
				499	#define CONFIG_FSL_SDHC_V2_3
				500	#define CONFIG_SYS_FSL_NUM_LAWS 12
				501	#define CONFIG_TSECV2
				502	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				503	#define CONFIG_NUM_DDR_CONTROLLERS 2
Priyanka Jain	c73b903	2013-07-02 09:21:04 +0530	[diff] [blame]	504	#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
				505	#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
				506	#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
				507	#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
York Sun	84fa67e	2013-04-18 19:31:01 -0700	[diff] [blame]	508	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
Prabhakar Kushwaha	92543c2	2013-01-23 17:59:57 +0000	[diff] [blame]	509	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				510	#define CONFIG_NAND_FSL_IFC
Prabhakar Kushwaha	92543c2	2013-01-23 17:59:57 +0000	[diff] [blame]	511	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				512	#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
				513	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
				514
York Sun	64fd08b	2013-03-25 07:40:05 +0000	[diff] [blame]	515	#elif defined(CONFIG_PPC_T4240) \|\| defined(CONFIG_PPC_T4160)
				516	#define CONFIG_E6500
York Sun	2394a0f	2012-10-08 07:44:30 +0000	[diff] [blame]	517	#define CONFIG_SYS_PPC64 /* 64-bit core */
York Sun	9941a22	2012-10-08 07:44:19 +0000	[diff] [blame]	518	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				519	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sun	aa150bb	2013-03-25 07:40:07 +0000	[diff] [blame]	520	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun	9941a22	2012-10-08 07:44:19 +0000	[diff] [blame]	521	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
York Sun	64fd08b	2013-03-25 07:40:05 +0000	[diff] [blame]	522	#ifdef CONFIG_PPC_T4240
York Sun	9941a22	2012-10-08 07:44:19 +0000	[diff] [blame]	523	#define CONFIG_MAX_CPUS 12
York Sun	9941a22	2012-10-08 07:44:19 +0000	[diff] [blame]	524	#define CONFIG_SYS_NUM_FM1_DTSEC 8
				525	#define CONFIG_SYS_NUM_FM1_10GEC 2
				526	#define CONFIG_SYS_NUM_FM2_DTSEC 8
				527	#define CONFIG_SYS_NUM_FM2_10GEC 2
				528	#define CONFIG_NUM_DDR_CONTROLLERS 3
York Sun	64fd08b	2013-03-25 07:40:05 +0000	[diff] [blame]	529	#else
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	530	#define CONFIG_MAX_CPUS 8
York Sun	64fd08b	2013-03-25 07:40:05 +0000	[diff] [blame]	531	#define CONFIG_SYS_NUM_FM1_DTSEC 7
				532	#define CONFIG_SYS_NUM_FM1_10GEC 1
				533	#define CONFIG_SYS_NUM_FM2_DTSEC 7
				534	#define CONFIG_SYS_NUM_FM2_10GEC 1
				535	#define CONFIG_NUM_DDR_CONTROLLERS 2
				536	#endif
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	537	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
				538	#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwaha	873e9f0	2013-07-31 16:56:41 +0530	[diff] [blame]	539	#define CONFIG_SYS_FSL_SRDS_1
				540	#define CONFIG_SYS_FSL_SRDS_2
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	541	#define CONFIG_SYS_FSL_SRDS_3
				542	#define CONFIG_SYS_FSL_SRDS_4
				543	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				544	#define CONFIG_SYS_NUM_FMAN 2
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	545	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu	6f024c9	2013-05-16 10:18:13 +0800	[diff] [blame]	546	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	547	#define CONFIG_SYS_FMAN_V3
				548	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				549	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				550	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
				551	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				552	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				553	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang	d5eca7e	2013-06-25 18:12:14 +0800	[diff] [blame]	554	#define CONFIG_SYS_FSL_SRIO_LIODN
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	555	#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
				556	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				557	#define CONFIG_SYS_FSL_ERRATUM_A004468
				558	#define CONFIG_SYS_FSL_ERRATUM_A_004934
				559	#define CONFIG_SYS_FSL_ERRATUM_A005871
Scott Wood	3f4a5c4	2013-05-15 17:50:13 -0500	[diff] [blame]	560	#define CONFIG_SYS_FSL_ERRATUM_A006593
York Sun	fb5137a	2013-03-25 07:33:29 +0000	[diff] [blame]	561	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				562	#define CONFIG_SYS_FSL_PCI_VER_3_X
				563
Poonam Aggrwal	525ab51	2013-03-25 07:40:20 +0000	[diff] [blame]	564	#elif defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_B4420)
				565	#define CONFIG_E6500
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	566	#define CONFIG_SYS_PPC64 /* 64-bit core */
				567	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				568	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
				569	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	570	#define CONFIG_SYS_FSL_NUM_LAWS 32
Prabhakar Kushwaha	873e9f0	2013-07-31 16:56:41 +0530	[diff] [blame]	571	#define CONFIG_SYS_FSL_SRDS_1
				572	#define CONFIG_SYS_FSL_SRDS_2
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	573	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				574	#define CONFIG_SYS_NUM_FMAN 1
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	575	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
Mingkai Hu	6f024c9	2013-05-16 10:18:13 +0800	[diff] [blame]	576	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	577	#define CONFIG_SYS_FMAN_V3
				578	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
				579	#define CONFIG_SYS_FSL_TBCLK_DIV 16
				580	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				581	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				582	#define CONFIG_SYS_FSL_ERRATUM_A_004934
Shengzhou Liu	5d9606e	2013-02-27 21:56:54 +0000	[diff] [blame]	583	#define CONFIG_SYS_FSL_ERRATUM_A005871
Scott Wood	3f4a5c4	2013-05-15 17:50:13 -0500	[diff] [blame]	584	#define CONFIG_SYS_FSL_ERRATUM_A006593
Poonam Aggrwal	248865e	2012-12-23 19:24:16 +0000	[diff] [blame]	585	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				586
Poonam Aggrwal	525ab51	2013-03-25 07:40:20 +0000	[diff] [blame]	587	#ifdef CONFIG_PPC_B4860
York Sun	aa150bb	2013-03-25 07:40:07 +0000	[diff] [blame]	588	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
York Sun	bcf7b3d	2012-10-08 07:44:20 +0000	[diff] [blame]	589	#define CONFIG_MAX_CPUS 4
				590	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
York Sun	bcf7b3d	2012-10-08 07:44:20 +0000	[diff] [blame]	591	#define CONFIG_SYS_NUM_FM1_DTSEC 6
				592	#define CONFIG_SYS_NUM_FM1_10GEC 2
Poonam Aggrwal	1c85955	2012-12-23 19:22:33 +0000	[diff] [blame]	593	#define CONFIG_NUM_DDR_CONTROLLERS 2
York Sun	bcf7b3d	2012-10-08 07:44:20 +0000	[diff] [blame]	594	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				595	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				596	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
Liu Gang	bc6486a	2013-06-25 18:12:13 +0800	[diff] [blame]	597	#define CONFIG_SYS_FSL_SRIO_LIODN
Poonam Aggrwal	525ab51	2013-03-25 07:40:20 +0000	[diff] [blame]	598	#else
				599	#define CONFIG_MAX_CPUS 2
				600	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
				601	#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
				602	#define CONFIG_SYS_NUM_FM1_DTSEC 4
				603	#define CONFIG_SYS_NUM_FM1_10GEC 0
				604	#define CONFIG_NUM_DDR_CONTROLLERS 1
				605	#endif
York Sun	bcf7b3d	2012-10-08 07:44:20 +0000	[diff] [blame]	606
York Sun	4657136	2013-03-25 07:40:06 +0000	[diff] [blame]	607	#elif defined(CONFIG_PPC_T1040)
				608	#define CONFIG_E5500
				609	#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
				610	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
York Sun	aa150bb	2013-03-25 07:40:07 +0000	[diff] [blame]	611	#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
York Sun	4657136	2013-03-25 07:40:06 +0000	[diff] [blame]	612	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
				613	#define CONFIG_MAX_CPUS 4
				614	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
				615	#define CONFIG_SYS_FSL_NUM_LAWS 16
				616	#define CONFIG_SYS_FSL_SEC_COMPAT 4
				617	#define CONFIG_SYS_NUM_FMAN 1
				618	#define CONFIG_SYS_NUM_FM1_DTSEC 5
				619	#define CONFIG_NUM_DDR_CONTROLLERS 1
				620	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
				621	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
				622	#define CONFIG_SYS_FMAN_V3
				623	#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
				624	#define CONFIG_SYS_FSL_TBCLK_DIV 32
				625	#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
				626	#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
				627	#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
				628	#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
				629	#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
				630	#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
				631	#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
				632	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
				633
Mingkai Hu	1a25807	2013-07-04 17:30:36 +0800	[diff] [blame]	634	#elif defined(CONFIG_PPC_C29X)
				635	#define CONFIG_MAX_CPUS 1
				636	#define CONFIG_FSL_SDHC_V2_3
				637	#define CONFIG_SYS_FSL_NUM_LAWS 12
				638	#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
				639	#define CONFIG_TSECV2_1
				640	#define CONFIG_SYS_FSL_SEC_COMPAT 6
				641	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
				642	#define CONFIG_NUM_DDR_CONTROLLERS 1
				643	#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
				644	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
				645
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	646	#else
				647	#error Processor type not defined for this platform
				648	#endif
				649
Timur Tabi	d8f341c	2011-08-04 18:03:41 -0500	[diff] [blame]	650	#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
				651	#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
				652	#endif
				653
York Sun	aa150bb	2013-03-25 07:40:07 +0000	[diff] [blame]	654	#ifdef CONFIG_E6500
				655	#define CONFIG_SYS_FSL_THREADS_PER_CORE 2
				656	#else
				657	#define CONFIG_SYS_FSL_THREADS_PER_CORE 1
				658	#endif
				659
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	660	#endif /* _ASM_MPC85xx_CONFIG_H_ */