blob: 9db29e6b92f551fac22bf2ff63fd1452213b90ac [file] [log] [blame]
Dan Handley610e7e12018-03-01 18:44:00 +00001Arm CPU Specific Build Macros
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002=============================
3
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004This document describes the various build options present in the CPU specific
5operations framework to enable errata workarounds and to enable optimizations
6for a specific CPU on a platform.
7
Dimitris Papastamos446f7f12017-11-30 14:53:53 +00008Security Vulnerability Workarounds
9----------------------------------
10
Dan Handley610e7e12018-03-01 18:44:00 +000011TF-A exports a series of build flags which control which security
12vulnerability workarounds should be applied at runtime.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000013
14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010015 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
16 of the PEs in the system need the workaround. Setting this flag to 0 provides
17 no performance benefit for non-affected platforms, it just helps to comply
18 with the recommendation in the spec regarding workaround discovery.
19 Defaults to 1.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000020
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010021- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
23 the default value of 1 even on platforms that are unaffected by
24 CVE-2018-3639, in order to comply with the recommendation in the spec
25 regarding workaround discovery.
26
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010027- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
28 `CVE-2018-3639`_. This build option should be set to 1 if the target
29 platform contains at least 1 CPU that requires dynamic mitigation.
30 Defaults to 0.
31
Bipin Ravi86499742022-01-18 01:59:06 -060032- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_.
33 This build option should be set to 1 if the target platform contains at
34 least 1 CPU that requires this mitigation. Defaults to 1.
35
Paul Beesleyf8640672019-04-12 14:19:42 +010036.. _arm_cpu_macros_errata_workarounds:
37
Douglas Raillardd7c21b72017-06-28 15:23:03 +010038CPU Errata Workarounds
39----------------------
40
Dan Handley610e7e12018-03-01 18:44:00 +000041TF-A exports a series of build flags which control the errata workarounds that
42are applied to each CPU by the reset handler. The errata details can be found
43in the CPU specific errata documents published by Arm:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010044
45- `Cortex-A53 MPCore Software Developers Errata Notice`_
46- `Cortex-A57 MPCore Software Developers Errata Notice`_
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +010047- `Cortex-A72 MPCore Software Developers Errata Notice`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +010048
49The errata workarounds are implemented for a particular revision or a set of
50processor revisions. This is checked by the reset handler at runtime. Each
51errata workaround is identified by its ``ID`` as specified in the processor's
52errata notice document. The format of the define used to enable/disable the
53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
54is for example ``A57`` for the ``Cortex_A57`` CPU.
55
Paul Beesleyf8640672019-04-12 14:19:42 +010056Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to
57write errata workaround functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010058
59All workarounds are disabled by default. The platform is responsible for
60enabling these workarounds according to its requirement by defining the
61errata workaround build flags in the platform specific makefile. In case
62these workarounds are enabled for the wrong CPU revision then the errata
63workaround is not applied. In the DEBUG build, this is indicated by
64printing a warning to the crash console.
65
66In the current implementation, a platform which has more than 1 variant
67with different revisions of a processor has no runtime mechanism available
68for it to specify which errata workarounds should be enabled or not.
69
John Tsichritzis4daa1de2018-07-23 09:11:59 +010070The value of the build flags is 0 by default, that is, disabled. A value of 1
71will enable it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010072
Joel Hutton26d16762019-04-10 12:52:52 +010073For Cortex-A9, the following errata build flags are defined :
74
Louis Mayencourte6469d52019-04-18 12:11:25 +010075- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
Joel Hutton26d16762019-04-10 12:52:52 +010076 CPU. This needs to be enabled for all revisions of the CPU.
77
Ambroise Vincentd4a51eb2019-03-04 16:56:26 +000078For Cortex-A15, the following errata build flags are defined :
79
80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
82
Ambroise Vincent68b38122019-03-05 09:54:21 +000083- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
85
Ambroise Vincent8cf9eef2019-02-28 16:23:53 +000086For Cortex-A17, the following errata build flags are defined :
87
88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
90
Ambroise Vincentfa5c9512019-03-04 13:20:56 +000091- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
93
Louis Mayencourt8a061272019-04-05 16:25:25 +010094For Cortex-A35, the following errata build flags are defined :
95
96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
98
John Tsichritzis4daa1de2018-07-23 09:11:59 +010099For Cortex-A53, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
103
104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
106
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
109
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
112
Douglas Raillardb52353a2017-07-17 14:14:52 +0100113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
115 revision <= r0p4. This workaround can lead the linker to create ``*.stub``
116 sections.
117
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
120 r0p4 and onwards, this errata is enabled by default in hardware.
121
Douglas Raillardb52353a2017-07-17 14:14:52 +0100122- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
123 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
124 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
125 which are 4kB aligned.
126
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
128 CPUs. Though the erratum is present in every revision of the CPU,
129 this workaround is only applied to CPUs from r0p3 onwards, which feature
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100130 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100131 Earlier revisions of the CPU have other errata which require the same
132 workaround in software, so they should be covered anyway.
133
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100134- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all
135 revisions of Cortex-A53 CPU.
136
Ambroise Vincent7927fa02019-02-21 16:20:43 +0000137For Cortex-A55, the following errata build flags are defined :
138
139- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
140 CPU. This needs to be enabled only for revision r0p0 of the CPU.
141
Ambroise Vincent6f319602019-02-21 16:25:37 +0000142- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
143 CPU. This needs to be enabled only for revision r0p0 of the CPU.
144
Ambroise Vincent6a77f052019-02-21 16:27:34 +0000145- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
146 CPU. This needs to be enabled only for revision r0p0 of the CPU.
147
Ambroise Vincentdd961f72019-02-21 16:29:16 +0000148- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
149 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
150
Ambroise Vincenta1d64462019-02-21 16:29:50 +0000151- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
152 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
153
Ambroise Vincentb72fe7a2019-05-28 09:52:48 +0100154- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
155 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
156
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100157- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all
158 revisions of Cortex-A55 CPU.
159
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100160For Cortex-A57, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
163 CPU. This needs to be enabled only for revision r0p0 of the CPU.
164
165- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
166 CPU. This needs to be enabled only for revision r0p0 of the CPU.
167
168- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
169 CPU. This needs to be enabled only for revision r0p0 of the CPU.
170
Ambroise Vincent1b0db762019-02-21 16:35:07 +0000171- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
172 CPU. This needs to be enabled only for revision r0p0 of the CPU.
173
Ambroise Vincentaa2c0292019-02-21 16:35:49 +0000174- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
175 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
176
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100177- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
178 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
179
180- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
181 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
182
183- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
184 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
185
186- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
187 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
188
189- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
190 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
191
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100192- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
193 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
194
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100195- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all
196 revisions of Cortex-A57 CPU.
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100197
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100198For Cortex-A72, the following errata build flags are defined :
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100199
200- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
201 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
202
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100203- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all
204 revisions of Cortex-A72 CPU.
205
Louis Mayencourt4405de62019-02-21 16:38:16 +0000206For Cortex-A73, the following errata build flags are defined :
207
Louis Mayencourtd69722c2019-02-27 14:24:16 +0000208- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
209 CPU. This needs to be enabled only for revision r0p0 of the CPU.
210
Louis Mayencourt4405de62019-02-21 16:38:16 +0000211- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
212 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
213
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000214For Cortex-A75, the following errata build flags are defined :
215
216- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
217 CPU. This needs to be enabled only for revision r0p0 of the CPU.
218
Louis Mayencourt8d868702019-02-25 14:57:57 +0000219- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
220 CPU. This needs to be enabled only for revision r0p0 of the CPU.
221
Louis Mayencourt09924472019-02-21 17:35:07 +0000222For Cortex-A76, the following errata build flags are defined :
223
Louis Mayencourt59fa2182019-02-25 15:17:44 +0000224- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
225 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
226
Louis Mayencourt09924472019-02-21 17:35:07 +0000227- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
228 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
229
Louis Mayencourtadda9d42019-02-25 11:37:38 +0000230- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
231 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
232
Soby Mathew1d3ba1c2019-05-01 09:43:18 +0100233- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
234 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
235
236- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
237 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
238
239- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
240 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
241
242- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
243 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
244
johpow019603f982020-05-29 14:17:38 -0500245- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
246 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
247
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100248- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
249 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
250 limitation of errata framework this errata is applied to all revisions
251 of Cortex-A76 CPU.
252
johpow0181365e32020-09-29 17:19:09 -0500253- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
254 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
255
johpow013e34e922020-12-15 19:02:18 -0600256- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76
257 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
258
Bipin Ravi23e29e42022-11-02 16:50:03 -0500259- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76
260 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
261 still open.
262
johpow0168aedc72020-06-03 15:23:31 -0500263For Cortex-A77, the following errata build flags are defined :
264
laurenw-arm99ad9762020-07-14 14:18:34 -0500265- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
266 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
267
johpow01a2fa12c2020-09-10 13:39:26 -0500268- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
269 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
270
laurenw-armf5dbbef2021-03-23 13:09:35 -0500271- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
272 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
273
johpow01eb146102021-05-03 13:37:13 -0500274- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
275 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
276
Bipin Ravi8e916622022-06-08 15:27:00 -0500277- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77
278 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
279
Boyan Karatoteve5cf16b2022-09-27 10:37:54 +0100280 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
281 CPU. This needs to be enabled for revisions <= r1p1 of the CPU.
282
Boyan Karatotevaaf5d292022-11-01 11:22:12 +0000283 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77
284 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
285
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500286For Cortex-A78, the following errata build flags are defined :
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600287
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500288- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
289 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600290
johpow019131eb82020-10-06 17:55:25 -0500291- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
292 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
293
johpow0185ea43d2020-10-07 15:08:01 -0500294- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
295 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
296 issue but there is no workaround for that revision.
297
johpow01b3e82942021-04-30 18:08:52 -0500298- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
299 CPU. This needs to be enabled for revisions r0p0 and r1p0.
300
nayanpatel-arm80bf7a52021-08-11 13:33:00 -0700301- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
302 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
303
nayanpatel-arm39e08652021-09-28 17:31:50 -0700304- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
305 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
306 is still open.
307
johpow0145c17242021-09-02 17:53:30 -0500308- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
309 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
310 is present in r0p0 but there is no workaround. It is still open.
311
John Powell12bc0de2022-05-03 15:22:57 -0500312- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78
313 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
314 it is still open.
315
John Powella93b7e52022-05-03 15:52:11 -0500316- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78
317 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
318 it is still open.
319
Bipin Ravi8f78e0d2022-12-15 14:48:21 -0600320- ``ERRATA_A78_2772019``: This applies errata 2772019 workaround to Cortex-A78
321 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
322 it is still open.
323
Sona Mathewf13c1a92023-01-11 12:55:30 -0600324- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78
325 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
326 it is still open.
327
Varun Wadekara3110ad2021-07-27 00:39:40 -0700328For Cortex-A78 AE, the following errata build flags are defined :
329
Varun Wadekar9030a6c2022-03-09 22:04:00 +0000330- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
331 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
332 This erratum is still open.
333
334- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to
335 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
336 erratum is still open.
Varun Wadekar0914fc42021-07-27 02:32:29 -0700337
Varun Wadekar9030a6c2022-03-09 22:04:00 +0000338- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to
339 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
340 erratum is still open.
Varun Wadekara3110ad2021-07-27 00:39:40 -0700341
Varun Wadekarac6bf2e2022-03-09 22:20:32 +0000342- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to
343 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
344 erratum is still open.
345
laurenw-arm4dc18872022-07-12 10:43:52 -0500346For Cortex-A78C, the following errata build flags are defined :
347
348- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to
349 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
350 it is still open.
351
Bipin Ravi9c36e122022-07-15 17:20:16 -0500352- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to
353 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
354 it is still open.
355
Akram Ahmadfbc1edb2022-09-06 11:23:25 +0100356- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to
357 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
358 erratum is still open.
359
Akram Ahmaddbff7cf2022-07-19 14:38:46 +0100360- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to
361 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
362 erratum is still open.
363
Bipin Ravie0b52cc2023-01-18 11:03:21 -0600364- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
365 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
366 This erratum is still open.
367
Okash Khawajabaee3902022-04-21 12:20:21 +0100368For Cortex-X1 CPU, the following errata build flags are defined:
369
370- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1
371 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
372
373- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1
374 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
375
376- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1
377 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
378
lauwal01bd555f42019-06-24 11:23:50 -0500379For Neoverse N1, the following errata build flags are defined :
380
381- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
382 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
383
lauwal01363ee3c2019-06-24 11:28:34 -0500384- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
385 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
386
lauwal01f2adb132019-06-24 11:32:40 -0500387- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
388 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
389
lauwal01e1590442019-06-24 11:35:37 -0500390- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
391 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
392
lauwal01197f14c2019-06-24 11:38:53 -0500393- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
394 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
395
lauwal0107c2a232019-06-24 11:42:02 -0500396- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
397 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
398
lauwal0142771af2019-06-24 11:44:58 -0500399- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
400 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
401
lauwal0100396bf2019-06-24 11:47:30 -0500402- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
403 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
404
lauwal01644b6ed2019-06-24 11:49:01 -0500405- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
406 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
407
Andre Przywarab9347402019-05-20 14:57:06 +0100408- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
409 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
410
laurenw-arm94accd32019-08-20 15:51:24 -0500411- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
412 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
413
johpow01e2428fd2020-08-05 12:27:12 -0500414- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
415 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
416
johpow01f1a84f52020-10-07 14:33:15 -0500417- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
418 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
419 revisions r0p0, r1p0, and r2p0 there is no workaround.
420
Bipin Ravi9edf2492022-11-02 16:12:01 -0500421- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1
422 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
423 still open.
424
johpow01c73b03c2021-05-03 15:33:39 -0500425For Neoverse V1, the following errata build flags are defined :
426
Juan Pablo Conde31c93372022-02-28 14:14:44 -0500427- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1
428 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
429 r1p0.
430
laurenw-arm3c86d832021-08-02 13:22:32 -0500431- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
432 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
433 in r1p1.
434
johpow01c73b03c2021-05-03 15:33:39 -0500435- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
436 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
437 in r1p1.
438
laurenw-armb1923e92021-08-02 14:40:08 -0500439- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1
440 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
441 in r1p1.
442
laurenw-arm6b56f962021-08-02 15:00:15 -0500443- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1
444 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
445
johpow0107acb4f2020-10-07 16:38:37 -0500446- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
447 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
448 CPU.
449
johpow0197db6752021-08-02 18:59:08 -0500450- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1
451 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
452 issue is present in r0p0 as well but there is no workaround for that
453 revision. It is still open.
454
johpow01ad1ca342021-08-03 14:35:20 -0500455- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1
456 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
457 CPU. It is still open.
458
nayanpatel-armfc26ffe2021-09-28 13:41:03 -0700459- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
460 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
461 It is still open.
462
johpow014de29cb2021-09-02 18:29:17 -0500463- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
464 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
465 issue is present in r0p0 as well but there is no workaround for that
466 revision. It is still open.
467
Bipin Ravi971938f2022-06-08 16:28:46 -0500468- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1
469 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
Bipin Ravib4cb31f2022-06-14 17:09:23 -0500470
471- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1
472 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
Bipin Ravi971938f2022-06-08 16:28:46 -0500473 It is still open.
474
Bipin Ravife4b0c42022-12-15 11:57:53 -0600475- ``ERRATA_V1_2743093``: This applies errata 2743093 workaround to Neoverse-V1
476 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
477 CPU. It is still open.
478
Sona Mathewfe405d02023-01-11 17:04:24 -0600479- ``ERRATA_V1_2779461``: This applies erratum 2779461 workaround to Neoverse-V1
480 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
481 CPU. It is still open.
482
nayanpatel-arme55d3252021-08-06 16:39:48 -0700483For Cortex-A710, the following errata build flags are defined :
484
485- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
486 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
487 r2p0 of the CPU. It is still open.
488
nayanpatel-arm7597d082021-08-25 17:35:15 -0700489- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to
490 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
491 r2p0 of the CPU. It is still open.
492
Bipin Ravicd39b142021-03-31 16:45:40 -0500493- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
494 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
495 and is still open.
496
Bipin Ravi87e1d282021-03-31 18:45:55 -0500497- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
498 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
499 of the CPU and is still open.
500
nayanpatel-arm0b338b42021-09-16 15:27:53 -0700501- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to
502 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
503 is still open.
504
nayanpatel-armf2dce0e2021-09-22 12:35:03 -0700505- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
506 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
507 of the CPU and is still open.
508
Bipin Ravi32705b12022-02-06 02:32:54 -0600509- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
510 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
511 of the CPU and is fixed in r2p1.
512
Bipin Ravid53069b2022-02-06 03:11:44 -0600513- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
514 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
515 of the CPU and is fixed in r2p1.
516
Akram Ahmad1714c1d2022-07-21 15:25:08 +0100517- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to
518 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU
519 and is fixed in r2p1.
520
Jayanth Dodderi Chidanandde4f5892022-09-01 22:09:54 +0100521- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to
522 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
523 of the CPU and is fixed in r2p1.
524
johpow017249fd02022-02-28 18:34:04 -0600525- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to
Bipin Ravi380c1982022-12-22 13:31:46 -0600526 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
527 r2p1 of the CPU and is still open.
johpow017249fd02022-02-28 18:34:04 -0600528
Boyan Karatotevf8de5352022-10-03 14:21:28 +0100529- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to
530 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
531 of the CPU and is fixed in r2p1.
532
johpow017d52a8f2022-03-09 16:23:04 -0600533- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to
534 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
535 of the CPU and is fixed in r2p1.
536
Bipin Ravi77eab292022-07-12 15:53:21 -0500537- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to
538 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
539 of the CPU and is fixed in r2p1.
540
Bipin Ravief9a1552022-12-07 13:32:35 -0600541- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to
542 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
543 r2p1 of the CPU and is still open.
544
Bipin Ravieb35e852021-03-30 16:08:32 -0500545For Neoverse N2, the following errata build flags are defined :
546
nayanpatel-arm2f153992021-10-06 15:31:24 -0700547- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
548 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
549
Bipin Ravieb35e852021-03-30 16:08:32 -0500550- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
551 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
552
Bipin Ravi7f565472021-03-31 10:10:27 -0500553- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
554 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
555
Bipin Ravi7e030692021-08-30 13:02:51 -0500556- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
Bipin Ravi0ba631c2021-09-01 01:36:43 -0500557 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
558
559- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
560 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
Bipin Ravi7e030692021-08-30 13:02:51 -0500561
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -0700562- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
563 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
564
nayanpatel-arm2f153992021-10-06 15:31:24 -0700565- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
566 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
567
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700568- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
569 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
570
nayanpatel-armfed98132021-10-07 17:59:33 -0700571- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
572 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
573
nayanpatel-arm45b9f6f2021-10-20 17:30:46 -0700574- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
575 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
576
Boyan Karatotevd3f8b4d2022-10-03 14:07:08 +0100577- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2
578 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
579 r0p1.
580
Akram Ahmadb621bda2022-07-18 12:27:29 +0100581- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2
582 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
583 r0p1.
584
Daniel Boulby1af2b112022-07-06 14:33:13 +0100585- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2
586 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
587 r0p1.
588
Bipin Ravicc744bf2022-12-07 17:01:26 -0600589- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2
590 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
591 in r0p3.
592
johpow0115f10bd2021-12-01 17:40:39 -0600593For Cortex-X2, the following errata build flags are defined :
594
johpow010afef362021-12-02 13:25:50 -0600595- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
596 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
597 it is still open.
598
johpow01f6c37de2021-12-03 11:27:33 -0600599- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
600 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
601 it is still open.
602
johpow0115f10bd2021-12-01 17:40:39 -0600603- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
604 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
605
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600606- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to Cortex-X2
607 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
608 CPU, it is fixed in r2p1.
Bipin Ravi2f73d972022-01-20 00:01:04 -0600609
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600610- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to Cortex-X2
611 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
612 CPU, it is fixed in r2p1.
Bipin Ravi9ad54782022-01-20 00:42:05 -0600613
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600614- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to Cortex-X2
615 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
616 CPU, it is fixed in r2p1.
Bipin Ravi78b72082022-02-06 01:29:31 -0600617
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600618- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to Cortex-X2
619 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed
620 in r2p1.
Bipin Ravic6b65212022-03-08 10:37:43 -0600621
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600622- ``ERRATA_X2_2282622``: This applies errata 2282622 workaround to Cortex-X2
623 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
624 CPU and is still open.
Bipin Ravi4e315c32022-07-12 17:13:01 -0500625
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600626- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to Cortex-X2
627 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU
628 and is fixed in r2p1.
629
630- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2
631 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
632 CPU and is still open.
Bipin Ravi86839eb2022-12-07 13:54:02 -0600633
Boyan Karatotev6559dbd2022-10-03 14:18:28 +0100634For Cortex-X3, the following errata build flags are defined :
635
636- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to
637 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
638 of the CPU, it is fixed in r1p1.
639
Harrison Mutai82dd5ac2022-11-11 14:09:55 +0000640- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3
641 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
642 CPU, it is still open.
643
johpow01de7b5242022-01-04 16:15:18 -0600644For Cortex-A510, the following errata build flags are defined :
645
646- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
647 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is
648 fixed in r0p1.
649
johpow0149f60dd2022-01-06 14:54:49 -0600650- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to
651 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
652 r0p2, r0p3 and r1p0, it is fixed in r1p1.
653
johpow018276f252022-01-07 17:12:31 -0600654- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to
655 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
656 r0p2, it is fixed in r0p3.
657
johpow015a993002022-01-11 17:54:41 -0600658- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to
659 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
660 in r0p3. The issue is also present in r0p0 and r0p1 but there is no
661 workaround for those revisions.
662
johpow013ba9cb22022-02-13 21:00:10 -0600663- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
664 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
665 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
666 ENABLE_MPMM=1.
667
johpow013ead2952022-02-14 20:19:08 -0600668- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
669 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
670 r0p3 and r1p0, it is fixed in r1p1.
671
johpow01ac55c012022-02-15 22:55:22 -0600672- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
673 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
674 r0p3 and r1p0, it is fixed in r1p1.
675
Harrison Mutaie5249fe2022-12-09 12:14:25 +0000676- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to
Akram Ahmada85254e2022-07-21 14:01:33 +0100677 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
678 r0p3, r1p0 and r1p1. It is fixed in r1p2.
679
Akram Ahmad60accba2022-07-22 16:20:44 +0100680- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to
681 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
682 r0p3, r1p0, r1p1, and is fixed in r1p2.
683
Akram Ahmad89034d62022-09-21 13:59:56 +0100684- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to
685 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
686 r0p3, r1p0, r1p1. It is fixed in r1p2.
687
Harrison Mutaie5249fe2022-12-09 12:14:25 +0000688- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to
689 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
690 r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
691
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100692DSU Errata Workarounds
693----------------------
694
695Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
696Shared Unit) errata. The DSU errata details can be found in the respective Arm
697documentation:
698
699- `Arm DSU Software Developers Errata Notice`_.
700
701Each erratum is identified by an ``ID``, as defined in the DSU errata notice
702document. Thus, the build flags which enable/disable the errata workarounds
703have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
704of DSU errata workarounds are similar to `CPU errata workarounds`_.
705
706For DSU errata, the following build flags are defined:
707
Louis Mayencourt4498b152019-04-09 16:29:01 +0100708- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
709 affected DSU configurations. This errata applies only for those DSUs that
710 revision is r0p0 (on r0p1 it is fixed). However, please note that this
711 workaround results in increased DSU power consumption on idle.
712
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100713- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
714 affected DSU configurations. This errata applies only for those DSUs that
715 contain the ACP interface **and** the DSU revision is older than r2p0 (on
716 r2p0 it is fixed). However, please note that this workaround results in
717 increased DSU power consumption on idle.
718
Bipin Raviaf40d692021-12-22 14:35:21 -0600719- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the
720 affected DSU configurations. This errata applies for those DSUs with
721 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However,
722 please note that this workaround results in increased DSU power consumption
723 on idle.
724
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100725CPU Specific optimizations
726--------------------------
727
728This section describes some of the optimizations allowed by the CPU micro
729architecture that can be enabled by the platform as desired.
730
731- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
732 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
733 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
734 of the L2 by set/way flushes any dirty lines from the L1 as well. This
735 is a known safe deviation from the Cortex-A57 TRM defined power down
736 sequence. Each Cortex-A57 based platform must make its own decision on
737 whether to use the optimization.
738
739- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
740 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
741 in a way most programmers expect, and will most probably result in a
Dan Handley610e7e12018-03-01 18:44:00 +0000742 significant speed degradation to any code that employs them. The Armv8-A
743 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100744 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
745 flag enforces this behaviour. This needs to be enabled only for revisions
746 <= r0p3 of the CPU and is enabled by default.
747
748- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
749 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
750 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
751 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
752 `Cortex-A57 Software Optimization Guide`_.
753
Varun Wadekar5ee3abc2018-06-12 16:49:12 -0700754- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
755 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
756 this bit only if their memory system meets the requirement that cache
757 line fill requests from the Cortex-A57 processor are atomic. Each
758 Cortex-A57 based platform must make its own decision on whether to use
759 the optimization. This flag is disabled by default.
760
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100761- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
Manish Pandey3880a362020-01-24 11:54:44 +0000762 level cache(LLC) is present in the system, and that the DataSource field
763 on the master CHI interface indicates when data is returned from the LLC.
764 This is used to control how the LL_CACHE* PMU events count.
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100765 Default value is 0 (Disabled).
Manish Pandey3880a362020-01-24 11:54:44 +0000766
Manish V Badarkhe173c2962022-05-09 21:55:19 +0100767GIC Errata Workarounds
768----------------------
769- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374
770 workaround for the affected GIC600 and GIC600-AE implementations. It applies
771 to implementations of GIC600 and GIC600-AE with revisions less than or equal
772 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600,
773 then this flag is enabled; otherwise, it is 0 (Disabled).
774
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100775--------------
776
Bipin Ravi7dccf8f2022-12-22 14:19:59 -0600777*Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100778
John Tsichritzis3eeac412018-09-04 10:56:53 +0100779.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
780.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
Bipin Ravi86499742022-01-18 01:59:06 -0600781.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960
Paul Beesley2437ddc2019-02-08 16:43:05 +0000782.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
783.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100784.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100785.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100786.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html