blob: e15c82e10ffb53998486fca376dc6e5b3d3e4f84 [file] [log] [blame]
Dan Handley610e7e12018-03-01 18:44:00 +00001Arm CPU Specific Build Macros
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002=============================
3
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004This document describes the various build options present in the CPU specific
5operations framework to enable errata workarounds and to enable optimizations
6for a specific CPU on a platform.
7
Dimitris Papastamos446f7f12017-11-30 14:53:53 +00008Security Vulnerability Workarounds
9----------------------------------
10
Dan Handley610e7e12018-03-01 18:44:00 +000011TF-A exports a series of build flags which control which security
12vulnerability workarounds should be applied at runtime.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000013
14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010015 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
16 of the PEs in the system need the workaround. Setting this flag to 0 provides
17 no performance benefit for non-affected platforms, it just helps to comply
18 with the recommendation in the spec regarding workaround discovery.
19 Defaults to 1.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000020
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010021- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
23 the default value of 1 even on platforms that are unaffected by
24 CVE-2018-3639, in order to comply with the recommendation in the spec
25 regarding workaround discovery.
26
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010027- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
28 `CVE-2018-3639`_. This build option should be set to 1 if the target
29 platform contains at least 1 CPU that requires dynamic mitigation.
30 Defaults to 0.
31
Bipin Ravi86499742022-01-18 01:59:06 -060032- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_.
33 This build option should be set to 1 if the target platform contains at
34 least 1 CPU that requires this mitigation. Defaults to 1.
35
Paul Beesleyf8640672019-04-12 14:19:42 +010036.. _arm_cpu_macros_errata_workarounds:
37
Douglas Raillardd7c21b72017-06-28 15:23:03 +010038CPU Errata Workarounds
39----------------------
40
Dan Handley610e7e12018-03-01 18:44:00 +000041TF-A exports a series of build flags which control the errata workarounds that
42are applied to each CPU by the reset handler. The errata details can be found
43in the CPU specific errata documents published by Arm:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010044
45- `Cortex-A53 MPCore Software Developers Errata Notice`_
46- `Cortex-A57 MPCore Software Developers Errata Notice`_
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +010047- `Cortex-A72 MPCore Software Developers Errata Notice`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +010048
49The errata workarounds are implemented for a particular revision or a set of
50processor revisions. This is checked by the reset handler at runtime. Each
51errata workaround is identified by its ``ID`` as specified in the processor's
52errata notice document. The format of the define used to enable/disable the
53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
54is for example ``A57`` for the ``Cortex_A57`` CPU.
55
Paul Beesleyf8640672019-04-12 14:19:42 +010056Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to
57write errata workaround functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010058
59All workarounds are disabled by default. The platform is responsible for
60enabling these workarounds according to its requirement by defining the
61errata workaround build flags in the platform specific makefile. In case
62these workarounds are enabled for the wrong CPU revision then the errata
63workaround is not applied. In the DEBUG build, this is indicated by
64printing a warning to the crash console.
65
66In the current implementation, a platform which has more than 1 variant
67with different revisions of a processor has no runtime mechanism available
68for it to specify which errata workarounds should be enabled or not.
69
John Tsichritzis4daa1de2018-07-23 09:11:59 +010070The value of the build flags is 0 by default, that is, disabled. A value of 1
71will enable it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010072
Joel Hutton26d16762019-04-10 12:52:52 +010073For Cortex-A9, the following errata build flags are defined :
74
Louis Mayencourte6469d52019-04-18 12:11:25 +010075- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
Joel Hutton26d16762019-04-10 12:52:52 +010076 CPU. This needs to be enabled for all revisions of the CPU.
77
Ambroise Vincentd4a51eb2019-03-04 16:56:26 +000078For Cortex-A15, the following errata build flags are defined :
79
80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
82
Ambroise Vincent68b38122019-03-05 09:54:21 +000083- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
85
Ambroise Vincent8cf9eef2019-02-28 16:23:53 +000086For Cortex-A17, the following errata build flags are defined :
87
88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
90
Ambroise Vincentfa5c9512019-03-04 13:20:56 +000091- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
93
Louis Mayencourt8a061272019-04-05 16:25:25 +010094For Cortex-A35, the following errata build flags are defined :
95
96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
98
John Tsichritzis4daa1de2018-07-23 09:11:59 +010099For Cortex-A53, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
103
104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
106
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
109
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
112
Douglas Raillardb52353a2017-07-17 14:14:52 +0100113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
115 revision <= r0p4. This workaround can lead the linker to create ``*.stub``
116 sections.
117
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
120 r0p4 and onwards, this errata is enabled by default in hardware.
121
Douglas Raillardb52353a2017-07-17 14:14:52 +0100122- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
123 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
124 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
125 which are 4kB aligned.
126
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
128 CPUs. Though the erratum is present in every revision of the CPU,
129 this workaround is only applied to CPUs from r0p3 onwards, which feature
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100130 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100131 Earlier revisions of the CPU have other errata which require the same
132 workaround in software, so they should be covered anyway.
133
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100134- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all
135 revisions of Cortex-A53 CPU.
136
Ambroise Vincent7927fa02019-02-21 16:20:43 +0000137For Cortex-A55, the following errata build flags are defined :
138
139- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
140 CPU. This needs to be enabled only for revision r0p0 of the CPU.
141
Ambroise Vincent6f319602019-02-21 16:25:37 +0000142- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
143 CPU. This needs to be enabled only for revision r0p0 of the CPU.
144
Ambroise Vincent6a77f052019-02-21 16:27:34 +0000145- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
146 CPU. This needs to be enabled only for revision r0p0 of the CPU.
147
Ambroise Vincentdd961f72019-02-21 16:29:16 +0000148- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
149 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
150
Ambroise Vincenta1d64462019-02-21 16:29:50 +0000151- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
152 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
153
Ambroise Vincentb72fe7a2019-05-28 09:52:48 +0100154- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
155 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
156
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100157- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all
158 revisions of Cortex-A55 CPU.
159
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100160For Cortex-A57, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
162- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
163 CPU. This needs to be enabled only for revision r0p0 of the CPU.
164
165- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
166 CPU. This needs to be enabled only for revision r0p0 of the CPU.
167
168- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
169 CPU. This needs to be enabled only for revision r0p0 of the CPU.
170
Ambroise Vincent1b0db762019-02-21 16:35:07 +0000171- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
172 CPU. This needs to be enabled only for revision r0p0 of the CPU.
173
Ambroise Vincentaa2c0292019-02-21 16:35:49 +0000174- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
175 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
176
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100177- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
178 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
179
180- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
181 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
182
183- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
184 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
185
186- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
187 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
188
189- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
190 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
191
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100192- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
193 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
194
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100195- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all
196 revisions of Cortex-A57 CPU.
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100197
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100198For Cortex-A72, the following errata build flags are defined :
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100199
200- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
201 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
202
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100203- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all
204 revisions of Cortex-A72 CPU.
205
Louis Mayencourt4405de62019-02-21 16:38:16 +0000206For Cortex-A73, the following errata build flags are defined :
207
Louis Mayencourtd69722c2019-02-27 14:24:16 +0000208- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
209 CPU. This needs to be enabled only for revision r0p0 of the CPU.
210
Louis Mayencourt4405de62019-02-21 16:38:16 +0000211- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
212 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
213
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000214For Cortex-A75, the following errata build flags are defined :
215
216- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
217 CPU. This needs to be enabled only for revision r0p0 of the CPU.
218
Louis Mayencourt8d868702019-02-25 14:57:57 +0000219- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
220 CPU. This needs to be enabled only for revision r0p0 of the CPU.
221
Louis Mayencourt09924472019-02-21 17:35:07 +0000222For Cortex-A76, the following errata build flags are defined :
223
Louis Mayencourt59fa2182019-02-25 15:17:44 +0000224- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
225 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
226
Louis Mayencourt09924472019-02-21 17:35:07 +0000227- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
228 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
229
Louis Mayencourtadda9d42019-02-25 11:37:38 +0000230- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
231 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
232
Soby Mathew1d3ba1c2019-05-01 09:43:18 +0100233- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76
234 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
235
236- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76
237 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
238
239- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76
240 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
241
242- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
243 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
244
johpow019603f982020-05-29 14:17:38 -0500245- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76
246 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
247
Manish V Badarkhea59fa012020-07-31 08:38:49 +0100248- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
249 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
250 limitation of errata framework this errata is applied to all revisions
251 of Cortex-A76 CPU.
252
johpow0181365e32020-09-29 17:19:09 -0500253- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76
254 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
255
johpow013e34e922020-12-15 19:02:18 -0600256- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76
257 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
258
johpow0168aedc72020-06-03 15:23:31 -0500259For Cortex-A77, the following errata build flags are defined :
260
laurenw-arm99ad9762020-07-14 14:18:34 -0500261- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
262 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
263
johpow01a2fa12c2020-09-10 13:39:26 -0500264- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
265 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
266
laurenw-armf5dbbef2021-03-23 13:09:35 -0500267- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
268 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
269
johpow01eb146102021-05-03 13:37:13 -0500270- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
271 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
272
Bipin Ravi8e916622022-06-08 15:27:00 -0500273- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77
274 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
275
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500276For Cortex-A78, the following errata build flags are defined :
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600277
Jimmy Brisson3571fb92020-06-01 10:18:22 -0500278- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
279 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
Madhukar Pappireddy4efede72019-12-18 15:56:27 -0600280
johpow019131eb82020-10-06 17:55:25 -0500281- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
282 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
283
johpow0185ea43d2020-10-07 15:08:01 -0500284- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78
285 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
286 issue but there is no workaround for that revision.
287
johpow01b3e82942021-04-30 18:08:52 -0500288- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
289 CPU. This needs to be enabled for revisions r0p0 and r1p0.
290
nayanpatel-arm80bf7a52021-08-11 13:33:00 -0700291- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
292 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
293
nayanpatel-arm39e08652021-09-28 17:31:50 -0700294- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
295 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
296 is still open.
297
johpow0145c17242021-09-02 17:53:30 -0500298- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
299 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
300 is present in r0p0 but there is no workaround. It is still open.
301
John Powell12bc0de2022-05-03 15:22:57 -0500302- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78
303 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
304 it is still open.
305
John Powella93b7e52022-05-03 15:52:11 -0500306- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78
307 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
308 it is still open.
309
Varun Wadekara3110ad2021-07-27 00:39:40 -0700310For Cortex-A78 AE, the following errata build flags are defined :
311
Varun Wadekar9030a6c2022-03-09 22:04:00 +0000312- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to
313 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
314 This erratum is still open.
315
316- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to
317 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
318 erratum is still open.
Varun Wadekar0914fc42021-07-27 02:32:29 -0700319
Varun Wadekar9030a6c2022-03-09 22:04:00 +0000320- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to
321 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
322 erratum is still open.
Varun Wadekara3110ad2021-07-27 00:39:40 -0700323
Varun Wadekarac6bf2e2022-03-09 22:20:32 +0000324- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to
325 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
326 erratum is still open.
327
laurenw-arm4dc18872022-07-12 10:43:52 -0500328For Cortex-A78C, the following errata build flags are defined :
329
330- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to
331 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
332 it is still open.
333
Bipin Ravi9c36e122022-07-15 17:20:16 -0500334- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to
335 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
336 it is still open.
337
Okash Khawajabaee3902022-04-21 12:20:21 +0100338For Cortex-X1 CPU, the following errata build flags are defined:
339
340- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1
341 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
342
343- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1
344 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
345
346- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1
347 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
348
lauwal01bd555f42019-06-24 11:23:50 -0500349For Neoverse N1, the following errata build flags are defined :
350
351- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
352 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
353
lauwal01363ee3c2019-06-24 11:28:34 -0500354- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1
355 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
356
lauwal01f2adb132019-06-24 11:32:40 -0500357- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1
358 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
359
lauwal01e1590442019-06-24 11:35:37 -0500360- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
361 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
362
lauwal01197f14c2019-06-24 11:38:53 -0500363- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
364 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
365
lauwal0107c2a232019-06-24 11:42:02 -0500366- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1
367 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
368
lauwal0142771af2019-06-24 11:44:58 -0500369- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1
370 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
371
lauwal0100396bf2019-06-24 11:47:30 -0500372- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1
373 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
374
lauwal01644b6ed2019-06-24 11:49:01 -0500375- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1
376 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
377
Andre Przywarab9347402019-05-20 14:57:06 +0100378- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
379 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
380
laurenw-arm94accd32019-08-20 15:51:24 -0500381- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
382 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
383
johpow01e2428fd2020-08-05 12:27:12 -0500384- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1
385 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
386
johpow01f1a84f52020-10-07 14:33:15 -0500387- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1
388 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
389 revisions r0p0, r1p0, and r2p0 there is no workaround.
390
johpow01c73b03c2021-05-03 15:33:39 -0500391For Neoverse V1, the following errata build flags are defined :
392
Juan Pablo Conde31c93372022-02-28 14:14:44 -0500393- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1
394 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
395 r1p0.
396
laurenw-arm3c86d832021-08-02 13:22:32 -0500397- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
398 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
399 in r1p1.
400
johpow01c73b03c2021-05-03 15:33:39 -0500401- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
402 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
403 in r1p1.
404
laurenw-armb1923e92021-08-02 14:40:08 -0500405- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1
406 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
407 in r1p1.
408
laurenw-arm6b56f962021-08-02 15:00:15 -0500409- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1
410 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
411
johpow0107acb4f2020-10-07 16:38:37 -0500412- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
413 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
414 CPU.
415
johpow0197db6752021-08-02 18:59:08 -0500416- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1
417 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
418 issue is present in r0p0 as well but there is no workaround for that
419 revision. It is still open.
420
johpow01ad1ca342021-08-03 14:35:20 -0500421- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1
422 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
423 CPU. It is still open.
424
nayanpatel-armfc26ffe2021-09-28 13:41:03 -0700425- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
426 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
427 It is still open.
428
johpow014de29cb2021-09-02 18:29:17 -0500429- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
430 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
431 issue is present in r0p0 as well but there is no workaround for that
432 revision. It is still open.
433
Bipin Ravi971938f2022-06-08 16:28:46 -0500434- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1
435 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
Bipin Ravib4cb31f2022-06-14 17:09:23 -0500436
437- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1
438 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
Bipin Ravi971938f2022-06-08 16:28:46 -0500439 It is still open.
440
nayanpatel-arme55d3252021-08-06 16:39:48 -0700441For Cortex-A710, the following errata build flags are defined :
442
443- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
444 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
445 r2p0 of the CPU. It is still open.
446
nayanpatel-arm7597d082021-08-25 17:35:15 -0700447- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to
448 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
449 r2p0 of the CPU. It is still open.
450
Bipin Ravicd39b142021-03-31 16:45:40 -0500451- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
452 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
453 and is still open.
454
Bipin Ravi87e1d282021-03-31 18:45:55 -0500455- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
456 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
457 of the CPU and is still open.
458
nayanpatel-arm0b338b42021-09-16 15:27:53 -0700459- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to
460 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
461 is still open.
462
nayanpatel-armf2dce0e2021-09-22 12:35:03 -0700463- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
464 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
465 of the CPU and is still open.
466
Bipin Ravi32705b12022-02-06 02:32:54 -0600467- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
468 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
469 of the CPU and is fixed in r2p1.
470
Bipin Ravid53069b2022-02-06 03:11:44 -0600471- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to
472 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
473 of the CPU and is fixed in r2p1.
474
johpow017249fd02022-02-28 18:34:04 -0600475- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to
476 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
477 of the CPU and is fixed in r2p1.
478
johpow017d52a8f2022-03-09 16:23:04 -0600479- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to
480 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
481 of the CPU and is fixed in r2p1.
482
Bipin Ravi77eab292022-07-12 15:53:21 -0500483- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to
484 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
485 of the CPU and is fixed in r2p1.
486
Bipin Ravieb35e852021-03-30 16:08:32 -0500487For Neoverse N2, the following errata build flags are defined :
488
nayanpatel-arm2f153992021-10-06 15:31:24 -0700489- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
490 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
491
Bipin Ravieb35e852021-03-30 16:08:32 -0500492- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
493 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
494
Bipin Ravi7f565472021-03-31 10:10:27 -0500495- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
496 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
497
Bipin Ravi7e030692021-08-30 13:02:51 -0500498- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
Bipin Ravi0ba631c2021-09-01 01:36:43 -0500499 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
500
501- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
502 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
Bipin Ravi7e030692021-08-30 13:02:51 -0500503
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -0700504- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
505 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
506
nayanpatel-arm2f153992021-10-06 15:31:24 -0700507- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
508 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
509
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700510- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
511 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
512
nayanpatel-armfed98132021-10-07 17:59:33 -0700513- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
514 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
515
nayanpatel-arm45b9f6f2021-10-20 17:30:46 -0700516- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
517 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
518
Akram Ahmadb621bda2022-07-18 12:27:29 +0100519- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2
520 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
521 r0p1.
522
Daniel Boulby1af2b112022-07-06 14:33:13 +0100523- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2
524 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
525 r0p1.
526
johpow0115f10bd2021-12-01 17:40:39 -0600527For Cortex-X2, the following errata build flags are defined :
528
johpow010afef362021-12-02 13:25:50 -0600529- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
530 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
531 it is still open.
532
johpow01f6c37de2021-12-03 11:27:33 -0600533- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
534 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
535 it is still open.
536
johpow0115f10bd2021-12-01 17:40:39 -0600537- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
538 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
539
Bipin Ravi2f73d972022-01-20 00:01:04 -0600540- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to
541 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
542 r2p0 of the CPU, it is fixed in r2p1.
543
Bipin Ravi9ad54782022-01-20 00:42:05 -0600544- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to
545 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
546 r2p0 of the CPU, it is fixed in r2p1.
547
Bipin Ravi78b72082022-02-06 01:29:31 -0600548- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to
549 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
550 r2p0 of the CPU, it is fixed in r2p1.
551
Bipin Ravic6b65212022-03-08 10:37:43 -0600552- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to
553 Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU,
554 it is fixed in r2p1.
555
Bipin Ravi4e315c32022-07-12 17:13:01 -0500556- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to
557 Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
558 of the CPU and is fixed in r2p1.
559
johpow01de7b5242022-01-04 16:15:18 -0600560For Cortex-A510, the following errata build flags are defined :
561
562- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
563 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is
564 fixed in r0p1.
565
johpow0149f60dd2022-01-06 14:54:49 -0600566- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to
567 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
568 r0p2, r0p3 and r1p0, it is fixed in r1p1.
569
johpow018276f252022-01-07 17:12:31 -0600570- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to
571 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
572 r0p2, it is fixed in r0p3.
573
johpow015a993002022-01-11 17:54:41 -0600574- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to
575 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
576 in r0p3. The issue is also present in r0p0 and r0p1 but there is no
577 workaround for those revisions.
578
johpow013ba9cb22022-02-13 21:00:10 -0600579- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to
580 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
581 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
582 ENABLE_MPMM=1.
583
johpow013ead2952022-02-14 20:19:08 -0600584- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to
585 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
586 r0p3 and r1p0, it is fixed in r1p1.
587
johpow01ac55c012022-02-15 22:55:22 -0600588- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to
589 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
590 r0p3 and r1p0, it is fixed in r1p1.
591
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100592DSU Errata Workarounds
593----------------------
594
595Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
596Shared Unit) errata. The DSU errata details can be found in the respective Arm
597documentation:
598
599- `Arm DSU Software Developers Errata Notice`_.
600
601Each erratum is identified by an ``ID``, as defined in the DSU errata notice
602document. Thus, the build flags which enable/disable the errata workarounds
603have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
604of DSU errata workarounds are similar to `CPU errata workarounds`_.
605
606For DSU errata, the following build flags are defined:
607
Louis Mayencourt4498b152019-04-09 16:29:01 +0100608- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
609 affected DSU configurations. This errata applies only for those DSUs that
610 revision is r0p0 (on r0p1 it is fixed). However, please note that this
611 workaround results in increased DSU power consumption on idle.
612
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100613- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
614 affected DSU configurations. This errata applies only for those DSUs that
615 contain the ACP interface **and** the DSU revision is older than r2p0 (on
616 r2p0 it is fixed). However, please note that this workaround results in
617 increased DSU power consumption on idle.
618
Bipin Raviaf40d692021-12-22 14:35:21 -0600619- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the
620 affected DSU configurations. This errata applies for those DSUs with
621 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However,
622 please note that this workaround results in increased DSU power consumption
623 on idle.
624
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100625CPU Specific optimizations
626--------------------------
627
628This section describes some of the optimizations allowed by the CPU micro
629architecture that can be enabled by the platform as desired.
630
631- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
632 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
633 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
634 of the L2 by set/way flushes any dirty lines from the L1 as well. This
635 is a known safe deviation from the Cortex-A57 TRM defined power down
636 sequence. Each Cortex-A57 based platform must make its own decision on
637 whether to use the optimization.
638
639- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
640 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
641 in a way most programmers expect, and will most probably result in a
Dan Handley610e7e12018-03-01 18:44:00 +0000642 significant speed degradation to any code that employs them. The Armv8-A
643 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100644 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
645 flag enforces this behaviour. This needs to be enabled only for revisions
646 <= r0p3 of the CPU and is enabled by default.
647
648- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
649 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
650 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
651 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
652 `Cortex-A57 Software Optimization Guide`_.
653
Varun Wadekar5ee3abc2018-06-12 16:49:12 -0700654- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable
655 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
656 this bit only if their memory system meets the requirement that cache
657 line fill requests from the Cortex-A57 processor are atomic. Each
658 Cortex-A57 based platform must make its own decision on whether to use
659 the optimization. This flag is disabled by default.
660
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100661- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last
Manish Pandey3880a362020-01-24 11:54:44 +0000662 level cache(LLC) is present in the system, and that the DataSource field
663 on the master CHI interface indicates when data is returned from the LLC.
664 This is used to control how the LL_CACHE* PMU events count.
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100665 Default value is 0 (Disabled).
Manish Pandey3880a362020-01-24 11:54:44 +0000666
Manish V Badarkhe173c2962022-05-09 21:55:19 +0100667GIC Errata Workarounds
668----------------------
669- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374
670 workaround for the affected GIC600 and GIC600-AE implementations. It applies
671 to implementations of GIC600 and GIC600-AE with revisions less than or equal
672 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600,
673 then this flag is enabled; otherwise, it is 0 (Disabled).
674
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100675--------------
676
Manish V Badarkhe173c2962022-05-09 21:55:19 +0100677*Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100678
John Tsichritzis3eeac412018-09-04 10:56:53 +0100679.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
680.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
Bipin Ravi86499742022-01-18 01:59:06 -0600681.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960
Paul Beesley2437ddc2019-02-08 16:43:05 +0000682.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
683.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100684.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100685.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100686.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html