| commit | c3b4ca1682a438c1320672528868c2ae4dd1bbcc | [log] [tgz] |
|---|---|---|
| author | Eleanor Bonnici <Eleanor.bonnici@arm.com> | Wed Aug 02 18:33:41 2017 +0100 |
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | Thu Sep 07 14:22:02 2017 +0100 |
| tree | fc6499c90c931c8d20aa7a569322fe8fb91bce53 | |
| parent | 0c9bd27d0c37e138628229c66afe3c7cbd47261d [diff] |
Cortex-A72: Implement workaround for erratum 859971 Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>