commit 7d52a8f787d9f0f7112b64256fb3af7a66f0b520
author johpow01 <john.powell@arm.com> Wed Mar 09 16:23:04 2022 -0600
committer John Powell <john.powell@arm.com> Mon May 09 20:02:10 2022 +0200
tree 882e7385a1c98ec9ea8b032695a76553cfa8fa9e
parent b22caf151dea3cefea8e3414aa9115271f6fe860

fix(errata): workaround for Cortex-A710 erratum 2008768

Cortex-A710 erratum 2008768 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to clear
the ED bit in each ERXCTLR_EL1 register before setting the PWRDN bit in
CPUPWRCTLR_EL1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib2171c06da762dd4155b02c03d86766f1616381d

docs/design/cpu-specific-build-macros.rst

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 3029458..fd2f97c 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -433,6 +433,10 @@
    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
    of the CPU and is fixed in r2p1.
 
+-  ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to
+   Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+   of the CPU and is fixed in r2p1.
+
 For Neoverse N2, the following errata build flags are defined :
 
 -  ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2