| commit | 4498b15fbb6a22b89e96796eb7d1590a71c0a56b | [log] [tgz] |
|---|---|---|
| author | Louis Mayencourt <louis.mayencourt@arm.com> | Tue Apr 09 16:29:01 2019 +0100 |
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | Wed Apr 17 13:46:43 2019 +0100 |
| tree | 1fcdb2dc74d4f1f127a9360319f3426e37c2dbf5 | |
| parent | 254f6f02374597c56a759bf1f102f977f04894df [diff] |
DSU: Implement workaround for errata 798953 Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>