| commit | 0992447183bfd227e998fbaddf40581a4f3ae05c | [log] [tgz] |
|---|---|---|
| author | Louis Mayencourt <louis.mayencourt@arm.com> | Thu Feb 21 17:35:07 2019 +0000 |
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | Tue Feb 26 16:21:06 2019 +0000 |
| tree | 0a79684da2ea12a62188da7d4415598f2a0d4398 | |
| parent | 8d868705199cb8a878f6df966567927323cf2ad5 [diff] |
Add workaround for errata 1130799 for Cortex-A76 TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page aggregated address translation data in the L2 TLB might cause corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to prevent this. Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>