Workaround for Neoverse N1 erratum 1220197
Neoverse N1 erratum 1220197 is a Cat B erratum [1],
present in older revisions of the Neoverse N1 processor core.
The workaround is to set two bits in the implementation defined
CPUECTLR_EL1 system register, which disables write streaming to the L2.
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html
Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index ef24f2e..ee8da17 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -240,6 +240,9 @@
- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1
+ CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
CPU. This needs to be enabled only for revision <= r3p0 of the CPU.