| commit | 9603f98914721a81e969d5599194e1ccd61710af | [log] [tgz] |
|---|---|---|
| author | johpow01 <john.powell@arm.com> | Fri May 29 14:17:38 2020 -0500 |
| committer | johpow01 <john.powell@arm.com> | Mon Jun 22 16:58:24 2020 -0500 |
| tree | 48bac5a436147056175a22b9c24ee099b8bee63b | |
| parent | 46c4b14113a79fc47e0fb7a14331ae760c8024d4 [diff] |
Workaround for Cortex A76 erratum 1791580 Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925