| commit | 8a061273966a0d22ddf268e2debe67ffd8df4a00 | [log] [tgz] |
|---|---|---|
| author | Louis Mayencourt <louis.mayencourt@arm.com> | Fri Apr 05 16:25:25 2019 +0100 |
| committer | Louis Mayencourt <louis.mayencourt@arm.com> | Wed Apr 17 13:46:43 2019 +0100 |
| tree | 599730f99e105a55b1733af839730a6cc204bc23 | |
| parent | a624f5936efe1281d8a5f6b9fd3f1bea6ef8d243 [diff] |
Cortex-A35: Implement workaround for errata 855472 Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>