tree 599730f99e105a55b1733af839730a6cc204bc23
parent a624f5936efe1281d8a5f6b9fd3f1bea6ef8d243
author Louis Mayencourt <louis.mayencourt@arm.com> 1554477925 +0100
committer Louis Mayencourt <louis.mayencourt@arm.com> 1555505203 +0100

Cortex-A35: Implement workaround for errata 855472

Under specific conditions, the processor might issue an eviction and an
L2 cache clean operation to the interconnect in the wrong order. Set
the CPUACTLR.ENDCCASCI bit to 1 to avoid this.

Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>