| commit | 99ad976207e012bff86d54d1201148e5b6c5b868 | [log] [tgz] |
|---|---|---|
| author | laurenw-arm <lauren.wehrmeister@arm.com> | Tue Jul 14 14:18:34 2020 -0500 |
| committer | laurenw-arm <lauren.wehrmeister@arm.com> | Fri Sep 25 15:41:56 2020 -0500 |
| tree | 20b2a75b13cec23588e00af85c5f0a91cb67f3fb | |
| parent | a6bdd6072edceebb3ea8006592a76c4736479ff1 [diff] [blame] |
Workaround for Cortex A77 erratum 1508412 Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 3c0e30f..e9ff17e 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst
@@ -251,6 +251,9 @@ For Cortex-A77, the following errata build flags are defined : +- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 + CPU. This needs to be enabled only for revision <= r1p0 of the CPU. + - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.