| commit | 4efede7c8dccd09007ac6f6e5dbf95bca31ce014 | [log] [tgz] |
|---|---|---|
| author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | Wed Dec 18 15:56:27 2019 -0600 |
| committer | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | Mon Dec 23 11:21:16 2019 -0600 |
| tree | 35a44b43b9f5f73e43ec8040107ba63d419dfdf7 | |
| parent | ce9af961eb8528162b271811174d2dfa26f102a2 [diff] |
Workaround for Hercules erratum 1688305 Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>