tree 35a44b43b9f5f73e43ec8040107ba63d419dfdf7
parent ce9af961eb8528162b271811174d2dfa26f102a2
author Madhukar Pappireddy <madhukar.pappireddy@arm.com> 1576706187 -0600
committer Madhukar Pappireddy <madhukar.pappireddy@arm.com> 1577121676 -0600

Workaround for Hercules erratum 1688305

Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.

Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>