Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 2 | /* |
| 3 | * |
| 4 | * HW data initialization for OMAP5 |
| 5 | * |
| 6 | * (C) Copyright 2013 |
| 7 | * Texas Instruments, <www.ti.com> |
| 8 | * |
| 9 | * Sricharan R <r.sricharan@ti.com> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 10 | */ |
| 11 | #include <common.h> |
Lokesh Vutla | 3685297 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 12 | #include <palmas.h> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 13 | #include <asm/arch/omap.h> |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 14 | #include <asm/arch/sys_proto.h> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 15 | #include <asm/omap_common.h> |
Lokesh Vutla | 61c517f | 2013-05-30 02:54:32 +0000 | [diff] [blame] | 16 | #include <asm/arch/clock.h> |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 17 | #include <asm/omap_gpio.h> |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 18 | #include <asm/io.h> |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 19 | #include <asm/emif.h> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 20 | |
| 21 | struct prcm_regs const **prcm = |
| 22 | (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 23 | struct dplls const **dplls_data = |
| 24 | (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 25 | struct vcores_data const **omap_vcores = |
| 26 | (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; |
Lokesh Vutla | 834b6b0 | 2013-02-04 04:22:04 +0000 | [diff] [blame] | 27 | struct omap_sys_ctrl_regs const **ctrl = |
SRICHARAN R | 4b1b61c | 2013-04-24 00:41:22 +0000 | [diff] [blame] | 28 | (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 29 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 30 | /* OPP NOM FREQUENCY for ES1.0 */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 31 | static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 32 | {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 33 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 34 | {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 35 | {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 36 | {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 37 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 38 | {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 39 | }; |
| 40 | |
Lokesh Vutla | c9e70e2 | 2013-12-12 15:36:21 +0530 | [diff] [blame] | 41 | /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 42 | static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 43 | {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 44 | {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 45 | {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 46 | {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 47 | {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 48 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 49 | {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 50 | }; |
| 51 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 52 | static const struct dpll_params |
| 53 | core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 54 | {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ |
| 55 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 56 | {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ |
| 57 | {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ |
| 58 | {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ |
| 59 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 60 | {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | static const struct dpll_params |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 64 | core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { |
| 65 | {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ |
| 66 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 67 | {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ |
| 68 | {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ |
| 69 | {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ |
| 70 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 71 | {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ |
| 72 | }; |
| 73 | |
| 74 | static const struct dpll_params |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 75 | core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { |
| 76 | {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ |
| 77 | {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ |
| 78 | {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ |
| 79 | {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ |
| 80 | {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 81 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 82 | {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 83 | }; |
| 84 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 85 | static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 86 | {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ |
| 87 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 88 | {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 89 | {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 90 | {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ |
| 91 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 92 | {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ |
| 93 | }; |
| 94 | |
| 95 | static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { |
| 96 | {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ |
| 97 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 98 | {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 99 | {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 100 | {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ |
| 101 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 102 | {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 103 | }; |
| 104 | |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 105 | static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { |
Lokesh Vutla | ff21205 | 2013-12-12 15:34:56 +0530 | [diff] [blame] | 106 | {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ |
Lokesh Vutla | 087cdb3 | 2016-07-25 15:45:44 +0530 | [diff] [blame] | 107 | {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ |
Lokesh Vutla | ff21205 | 2013-12-12 15:34:56 +0530 | [diff] [blame] | 108 | {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 109 | {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 110 | {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 111 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | ff21205 | 2013-12-12 15:34:56 +0530 | [diff] [blame] | 112 | {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 113 | }; |
| 114 | |
Praneeth Bajjuri | 9b21ff4 | 2017-08-21 12:50:52 +0530 | [diff] [blame] | 115 | static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = { |
| 116 | {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */ |
| 117 | {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */ |
| 118 | {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 119 | {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 120 | {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */ |
| 121 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 122 | {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 123 | }; |
| 124 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 125 | static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 126 | {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 127 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 128 | {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 129 | {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 130 | {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 131 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 132 | {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 133 | }; |
| 134 | |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 135 | static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { |
| 136 | {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 137 | {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 138 | {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 139 | {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 140 | {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 141 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 142 | {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 143 | }; |
| 144 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 145 | /* ABE M & N values with sys_clk as source */ |
Lokesh Vutla | 47ea168 | 2017-01-17 08:52:59 +0530 | [diff] [blame] | 146 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 147 | static const struct dpll_params |
| 148 | abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 149 | {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 150 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 151 | {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 152 | {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 153 | {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 154 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 155 | {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 156 | }; |
Lokesh Vutla | 47ea168 | 2017-01-17 08:52:59 +0530 | [diff] [blame] | 157 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 158 | |
| 159 | /* ABE M & N values with 32K clock as source */ |
Lokesh Vutla | 47ea168 | 2017-01-17 08:52:59 +0530 | [diff] [blame] | 160 | #ifndef CONFIG_SYS_OMAP_ABE_SYSCK |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 161 | static const struct dpll_params abe_dpll_params_32k_196608khz = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 162 | 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 163 | }; |
Lokesh Vutla | 47ea168 | 2017-01-17 08:52:59 +0530 | [diff] [blame] | 164 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 165 | |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 166 | /* ABE M & N values with sysclk2(22.5792 MHz) as input */ |
| 167 | static const struct dpll_params |
| 168 | abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { |
| 169 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 170 | {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 171 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 172 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 173 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 174 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 175 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 176 | }; |
| 177 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 178 | static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 179 | {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 180 | {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 181 | {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 182 | {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 183 | {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 184 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 185 | {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 186 | }; |
| 187 | |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 188 | static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { |
| 189 | {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 190 | {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 191 | {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 192 | {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 193 | {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 194 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 195 | {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 196 | }; |
| 197 | |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 198 | static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { |
| 199 | {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 200 | {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 201 | {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 202 | {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 203 | {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 204 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 205 | {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 206 | }; |
| 207 | |
Lokesh Vutla | adc52df | 2013-07-08 16:04:39 +0530 | [diff] [blame] | 208 | static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { |
| 209 | {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 210 | {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 211 | {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 212 | {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 213 | {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 214 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 215 | {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 216 | }; |
| 217 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 218 | struct dplls omap5_dplls_es1 = { |
| 219 | .mpu = mpu_dpll_params_800mhz, |
| 220 | .core = core_dpll_params_2128mhz_ddr532, |
| 221 | .per = per_dpll_params_768mhz, |
| 222 | .iva = iva_dpll_params_2330mhz, |
| 223 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 224 | .abe = abe_dpll_params_sysclk_196608khz, |
| 225 | #else |
| 226 | .abe = &abe_dpll_params_32k_196608khz, |
| 227 | #endif |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 228 | .usb = usb_dpll_params_1920mhz, |
| 229 | .ddr = NULL |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 230 | }; |
| 231 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 232 | struct dplls omap5_dplls_es2 = { |
Lokesh Vutla | c9e70e2 | 2013-12-12 15:36:21 +0530 | [diff] [blame] | 233 | .mpu = mpu_dpll_params_1ghz, |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 234 | .core = core_dpll_params_2128mhz_ddr532_es2, |
| 235 | .per = per_dpll_params_768mhz_es2, |
| 236 | .iva = iva_dpll_params_2330mhz, |
| 237 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 238 | .abe = abe_dpll_params_sysclk_196608khz, |
| 239 | #else |
| 240 | .abe = &abe_dpll_params_32k_196608khz, |
| 241 | #endif |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 242 | .usb = usb_dpll_params_1920mhz, |
| 243 | .ddr = NULL |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 244 | }; |
| 245 | |
Praneeth Bajjuri | 9b21ff4 | 2017-08-21 12:50:52 +0530 | [diff] [blame] | 246 | struct dplls dra76x_dplls = { |
| 247 | .mpu = mpu_dpll_params_1ghz, |
| 248 | .core = core_dpll_params_2128mhz_dra7xx, |
| 249 | .per = per_dpll_params_768mhz_dra76x, |
| 250 | .abe = abe_dpll_params_sysclk2_361267khz, |
| 251 | .iva = iva_dpll_params_2330mhz_dra7xx, |
| 252 | .usb = usb_dpll_params_1920mhz, |
| 253 | .ddr = ddr_dpll_params_2664mhz, |
| 254 | .gmac = gmac_dpll_params_2000mhz, |
| 255 | }; |
| 256 | |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 257 | struct dplls dra7xx_dplls = { |
| 258 | .mpu = mpu_dpll_params_1ghz, |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 259 | .core = core_dpll_params_2128mhz_dra7xx, |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 260 | .per = per_dpll_params_768mhz_dra7xx, |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 261 | .abe = abe_dpll_params_sysclk2_361267khz, |
| 262 | .iva = iva_dpll_params_2330mhz_dra7xx, |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 263 | .usb = usb_dpll_params_1920mhz, |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 264 | .ddr = ddr_dpll_params_2128mhz, |
Lokesh Vutla | adc52df | 2013-07-08 16:04:39 +0530 | [diff] [blame] | 265 | .gmac = gmac_dpll_params_2000mhz, |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 266 | }; |
| 267 | |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 268 | struct dplls dra72x_dplls = { |
| 269 | .mpu = mpu_dpll_params_1ghz, |
| 270 | .core = core_dpll_params_2128mhz_dra7xx, |
| 271 | .per = per_dpll_params_768mhz_dra7xx, |
| 272 | .abe = abe_dpll_params_sysclk2_361267khz, |
| 273 | .iva = iva_dpll_params_2330mhz_dra7xx, |
| 274 | .usb = usb_dpll_params_1920mhz, |
| 275 | .ddr = ddr_dpll_params_2664mhz, |
| 276 | .gmac = gmac_dpll_params_2000mhz, |
| 277 | }; |
| 278 | |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 279 | struct pmic_data palmas = { |
| 280 | .base_offset = PALMAS_SMPS_BASE_VOLT_UV, |
| 281 | .step = 10000, /* 10 mV represented in uV */ |
| 282 | /* |
| 283 | * Offset codes 1-6 all give the base voltage in Palmas |
| 284 | * Offset code 0 switches OFF the SMPS |
| 285 | */ |
| 286 | .start_code = 6, |
Lokesh Vutla | ae49f6d | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 287 | .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, |
| 288 | .pmic_bus_init = sri2c_init, |
| 289 | .pmic_write = omap_vc_bypass_send_value, |
Lokesh Vutla | 266b23a | 2016-08-17 16:25:35 +0530 | [diff] [blame] | 290 | .gpio_en = 0, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 291 | }; |
| 292 | |
Lubomir Popov | 21f3406 | 2014-12-19 17:34:31 +0200 | [diff] [blame] | 293 | /* The TPS659038 and TPS65917 are software-compatible, use common struct */ |
Lokesh Vutla | 3685297 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 294 | struct pmic_data tps659038 = { |
| 295 | .base_offset = PALMAS_SMPS_BASE_VOLT_UV, |
| 296 | .step = 10000, /* 10 mV represented in uV */ |
| 297 | /* |
| 298 | * Offset codes 1-6 all give the base voltage in Palmas |
| 299 | * Offset code 0 switches OFF the SMPS |
| 300 | */ |
| 301 | .start_code = 6, |
| 302 | .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, |
| 303 | .pmic_bus_init = gpi2c_init, |
| 304 | .pmic_write = palmas_i2c_write_u8, |
Lokesh Vutla | 266b23a | 2016-08-17 16:25:35 +0530 | [diff] [blame] | 305 | .gpio_en = 0, |
Lokesh Vutla | 3685297 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 306 | }; |
| 307 | |
Keerthy | 1b21f55 | 2017-08-21 12:50:54 +0530 | [diff] [blame] | 308 | /* The LP87565*/ |
| 309 | struct pmic_data lp87565 = { |
| 310 | .base_offset = LP873X_BUCK_BASE_VOLT_UV, |
| 311 | .step = 5000, /* 5 mV represented in uV */ |
| 312 | /* |
| 313 | * Offset codes 0 - 0x13 Invalid. |
| 314 | * Offset codes 0x14 0x17 give 10mV steps |
| 315 | * Offset codes 0x17 through 0x9D give 5mV steps |
| 316 | * So let us start with our operating range from .73V |
| 317 | */ |
| 318 | .start_code = 0x17, |
| 319 | .i2c_slave_addr = 0x60, |
| 320 | .pmic_bus_init = gpi2c_init, |
| 321 | .pmic_write = palmas_i2c_write_u8, |
| 322 | }; |
| 323 | |
Keerthy | 4d4e34b | 2016-11-23 13:25:27 +0530 | [diff] [blame] | 324 | /* The LP8732 and LP8733 are software-compatible, use common struct */ |
| 325 | struct pmic_data lp8733 = { |
| 326 | .base_offset = LP873X_BUCK_BASE_VOLT_UV, |
| 327 | .step = 5000, /* 5 mV represented in uV */ |
| 328 | /* |
| 329 | * Offset codes 0 - 0x13 Invalid. |
| 330 | * Offset codes 0x14 0x17 give 10mV steps |
| 331 | * Offset codes 0x17 through 0x9D give 5mV steps |
| 332 | * So let us start with our operating range from .73V |
| 333 | */ |
| 334 | .start_code = 0x17, |
| 335 | .i2c_slave_addr = 0x60, |
| 336 | .pmic_bus_init = gpi2c_init, |
| 337 | .pmic_write = palmas_i2c_write_u8, |
| 338 | }; |
| 339 | |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 340 | struct vcores_data omap5430_volts = { |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 341 | .mpu.value[OPP_NOM] = VDD_MPU, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 342 | .mpu.addr = SMPS_REG_ADDR_12_MPU, |
| 343 | .mpu.pmic = &palmas, |
| 344 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 345 | .core.value[OPP_NOM] = VDD_CORE, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 346 | .core.addr = SMPS_REG_ADDR_8_CORE, |
| 347 | .core.pmic = &palmas, |
| 348 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 349 | .mm.value[OPP_NOM] = VDD_MM, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 350 | .mm.addr = SMPS_REG_ADDR_45_IVA, |
| 351 | .mm.pmic = &palmas, |
| 352 | }; |
| 353 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 354 | struct vcores_data omap5430_volts_es2 = { |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 355 | .mpu.value[OPP_NOM] = VDD_MPU_ES2, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 356 | .mpu.addr = SMPS_REG_ADDR_12_MPU, |
| 357 | .mpu.pmic = &palmas, |
Nishanth Menon | 1eb62b4 | 2016-04-21 14:34:23 -0500 | [diff] [blame] | 358 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 359 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 360 | .core.value[OPP_NOM] = VDD_CORE_ES2, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 361 | .core.addr = SMPS_REG_ADDR_8_CORE, |
| 362 | .core.pmic = &palmas, |
| 363 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 364 | .mm.value[OPP_NOM] = VDD_MM_ES2, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 365 | .mm.addr = SMPS_REG_ADDR_45_IVA, |
| 366 | .mm.pmic = &palmas, |
Nishanth Menon | 07be757 | 2016-04-21 14:34:24 -0500 | [diff] [blame] | 367 | .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, |
Nishanth Menon | 159a21f | 2017-08-04 21:42:09 -0500 | [diff] [blame] | 368 | |
| 369 | .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN, |
| 370 | .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, |
| 371 | |
| 372 | .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN, |
| 373 | .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, |
| 374 | |
| 375 | .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN, |
| 376 | .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 377 | }; |
| 378 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 379 | /* |
Keerthy | 0efb06d | 2022-01-27 13:16:52 +0100 | [diff] [blame^] | 380 | * Enable IPU1 clock domains, modules and |
| 381 | * do some additional special settings needed |
| 382 | */ |
| 383 | void enable_ipu1_clocks(void) |
| 384 | { |
| 385 | if (!IS_ENABLED(CONFIG_DRA7XX) || |
| 386 | !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) |
| 387 | return; |
| 388 | |
| 389 | u32 const clk_domains[] = { |
| 390 | (*prcm)->cm_ipu_clkstctrl, |
| 391 | (*prcm)->cm_ipu1_clkstctrl, |
| 392 | 0 |
| 393 | }; |
| 394 | |
| 395 | u32 const clk_modules_hw_auto_essential[] = { |
| 396 | (*prcm)->cm_ipu1_ipu1_clkctrl, |
| 397 | 0 |
| 398 | }; |
| 399 | |
| 400 | u32 const clk_modules_explicit_en_essential[] = { |
| 401 | (*prcm)->cm_l4per_gptimer11_clkctrl, |
| 402 | (*prcm)->cm1_abe_timer7_clkctrl, |
| 403 | (*prcm)->cm1_abe_timer8_clkctrl, |
| 404 | 0 |
| 405 | }; |
| 406 | do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential, |
| 407 | clk_modules_explicit_en_essential, 0); |
| 408 | |
| 409 | /* Enable optional additional functional clock for IPU1 */ |
| 410 | setbits_le32((*prcm)->cm_ipu1_ipu1_clkctrl, |
| 411 | IPU1_CLKCTRL_CLKSEL_MASK); |
| 412 | /* Enable optional additional functional clock for IPU1 */ |
| 413 | setbits_le32((*prcm)->cm1_abe_timer7_clkctrl, |
| 414 | IPU1_CLKCTRL_CLKSEL_MASK); |
| 415 | /* Enable optional additional functional clock for IPU1 */ |
| 416 | setbits_le32((*prcm)->cm1_abe_timer8_clkctrl, |
| 417 | IPU1_CLKCTRL_CLKSEL_MASK); |
| 418 | } |
| 419 | |
| 420 | /* |
| 421 | * Enable IPU2 clock domains, modules and |
| 422 | * do some additional special settings needed |
| 423 | */ |
| 424 | void enable_ipu2_clocks(void) |
| 425 | { |
| 426 | if (!IS_ENABLED(CONFIG_DRA7XX) || |
| 427 | !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) |
| 428 | return; |
| 429 | |
| 430 | u32 const clk_domains[] = { |
| 431 | (*prcm)->cm_ipu_clkstctrl, |
| 432 | (*prcm)->cm_ipu2_clkstctrl, |
| 433 | 0 |
| 434 | }; |
| 435 | |
| 436 | u32 const clk_modules_hw_auto_essential[] = { |
| 437 | (*prcm)->cm_ipu2_ipu2_clkctrl, |
| 438 | 0 |
| 439 | }; |
| 440 | |
| 441 | u32 const clk_modules_explicit_en_essential[] = { |
| 442 | (*prcm)->cm_l4per_gptimer3_clkctrl, |
| 443 | (*prcm)->cm_l4per_gptimer4_clkctrl, |
| 444 | (*prcm)->cm_l4per_gptimer9_clkctrl, |
| 445 | 0 |
| 446 | }; |
| 447 | do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential, |
| 448 | clk_modules_explicit_en_essential, 0); |
| 449 | |
| 450 | /* Enable optional additional functional clock for IPU2 */ |
| 451 | setbits_le32((*prcm)->cm_l4per_gptimer4_clkctrl, |
| 452 | IPU1_CLKCTRL_CLKSEL_MASK); |
| 453 | /* Enable optional additional functional clock for IPU2 */ |
| 454 | setbits_le32((*prcm)->cm_l4per_gptimer9_clkctrl, |
| 455 | IPU1_CLKCTRL_CLKSEL_MASK); |
| 456 | } |
| 457 | |
| 458 | /* |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 459 | * Enable essential clock domains, modules and |
| 460 | * do some additional special settings needed |
| 461 | */ |
| 462 | void enable_basic_clocks(void) |
| 463 | { |
| 464 | u32 const clk_domains_essential[] = { |
| 465 | (*prcm)->cm_l4per_clkstctrl, |
| 466 | (*prcm)->cm_l3init_clkstctrl, |
| 467 | (*prcm)->cm_memif_clkstctrl, |
| 468 | (*prcm)->cm_l4cfg_clkstctrl, |
Mugunthan V N | 4a42ff1 | 2013-07-08 16:04:40 +0530 | [diff] [blame] | 469 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 470 | (*prcm)->cm_gmac_clkstctrl, |
| 471 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 472 | 0 |
| 473 | }; |
| 474 | |
| 475 | u32 const clk_modules_hw_auto_essential[] = { |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 476 | (*prcm)->cm_l3_gpmc_clkctrl, |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 477 | (*prcm)->cm_memif_emif_1_clkctrl, |
| 478 | (*prcm)->cm_memif_emif_2_clkctrl, |
| 479 | (*prcm)->cm_l4cfg_l4_cfg_clkctrl, |
| 480 | (*prcm)->cm_wkup_gpio1_clkctrl, |
| 481 | (*prcm)->cm_l4per_gpio2_clkctrl, |
| 482 | (*prcm)->cm_l4per_gpio3_clkctrl, |
| 483 | (*prcm)->cm_l4per_gpio4_clkctrl, |
| 484 | (*prcm)->cm_l4per_gpio5_clkctrl, |
| 485 | (*prcm)->cm_l4per_gpio6_clkctrl, |
Axel Lin | 01a461f | 2013-06-21 18:54:25 +0800 | [diff] [blame] | 486 | (*prcm)->cm_l4per_gpio7_clkctrl, |
| 487 | (*prcm)->cm_l4per_gpio8_clkctrl, |
Mugunthan V N | d7ced25 | 2017-04-07 13:42:00 +0200 | [diff] [blame] | 488 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 489 | (*prcm)->cm_l3init_ocp2scp3_clkctrl, |
| 490 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 491 | 0 |
| 492 | }; |
| 493 | |
| 494 | u32 const clk_modules_explicit_en_essential[] = { |
| 495 | (*prcm)->cm_wkup_gptimer1_clkctrl, |
| 496 | (*prcm)->cm_l3init_hsmmc1_clkctrl, |
| 497 | (*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 498 | (*prcm)->cm_l4per_gptimer2_clkctrl, |
| 499 | (*prcm)->cm_wkup_wdtimer2_clkctrl, |
Caleb Robey | 940d637 | 2020-01-02 08:17:27 -0600 | [diff] [blame] | 500 | (*prcm)->cm_l4per_uart1_clkctrl, |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 501 | (*prcm)->cm_l4per_uart3_clkctrl, |
| 502 | (*prcm)->cm_l4per_i2c1_clkctrl, |
Mugunthan V N | 4a42ff1 | 2013-07-08 16:04:40 +0530 | [diff] [blame] | 503 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 504 | (*prcm)->cm_gmac_gmac_clkctrl, |
| 505 | #endif |
Matt Porter | 3074626 | 2013-10-07 15:52:59 +0530 | [diff] [blame] | 506 | |
| 507 | #ifdef CONFIG_TI_QSPI |
| 508 | (*prcm)->cm_l4per_qspi_clkctrl, |
| 509 | #endif |
Mugunthan V N | d7ced25 | 2017-04-07 13:42:00 +0200 | [diff] [blame] | 510 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 511 | (*prcm)->cm_l3init_sata_clkctrl, |
| 512 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 513 | 0 |
| 514 | }; |
| 515 | |
| 516 | /* Enable optional additional functional clock for GPIO4 */ |
| 517 | setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, |
| 518 | GPIO4_CLKCTRL_OPTFCLKEN_MASK); |
| 519 | |
Kishon Vijay Abraham I | c76d616 | 2018-01-30 16:01:47 +0100 | [diff] [blame] | 520 | /* Enable 192 MHz clock for MMC1 & MMC2 */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 521 | setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, |
| 522 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 523 | setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 524 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 525 | |
| 526 | /* Set the correct clock dividers for mmc */ |
Kishon Vijay Abraham I | c76d616 | 2018-01-30 16:01:47 +0100 | [diff] [blame] | 527 | clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, |
| 528 | HSMMC_CLKCTRL_CLKSEL_DIV_MASK); |
| 529 | clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 530 | HSMMC_CLKCTRL_CLKSEL_DIV_MASK); |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 531 | |
| 532 | /* Select 32KHz clock as the source of GPTIMER1 */ |
| 533 | setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, |
| 534 | GPTIMER1_CLKCTRL_CLKSEL_MASK); |
| 535 | |
| 536 | do_enable_clocks(clk_domains_essential, |
| 537 | clk_modules_hw_auto_essential, |
| 538 | clk_modules_explicit_en_essential, |
| 539 | 1); |
| 540 | |
Matt Porter | 3074626 | 2013-10-07 15:52:59 +0530 | [diff] [blame] | 541 | #ifdef CONFIG_TI_QSPI |
| 542 | setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); |
| 543 | #endif |
| 544 | |
Mugunthan V N | d7ced25 | 2017-04-07 13:42:00 +0200 | [diff] [blame] | 545 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 546 | /* Enable optional functional clock for SATA */ |
| 547 | setbits_le32((*prcm)->cm_l3init_sata_clkctrl, |
| 548 | SATA_CLKCTRL_OPTFCLKEN_MASK); |
| 549 | #endif |
| 550 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 551 | /* Enable SCRM OPT clocks for PER and CORE dpll */ |
| 552 | setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, |
| 553 | OPTFCLKEN_SCRM_PER_MASK); |
| 554 | setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, |
| 555 | OPTFCLKEN_SCRM_CORE_MASK); |
| 556 | } |
| 557 | |
| 558 | void enable_basic_uboot_clocks(void) |
| 559 | { |
Keerthy | 0efb06d | 2022-01-27 13:16:52 +0100 | [diff] [blame^] | 560 | u32 cm_ipu_clkstctrl = 0; |
| 561 | |
| 562 | if (IS_ENABLED(CONFIG_DRA7XX) && |
| 563 | !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) |
| 564 | cm_ipu_clkstctrl = (*prcm)->cm_ipu_clkstctrl; |
| 565 | |
| 566 | u32 const clk_domains_essential[] = {cm_ipu_clkstctrl, 0}; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 567 | |
| 568 | u32 const clk_modules_hw_auto_essential[] = { |
Lubomir Popov | 6535403 | 2013-04-11 00:08:51 +0000 | [diff] [blame] | 569 | (*prcm)->cm_l3init_hsusbtll_clkctrl, |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 570 | 0 |
| 571 | }; |
| 572 | |
| 573 | u32 const clk_modules_explicit_en_essential[] = { |
| 574 | (*prcm)->cm_l4per_mcspi1_clkctrl, |
| 575 | (*prcm)->cm_l4per_i2c2_clkctrl, |
| 576 | (*prcm)->cm_l4per_i2c3_clkctrl, |
| 577 | (*prcm)->cm_l4per_i2c4_clkctrl, |
Nishanth Menon | 813fe9d | 2016-11-29 15:22:00 +0530 | [diff] [blame] | 578 | #if defined(CONFIG_DRA7XX) |
Lokesh Vutla | b04038f | 2015-06-05 15:19:21 +0530 | [diff] [blame] | 579 | (*prcm)->cm_ipu_i2c5_clkctrl, |
| 580 | #else |
Lubomir Popov | b36e609 | 2013-04-08 21:49:37 +0000 | [diff] [blame] | 581 | (*prcm)->cm_l4per_i2c5_clkctrl, |
Lokesh Vutla | b04038f | 2015-06-05 15:19:21 +0530 | [diff] [blame] | 582 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 583 | (*prcm)->cm_l3init_hsusbhost_clkctrl, |
| 584 | (*prcm)->cm_l3init_fsusb_clkctrl, |
| 585 | 0 |
| 586 | }; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 587 | do_enable_clocks(clk_domains_essential, |
| 588 | clk_modules_hw_auto_essential, |
| 589 | clk_modules_explicit_en_essential, |
| 590 | 1); |
| 591 | } |
| 592 | |
Vignesh R | 92dc6a0 | 2015-08-17 13:29:52 +0530 | [diff] [blame] | 593 | #ifdef CONFIG_TI_EDMA3 |
| 594 | void enable_edma3_clocks(void) |
| 595 | { |
| 596 | u32 const clk_domains_edma3[] = { |
| 597 | 0 |
| 598 | }; |
| 599 | |
| 600 | u32 const clk_modules_hw_auto_edma3[] = { |
| 601 | (*prcm)->cm_l3main1_tptc1_clkctrl, |
| 602 | (*prcm)->cm_l3main1_tptc2_clkctrl, |
| 603 | 0 |
| 604 | }; |
| 605 | |
| 606 | u32 const clk_modules_explicit_en_edma3[] = { |
| 607 | 0 |
| 608 | }; |
| 609 | |
| 610 | do_enable_clocks(clk_domains_edma3, |
| 611 | clk_modules_hw_auto_edma3, |
| 612 | clk_modules_explicit_en_edma3, |
| 613 | 1); |
| 614 | } |
| 615 | |
| 616 | void disable_edma3_clocks(void) |
| 617 | { |
| 618 | u32 const clk_domains_edma3[] = { |
| 619 | 0 |
| 620 | }; |
| 621 | |
| 622 | u32 const clk_modules_disable_edma3[] = { |
| 623 | (*prcm)->cm_l3main1_tptc1_clkctrl, |
| 624 | (*prcm)->cm_l3main1_tptc2_clkctrl, |
| 625 | 0 |
| 626 | }; |
| 627 | |
| 628 | do_disable_clocks(clk_domains_edma3, |
| 629 | clk_modules_disable_edma3, |
| 630 | 1); |
| 631 | } |
| 632 | #endif |
| 633 | |
Roger Quadros | 16c9710 | 2016-05-23 17:37:47 +0300 | [diff] [blame] | 634 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 635 | void enable_usb_clocks(int index) |
| 636 | { |
| 637 | u32 cm_l3init_usb_otg_ss_clkctrl = 0; |
| 638 | |
| 639 | if (index == 0) { |
| 640 | cm_l3init_usb_otg_ss_clkctrl = |
| 641 | (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; |
| 642 | /* Enable 960 MHz clock for dwc3 */ |
| 643 | setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, |
| 644 | OPTFCLKEN_REFCLK960M); |
| 645 | |
Roger Quadros | f125894 | 2016-05-23 17:37:49 +0300 | [diff] [blame] | 646 | /* Enable 32 KHz clock for USB_PHY1 */ |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 647 | setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, |
| 648 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
Roger Quadros | f125894 | 2016-05-23 17:37:49 +0300 | [diff] [blame] | 649 | |
| 650 | /* Enable 32 KHz clock for USB_PHY3 */ |
| 651 | if (is_dra7xx()) |
| 652 | setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, |
| 653 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 654 | } else if (index == 1) { |
| 655 | cm_l3init_usb_otg_ss_clkctrl = |
| 656 | (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; |
| 657 | /* Enable 960 MHz clock for dwc3 */ |
| 658 | setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, |
| 659 | OPTFCLKEN_REFCLK960M); |
| 660 | |
| 661 | /* Enable 32 KHz clock for dwc3 */ |
| 662 | setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, |
| 663 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
| 664 | |
| 665 | /* Enable 60 MHz clock for USB2PHY2 */ |
| 666 | setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, |
| 667 | L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); |
| 668 | } |
| 669 | |
| 670 | u32 const clk_domains_usb[] = { |
| 671 | 0 |
| 672 | }; |
| 673 | |
| 674 | u32 const clk_modules_hw_auto_usb[] = { |
| 675 | (*prcm)->cm_l3init_ocp2scp1_clkctrl, |
| 676 | cm_l3init_usb_otg_ss_clkctrl, |
| 677 | 0 |
| 678 | }; |
| 679 | |
| 680 | u32 const clk_modules_explicit_en_usb[] = { |
| 681 | 0 |
| 682 | }; |
| 683 | |
| 684 | do_enable_clocks(clk_domains_usb, |
| 685 | clk_modules_hw_auto_usb, |
| 686 | clk_modules_explicit_en_usb, |
| 687 | 1); |
| 688 | } |
| 689 | |
| 690 | void disable_usb_clocks(int index) |
| 691 | { |
| 692 | u32 cm_l3init_usb_otg_ss_clkctrl = 0; |
| 693 | |
| 694 | if (index == 0) { |
| 695 | cm_l3init_usb_otg_ss_clkctrl = |
| 696 | (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; |
| 697 | /* Disable 960 MHz clock for dwc3 */ |
| 698 | clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, |
| 699 | OPTFCLKEN_REFCLK960M); |
| 700 | |
Roger Quadros | f125894 | 2016-05-23 17:37:49 +0300 | [diff] [blame] | 701 | /* Disable 32 KHz clock for USB_PHY1 */ |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 702 | clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, |
| 703 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
Roger Quadros | f125894 | 2016-05-23 17:37:49 +0300 | [diff] [blame] | 704 | |
| 705 | /* Disable 32 KHz clock for USB_PHY3 */ |
| 706 | if (is_dra7xx()) |
| 707 | clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, |
| 708 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 709 | } else if (index == 1) { |
| 710 | cm_l3init_usb_otg_ss_clkctrl = |
| 711 | (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; |
| 712 | /* Disable 960 MHz clock for dwc3 */ |
| 713 | clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, |
| 714 | OPTFCLKEN_REFCLK960M); |
| 715 | |
| 716 | /* Disable 32 KHz clock for dwc3 */ |
| 717 | clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, |
| 718 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
| 719 | |
| 720 | /* Disable 60 MHz clock for USB2PHY2 */ |
| 721 | clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, |
| 722 | L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); |
| 723 | } |
| 724 | |
| 725 | u32 const clk_domains_usb[] = { |
| 726 | 0 |
| 727 | }; |
| 728 | |
| 729 | u32 const clk_modules_disable[] = { |
| 730 | (*prcm)->cm_l3init_ocp2scp1_clkctrl, |
| 731 | cm_l3init_usb_otg_ss_clkctrl, |
| 732 | 0 |
| 733 | }; |
| 734 | |
| 735 | do_disable_clocks(clk_domains_usb, |
| 736 | clk_modules_disable, |
| 737 | 1); |
| 738 | } |
| 739 | #endif |
| 740 | |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 741 | const struct ctrl_ioregs ioregs_omap5430 = { |
| 742 | .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, |
| 743 | .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, |
| 744 | .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, |
| 745 | .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, |
| 746 | .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, |
| 747 | }; |
| 748 | |
| 749 | const struct ctrl_ioregs ioregs_omap5432_es1 = { |
| 750 | .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, |
| 751 | .ctrl_lpddr2ch = 0x0, |
| 752 | .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, |
| 753 | .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, |
| 754 | .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, |
| 755 | .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, |
| 756 | .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, |
SRICHARAN R | e02f5f8 | 2013-11-08 17:40:37 +0530 | [diff] [blame] | 757 | .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 758 | }; |
| 759 | |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 760 | const struct ctrl_ioregs ioregs_omap5432_es2 = { |
| 761 | .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, |
| 762 | .ctrl_lpddr2ch = 0x0, |
| 763 | .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, |
| 764 | .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, |
| 765 | .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, |
| 766 | .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, |
| 767 | .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, |
SRICHARAN R | e02f5f8 | 2013-11-08 17:40:37 +0530 | [diff] [blame] | 768 | .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 769 | }; |
| 770 | |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 771 | const struct ctrl_ioregs ioregs_dra7xx_es1 = { |
| 772 | .ctrl_ddrch = 0x40404040, |
| 773 | .ctrl_lpddr2ch = 0x40404040, |
| 774 | .ctrl_ddr3ch = 0x80808080, |
Lokesh Vutla | 07fbc33 | 2015-06-03 14:43:27 +0530 | [diff] [blame] | 775 | .ctrl_ddrio_0 = 0x00094A40, |
| 776 | .ctrl_ddrio_1 = 0x04A52000, |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 777 | .ctrl_ddrio_2 = 0x84210000, |
Nishanth Menon | f013a3a | 2015-06-16 08:29:01 -0500 | [diff] [blame] | 778 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, |
| 779 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 780 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, |
| 781 | }; |
| 782 | |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 783 | const struct ctrl_ioregs ioregs_dra72x_es1 = { |
| 784 | .ctrl_ddrch = 0x40404040, |
| 785 | .ctrl_lpddr2ch = 0x40404040, |
| 786 | .ctrl_ddr3ch = 0x60606080, |
Lokesh Vutla | 07fbc33 | 2015-06-03 14:43:27 +0530 | [diff] [blame] | 787 | .ctrl_ddrio_0 = 0x00094A40, |
| 788 | .ctrl_ddrio_1 = 0x04A52000, |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 789 | .ctrl_ddrio_2 = 0x84210000, |
Nishanth Menon | f013a3a | 2015-06-16 08:29:01 -0500 | [diff] [blame] | 790 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, |
| 791 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 792 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, |
| 793 | }; |
| 794 | |
Nishanth Menon | 3269997 | 2016-03-15 18:09:12 -0500 | [diff] [blame] | 795 | const struct ctrl_ioregs ioregs_dra72x_es2 = { |
| 796 | .ctrl_ddrch = 0x40404040, |
| 797 | .ctrl_lpddr2ch = 0x40404040, |
| 798 | .ctrl_ddr3ch = 0x60606060, |
| 799 | .ctrl_ddrio_0 = 0x00094A40, |
| 800 | .ctrl_ddrio_1 = 0x00000000, |
| 801 | .ctrl_ddrio_2 = 0x00000000, |
| 802 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, |
| 803 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, |
| 804 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, |
| 805 | }; |
| 806 | |
Felipe Balbi | 449a437 | 2014-11-06 08:28:48 -0600 | [diff] [blame] | 807 | void __weak hw_data_init(void) |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 808 | { |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 809 | u32 omap_rev = omap_revision(); |
| 810 | |
| 811 | switch (omap_rev) { |
| 812 | |
| 813 | case OMAP5430_ES1_0: |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 814 | case OMAP5432_ES1_0: |
| 815 | *prcm = &omap5_es1_prcm; |
| 816 | *dplls_data = &omap5_dplls_es1; |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 817 | *omap_vcores = &omap5430_volts; |
Lokesh Vutla | f120cef | 2013-02-12 21:29:06 +0000 | [diff] [blame] | 818 | *ctrl = &omap5_ctrl; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 819 | break; |
| 820 | |
SRICHARAN R | 06ebff4 | 2013-02-12 01:33:42 +0000 | [diff] [blame] | 821 | case OMAP5430_ES2_0: |
| 822 | case OMAP5432_ES2_0: |
| 823 | *prcm = &omap5_es2_prcm; |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 824 | *dplls_data = &omap5_dplls_es2; |
| 825 | *omap_vcores = &omap5430_volts_es2; |
Lokesh Vutla | f120cef | 2013-02-12 21:29:06 +0000 | [diff] [blame] | 826 | *ctrl = &omap5_ctrl; |
SRICHARAN R | 06ebff4 | 2013-02-12 01:33:42 +0000 | [diff] [blame] | 827 | break; |
| 828 | |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 829 | case DRA762_ABZ_ES1_0: |
| 830 | case DRA762_ACD_ES1_0: |
Praneeth Bajjuri | 9b21ff4 | 2017-08-21 12:50:52 +0530 | [diff] [blame] | 831 | case DRA762_ES1_0: |
| 832 | *prcm = &dra7xx_prcm; |
| 833 | *dplls_data = &dra76x_dplls; |
| 834 | *ctrl = &dra7xx_ctrl; |
| 835 | break; |
| 836 | |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 837 | case DRA752_ES1_0: |
Nishanth Menon | 60475ff | 2014-01-14 10:54:42 -0600 | [diff] [blame] | 838 | case DRA752_ES1_1: |
Nishanth Menon | 4de1668 | 2015-08-13 09:50:58 -0500 | [diff] [blame] | 839 | case DRA752_ES2_0: |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 840 | *prcm = &dra7xx_prcm; |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 841 | *dplls_data = &dra7xx_dplls; |
Lokesh Vutla | f120cef | 2013-02-12 21:29:06 +0000 | [diff] [blame] | 842 | *ctrl = &dra7xx_ctrl; |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 843 | break; |
| 844 | |
Lokesh Vutla | 95d1116 | 2014-05-15 11:08:40 +0530 | [diff] [blame] | 845 | case DRA722_ES1_0: |
Ravi Babu | af9af44 | 2016-03-15 18:09:11 -0500 | [diff] [blame] | 846 | case DRA722_ES2_0: |
Vishal Mahaveer | 42d25eb | 2017-08-26 16:51:22 -0500 | [diff] [blame] | 847 | case DRA722_ES2_1: |
Lokesh Vutla | 95d1116 | 2014-05-15 11:08:40 +0530 | [diff] [blame] | 848 | *prcm = &dra7xx_prcm; |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 849 | *dplls_data = &dra72x_dplls; |
Lokesh Vutla | 95d1116 | 2014-05-15 11:08:40 +0530 | [diff] [blame] | 850 | *ctrl = &dra7xx_ctrl; |
| 851 | break; |
| 852 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 853 | default: |
| 854 | printf("\n INVALID OMAP REVISION "); |
| 855 | } |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 856 | } |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 857 | |
| 858 | void get_ioregs(const struct ctrl_ioregs **regs) |
| 859 | { |
| 860 | u32 omap_rev = omap_revision(); |
| 861 | |
| 862 | switch (omap_rev) { |
| 863 | case OMAP5430_ES1_0: |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 864 | case OMAP5430_ES2_0: |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 865 | *regs = &ioregs_omap5430; |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 866 | break; |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 867 | case OMAP5432_ES1_0: |
| 868 | *regs = &ioregs_omap5432_es1; |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 869 | break; |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 870 | case OMAP5432_ES2_0: |
| 871 | *regs = &ioregs_omap5432_es2; |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 872 | break; |
| 873 | case DRA752_ES1_0: |
Nishanth Menon | 60475ff | 2014-01-14 10:54:42 -0600 | [diff] [blame] | 874 | case DRA752_ES1_1: |
Nishanth Menon | 4de1668 | 2015-08-13 09:50:58 -0500 | [diff] [blame] | 875 | case DRA752_ES2_0: |
Lokesh Vutla | 6f1038f | 2017-08-21 12:50:55 +0530 | [diff] [blame] | 876 | case DRA762_ES1_0: |
Lokesh Vutla | 69483e6 | 2017-12-29 11:47:51 +0530 | [diff] [blame] | 877 | case DRA762_ACD_ES1_0: |
| 878 | case DRA762_ABZ_ES1_0: |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 879 | *regs = &ioregs_dra7xx_es1; |
| 880 | break; |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 881 | case DRA722_ES1_0: |
| 882 | *regs = &ioregs_dra72x_es1; |
| 883 | break; |
Nishanth Menon | 3269997 | 2016-03-15 18:09:12 -0500 | [diff] [blame] | 884 | case DRA722_ES2_0: |
Vishal Mahaveer | 42d25eb | 2017-08-26 16:51:22 -0500 | [diff] [blame] | 885 | case DRA722_ES2_1: |
Nishanth Menon | 3269997 | 2016-03-15 18:09:12 -0500 | [diff] [blame] | 886 | *regs = &ioregs_dra72x_es2; |
| 887 | break; |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 888 | |
| 889 | default: |
| 890 | printf("\n INVALID OMAP REVISION "); |
| 891 | } |
| 892 | } |