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git01.mediatek.com / filogic / uboot / 266b23a57d8e8b860a818e5302c287ef703ecb3a / . / arch / arm / cpu / armv7 / omap5 / hw_data.c
blob: fc9913582480a4f29a941f61afc5f5ee29602c67 [file] [log] [blame]
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]1/*
2 *
3 * HW data initialization for OMAP5
4 *
5 * (C) Copyright 2013
6 * Texas Instruments, <www.ti.com>
7 *
8 * Sricharan R <r.sricharan@ti.com>
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]11 */
12#include <common.h>
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]13#include <palmas.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]14#include <asm/arch/omap.h>
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]15#include <asm/arch/sys_proto.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]16#include <asm/omap_common.h>
Lokesh Vutla61c517f2013-05-30 02:54:32 +0000[diff] [blame]17#include <asm/arch/clock.h>
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]18#include <asm/omap_gpio.h>
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]19#include <asm/io.h>
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]20#include <asm/emif.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]21
22struct prcm_regs const **prcm =
23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]24struct dplls const **dplls_data =
25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]26struct vcores_data const **omap_vcores =
27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
Lokesh Vutla834b6b02013-02-04 04:22:04 +0000[diff] [blame]28struct omap_sys_ctrl_regs const **ctrl =
SRICHARAN R4b1b61c2013-04-24 00:41:22 +0000[diff] [blame]29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]30
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]31/* OPP HIGH FREQUENCY for ES2.0 */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]32static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]40};
41
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]42/* OPP NOM FREQUENCY for ES1.0 */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]43static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
46 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
47 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
48 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]51};
52
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]53/* OPP LOW FREQUENCY for ES1.0 */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]54static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]62};
63
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]64/* OPP LOW FREQUENCY for ES2.0 */
65static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]73};
74
Lokesh Vutlac9e70e22013-12-12 15:36:21 +0530[diff] [blame]75/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]76static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
78 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
79 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
80 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
81 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]84};
85
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]86static const struct dpll_params
87 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
90 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
91 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
92 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
94 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]95};
96
97static const struct dpll_params
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]98 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
99 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
101 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
102 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
103 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
105 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
106};
107
108static const struct dpll_params
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]109 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
110 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
111 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
112 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
113 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
114 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]117};
118
119static const struct dpll_params
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]120 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]128};
129
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]130static const struct dpll_params
131 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
139};
140
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]141static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
144 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
145 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
146 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
148 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
149};
150
151static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
152 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
154 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
155 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
156 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
158 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]159};
160
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]161static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]162 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
Lokesh Vutla087cdb32016-07-25 15:45:44 +0530[diff] [blame]163 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]164 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
165 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
166 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]169};
170
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]171static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]179};
180
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]181static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
182 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
183 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
184 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
185 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
186 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
189};
190
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]191/* ABE M & N values with sys_clk as source */
192static const struct dpll_params
193 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]194 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
196 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
197 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
198 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]201};
202
203/* ABE M & N values with 32K clock as source */
204static const struct dpll_params abe_dpll_params_32k_196608khz = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]206};
207
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]208/* ABE M & N values with sysclk2(22.5792 MHz) as input */
209static const struct dpll_params
210 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
212 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
216 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
217 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
218};
219
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]220static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]221 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]222 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]223 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
224 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
225 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]227 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]228};
229
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]230static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
231 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
232 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
233 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
234 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
235 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
237 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
238};
239
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]240static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
241 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
242 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
243 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
244 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
245 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]246 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]247 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]248};
249
Lokesh Vutlaadc52df2013-07-08 16:04:39 +0530[diff] [blame]250static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
251 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
252 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
253 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
254 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
255 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
256 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
257 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
258};
259
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]260struct dplls omap5_dplls_es1 = {
261 .mpu = mpu_dpll_params_800mhz,
262 .core = core_dpll_params_2128mhz_ddr532,
263 .per = per_dpll_params_768mhz,
264 .iva = iva_dpll_params_2330mhz,
265#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
266 .abe = abe_dpll_params_sysclk_196608khz,
267#else
268 .abe = &abe_dpll_params_32k_196608khz,
269#endif
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]270 .usb = usb_dpll_params_1920mhz,
271 .ddr = NULL
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]272};
273
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]274struct dplls omap5_dplls_es2 = {
Lokesh Vutlac9e70e22013-12-12 15:36:21 +0530[diff] [blame]275 .mpu = mpu_dpll_params_1ghz,
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]276 .core = core_dpll_params_2128mhz_ddr532_es2,
277 .per = per_dpll_params_768mhz_es2,
278 .iva = iva_dpll_params_2330mhz,
279#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
280 .abe = abe_dpll_params_sysclk_196608khz,
281#else
282 .abe = &abe_dpll_params_32k_196608khz,
283#endif
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]284 .usb = usb_dpll_params_1920mhz,
285 .ddr = NULL
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]286};
287
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]288struct dplls dra7xx_dplls = {
289 .mpu = mpu_dpll_params_1ghz,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]290 .core = core_dpll_params_2128mhz_dra7xx,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]291 .per = per_dpll_params_768mhz_dra7xx,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]292 .abe = abe_dpll_params_sysclk2_361267khz,
293 .iva = iva_dpll_params_2330mhz_dra7xx,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]294 .usb = usb_dpll_params_1920mhz,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]295 .ddr = ddr_dpll_params_2128mhz,
Lokesh Vutlaadc52df2013-07-08 16:04:39 +0530[diff] [blame]296 .gmac = gmac_dpll_params_2000mhz,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]297};
298
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]299struct dplls dra72x_dplls = {
300 .mpu = mpu_dpll_params_1ghz,
301 .core = core_dpll_params_2128mhz_dra7xx,
302 .per = per_dpll_params_768mhz_dra7xx,
303 .abe = abe_dpll_params_sysclk2_361267khz,
304 .iva = iva_dpll_params_2330mhz_dra7xx,
305 .usb = usb_dpll_params_1920mhz,
306 .ddr = ddr_dpll_params_2664mhz,
307 .gmac = gmac_dpll_params_2000mhz,
308};
309
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]310struct pmic_data palmas = {
311 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
312 .step = 10000, /* 10 mV represented in uV */
313 /*
314 * Offset codes 1-6 all give the base voltage in Palmas
315 * Offset code 0 switches OFF the SMPS
316 */
317 .start_code = 6,
Lokesh Vutlaae49f6d2013-05-30 02:54:33 +0000[diff] [blame]318 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
319 .pmic_bus_init = sri2c_init,
320 .pmic_write = omap_vc_bypass_send_value,
Lokesh Vutla266b23a2016-08-17 16:25:35 +0530[diff] [blame^]321 .gpio_en = 0,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]322};
323
Lubomir Popov21f34062014-12-19 17:34:31 +0200[diff] [blame]324/* The TPS659038 and TPS65917 are software-compatible, use common struct */
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]325struct pmic_data tps659038 = {
326 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
327 .step = 10000, /* 10 mV represented in uV */
328 /*
329 * Offset codes 1-6 all give the base voltage in Palmas
330 * Offset code 0 switches OFF the SMPS
331 */
332 .start_code = 6,
333 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
334 .pmic_bus_init = gpi2c_init,
335 .pmic_write = palmas_i2c_write_u8,
Lokesh Vutla266b23a2016-08-17 16:25:35 +0530[diff] [blame^]336 .gpio_en = 0,
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]337};
338
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]339struct vcores_data omap5430_volts = {
340 .mpu.value = VDD_MPU,
341 .mpu.addr = SMPS_REG_ADDR_12_MPU,
342 .mpu.pmic = &palmas,
343
344 .core.value = VDD_CORE,
345 .core.addr = SMPS_REG_ADDR_8_CORE,
346 .core.pmic = &palmas,
347
348 .mm.value = VDD_MM,
349 .mm.addr = SMPS_REG_ADDR_45_IVA,
350 .mm.pmic = &palmas,
351};
352
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]353struct vcores_data omap5430_volts_es2 = {
354 .mpu.value = VDD_MPU_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]355 .mpu.addr = SMPS_REG_ADDR_12_MPU,
356 .mpu.pmic = &palmas,
Nishanth Menon1eb62b42016-04-21 14:34:23 -0500[diff] [blame]357 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]358
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]359 .core.value = VDD_CORE_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]360 .core.addr = SMPS_REG_ADDR_8_CORE,
361 .core.pmic = &palmas,
362
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]363 .mm.value = VDD_MM_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]364 .mm.addr = SMPS_REG_ADDR_45_IVA,
365 .mm.pmic = &palmas,
Nishanth Menon07be7572016-04-21 14:34:24 -0500[diff] [blame]366 .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]367};
368
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]369/*
370 * Enable essential clock domains, modules and
371 * do some additional special settings needed
372 */
373void enable_basic_clocks(void)
374{
375 u32 const clk_domains_essential[] = {
376 (*prcm)->cm_l4per_clkstctrl,
377 (*prcm)->cm_l3init_clkstctrl,
378 (*prcm)->cm_memif_clkstctrl,
379 (*prcm)->cm_l4cfg_clkstctrl,
Mugunthan V N4a42ff12013-07-08 16:04:40 +0530[diff] [blame]380#ifdef CONFIG_DRIVER_TI_CPSW
381 (*prcm)->cm_gmac_clkstctrl,
382#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]383 0
384 };
385
386 u32 const clk_modules_hw_auto_essential[] = {
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]387 (*prcm)->cm_l3_gpmc_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]388 (*prcm)->cm_memif_emif_1_clkctrl,
389 (*prcm)->cm_memif_emif_2_clkctrl,
390 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
391 (*prcm)->cm_wkup_gpio1_clkctrl,
392 (*prcm)->cm_l4per_gpio2_clkctrl,
393 (*prcm)->cm_l4per_gpio3_clkctrl,
394 (*prcm)->cm_l4per_gpio4_clkctrl,
395 (*prcm)->cm_l4per_gpio5_clkctrl,
396 (*prcm)->cm_l4per_gpio6_clkctrl,
Axel Lin01a461f2013-06-21 18:54:25 +0800[diff] [blame]397 (*prcm)->cm_l4per_gpio7_clkctrl,
398 (*prcm)->cm_l4per_gpio8_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]399 0
400 };
401
402 u32 const clk_modules_explicit_en_essential[] = {
403 (*prcm)->cm_wkup_gptimer1_clkctrl,
404 (*prcm)->cm_l3init_hsmmc1_clkctrl,
405 (*prcm)->cm_l3init_hsmmc2_clkctrl,
406 (*prcm)->cm_l4per_gptimer2_clkctrl,
407 (*prcm)->cm_wkup_wdtimer2_clkctrl,
408 (*prcm)->cm_l4per_uart3_clkctrl,
409 (*prcm)->cm_l4per_i2c1_clkctrl,
Mugunthan V N4a42ff12013-07-08 16:04:40 +0530[diff] [blame]410#ifdef CONFIG_DRIVER_TI_CPSW
411 (*prcm)->cm_gmac_gmac_clkctrl,
412#endif
Matt Porter30746262013-10-07 15:52:59 +0530[diff] [blame]413
414#ifdef CONFIG_TI_QSPI
415 (*prcm)->cm_l4per_qspi_clkctrl,
416#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]417 0
418 };
419
420 /* Enable optional additional functional clock for GPIO4 */
421 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
422 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
423
424 /* Enable 96 MHz clock for MMC1 & MMC2 */
425 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
426 HSMMC_CLKCTRL_CLKSEL_MASK);
427 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
428 HSMMC_CLKCTRL_CLKSEL_MASK);
429
430 /* Set the correct clock dividers for mmc */
431 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
432 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
433 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
434 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
435
436 /* Select 32KHz clock as the source of GPTIMER1 */
437 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
438 GPTIMER1_CLKCTRL_CLKSEL_MASK);
439
440 do_enable_clocks(clk_domains_essential,
441 clk_modules_hw_auto_essential,
442 clk_modules_explicit_en_essential,
443 1);
444
Matt Porter30746262013-10-07 15:52:59 +0530[diff] [blame]445#ifdef CONFIG_TI_QSPI
446 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
447#endif
448
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]449 /* Enable SCRM OPT clocks for PER and CORE dpll */
450 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
451 OPTFCLKEN_SCRM_PER_MASK);
452 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
453 OPTFCLKEN_SCRM_CORE_MASK);
454}
455
456void enable_basic_uboot_clocks(void)
457{
458 u32 const clk_domains_essential[] = {
Lokesh Vutlab04038f2015-06-05 15:19:21 +0530[diff] [blame]459#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
460 (*prcm)->cm_ipu_clkstctrl,
461#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]462 0
463 };
464
465 u32 const clk_modules_hw_auto_essential[] = {
Lubomir Popov65354032013-04-11 00:08:51 +0000[diff] [blame]466 (*prcm)->cm_l3init_hsusbtll_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]467 0
468 };
469
470 u32 const clk_modules_explicit_en_essential[] = {
471 (*prcm)->cm_l4per_mcspi1_clkctrl,
472 (*prcm)->cm_l4per_i2c2_clkctrl,
473 (*prcm)->cm_l4per_i2c3_clkctrl,
474 (*prcm)->cm_l4per_i2c4_clkctrl,
Lokesh Vutlab04038f2015-06-05 15:19:21 +0530[diff] [blame]475#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
476 (*prcm)->cm_ipu_i2c5_clkctrl,
477#else
Lubomir Popovb36e6092013-04-08 21:49:37 +0000[diff] [blame]478 (*prcm)->cm_l4per_i2c5_clkctrl,
Lokesh Vutlab04038f2015-06-05 15:19:21 +0530[diff] [blame]479#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]480 (*prcm)->cm_l3init_hsusbhost_clkctrl,
481 (*prcm)->cm_l3init_fsusb_clkctrl,
482 0
483 };
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]484 do_enable_clocks(clk_domains_essential,
485 clk_modules_hw_auto_essential,
486 clk_modules_explicit_en_essential,
487 1);
488}
489
Vignesh R92dc6a02015-08-17 13:29:52 +0530[diff] [blame]490#ifdef CONFIG_TI_EDMA3
491void enable_edma3_clocks(void)
492{
493 u32 const clk_domains_edma3[] = {
494 0
495 };
496
497 u32 const clk_modules_hw_auto_edma3[] = {
498 (*prcm)->cm_l3main1_tptc1_clkctrl,
499 (*prcm)->cm_l3main1_tptc2_clkctrl,
500 0
501 };
502
503 u32 const clk_modules_explicit_en_edma3[] = {
504 0
505 };
506
507 do_enable_clocks(clk_domains_edma3,
508 clk_modules_hw_auto_edma3,
509 clk_modules_explicit_en_edma3,
510 1);
511}
512
513void disable_edma3_clocks(void)
514{
515 u32 const clk_domains_edma3[] = {
516 0
517 };
518
519 u32 const clk_modules_disable_edma3[] = {
520 (*prcm)->cm_l3main1_tptc1_clkctrl,
521 (*prcm)->cm_l3main1_tptc2_clkctrl,
522 0
523 };
524
525 do_disable_clocks(clk_domains_edma3,
526 clk_modules_disable_edma3,
527 1);
528}
529#endif
530
Roger Quadros16c97102016-05-23 17:37:47 +0300[diff] [blame]531#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]532void enable_usb_clocks(int index)
533{
534 u32 cm_l3init_usb_otg_ss_clkctrl = 0;
535
536 if (index == 0) {
537 cm_l3init_usb_otg_ss_clkctrl =
538 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
539 /* Enable 960 MHz clock for dwc3 */
540 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
541 OPTFCLKEN_REFCLK960M);
542
Roger Quadrosf1258942016-05-23 17:37:49 +0300[diff] [blame]543 /* Enable 32 KHz clock for USB_PHY1 */
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]544 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
545 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
Roger Quadrosf1258942016-05-23 17:37:49 +0300[diff] [blame]546
547 /* Enable 32 KHz clock for USB_PHY3 */
548 if (is_dra7xx())
549 setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
550 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]551 } else if (index == 1) {
552 cm_l3init_usb_otg_ss_clkctrl =
553 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
554 /* Enable 960 MHz clock for dwc3 */
555 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
556 OPTFCLKEN_REFCLK960M);
557
558 /* Enable 32 KHz clock for dwc3 */
559 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
560 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
561
562 /* Enable 60 MHz clock for USB2PHY2 */
563 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
564 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
565 }
566
567 u32 const clk_domains_usb[] = {
568 0
569 };
570
571 u32 const clk_modules_hw_auto_usb[] = {
572 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
573 cm_l3init_usb_otg_ss_clkctrl,
574 0
575 };
576
577 u32 const clk_modules_explicit_en_usb[] = {
578 0
579 };
580
581 do_enable_clocks(clk_domains_usb,
582 clk_modules_hw_auto_usb,
583 clk_modules_explicit_en_usb,
584 1);
585}
586
587void disable_usb_clocks(int index)
588{
589 u32 cm_l3init_usb_otg_ss_clkctrl = 0;
590
591 if (index == 0) {
592 cm_l3init_usb_otg_ss_clkctrl =
593 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
594 /* Disable 960 MHz clock for dwc3 */
595 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
596 OPTFCLKEN_REFCLK960M);
597
Roger Quadrosf1258942016-05-23 17:37:49 +0300[diff] [blame]598 /* Disable 32 KHz clock for USB_PHY1 */
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]599 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
600 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
Roger Quadrosf1258942016-05-23 17:37:49 +0300[diff] [blame]601
602 /* Disable 32 KHz clock for USB_PHY3 */
603 if (is_dra7xx())
604 clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
605 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]606 } else if (index == 1) {
607 cm_l3init_usb_otg_ss_clkctrl =
608 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
609 /* Disable 960 MHz clock for dwc3 */
610 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
611 OPTFCLKEN_REFCLK960M);
612
613 /* Disable 32 KHz clock for dwc3 */
614 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
615 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
616
617 /* Disable 60 MHz clock for USB2PHY2 */
618 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
619 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
620 }
621
622 u32 const clk_domains_usb[] = {
623 0
624 };
625
626 u32 const clk_modules_disable[] = {
627 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
628 cm_l3init_usb_otg_ss_clkctrl,
629 0
630 };
631
632 do_disable_clocks(clk_domains_usb,
633 clk_modules_disable,
634 1);
635}
636#endif
637
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]638const struct ctrl_ioregs ioregs_omap5430 = {
639 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
640 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
641 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
642 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
643 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
644};
645
646const struct ctrl_ioregs ioregs_omap5432_es1 = {
647 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
648 .ctrl_lpddr2ch = 0x0,
649 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
650 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
651 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
652 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
653 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
SRICHARAN Re02f5f82013-11-08 17:40:37 +0530[diff] [blame]654 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]655};
656
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]657const struct ctrl_ioregs ioregs_omap5432_es2 = {
658 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
659 .ctrl_lpddr2ch = 0x0,
660 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
661 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
662 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
663 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
664 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
SRICHARAN Re02f5f82013-11-08 17:40:37 +0530[diff] [blame]665 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]666};
667
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]668const struct ctrl_ioregs ioregs_dra7xx_es1 = {
669 .ctrl_ddrch = 0x40404040,
670 .ctrl_lpddr2ch = 0x40404040,
671 .ctrl_ddr3ch = 0x80808080,
Lokesh Vutla07fbc332015-06-03 14:43:27 +0530[diff] [blame]672 .ctrl_ddrio_0 = 0x00094A40,
673 .ctrl_ddrio_1 = 0x04A52000,
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]674 .ctrl_ddrio_2 = 0x84210000,
Nishanth Menonf013a3a2015-06-16 08:29:01 -0500[diff] [blame]675 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
676 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]677 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
678};
679
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]680const struct ctrl_ioregs ioregs_dra72x_es1 = {
681 .ctrl_ddrch = 0x40404040,
682 .ctrl_lpddr2ch = 0x40404040,
683 .ctrl_ddr3ch = 0x60606080,
Lokesh Vutla07fbc332015-06-03 14:43:27 +0530[diff] [blame]684 .ctrl_ddrio_0 = 0x00094A40,
685 .ctrl_ddrio_1 = 0x04A52000,
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]686 .ctrl_ddrio_2 = 0x84210000,
Nishanth Menonf013a3a2015-06-16 08:29:01 -0500[diff] [blame]687 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
688 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]689 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
690};
691
Nishanth Menon32699972016-03-15 18:09:12 -0500[diff] [blame]692const struct ctrl_ioregs ioregs_dra72x_es2 = {
693 .ctrl_ddrch = 0x40404040,
694 .ctrl_lpddr2ch = 0x40404040,
695 .ctrl_ddr3ch = 0x60606060,
696 .ctrl_ddrio_0 = 0x00094A40,
697 .ctrl_ddrio_1 = 0x00000000,
698 .ctrl_ddrio_2 = 0x00000000,
699 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
700 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
701 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
702};
703
Felipe Balbi449a4372014-11-06 08:28:48 -0600[diff] [blame]704void __weak hw_data_init(void)
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]705{
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]706 u32 omap_rev = omap_revision();
707
708 switch (omap_rev) {
709
710 case OMAP5430_ES1_0:
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]711 case OMAP5432_ES1_0:
712 *prcm = &omap5_es1_prcm;
713 *dplls_data = &omap5_dplls_es1;
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]714 *omap_vcores = &omap5430_volts;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]715 *ctrl = &omap5_ctrl;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]716 break;
717
SRICHARAN R06ebff42013-02-12 01:33:42 +0000[diff] [blame]718 case OMAP5430_ES2_0:
719 case OMAP5432_ES2_0:
720 *prcm = &omap5_es2_prcm;
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]721 *dplls_data = &omap5_dplls_es2;
722 *omap_vcores = &omap5430_volts_es2;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]723 *ctrl = &omap5_ctrl;
SRICHARAN R06ebff42013-02-12 01:33:42 +0000[diff] [blame]724 break;
725
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]726 case DRA752_ES1_0:
Nishanth Menon60475ff2014-01-14 10:54:42 -0600[diff] [blame]727 case DRA752_ES1_1:
Nishanth Menon4de16682015-08-13 09:50:58 -0500[diff] [blame]728 case DRA752_ES2_0:
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]729 *prcm = &dra7xx_prcm;
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]730 *dplls_data = &dra7xx_dplls;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]731 *ctrl = &dra7xx_ctrl;
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]732 break;
733
Lokesh Vutla95d11162014-05-15 11:08:40 +0530[diff] [blame]734 case DRA722_ES1_0:
Ravi Babuaf9af442016-03-15 18:09:11 -0500[diff] [blame]735 case DRA722_ES2_0:
Lokesh Vutla95d11162014-05-15 11:08:40 +0530[diff] [blame]736 *prcm = &dra7xx_prcm;
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]737 *dplls_data = &dra72x_dplls;
Lokesh Vutla95d11162014-05-15 11:08:40 +0530[diff] [blame]738 *ctrl = &dra7xx_ctrl;
739 break;
740
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]741 default:
742 printf("\n INVALID OMAP REVISION ");
743 }
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]744}
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]745
746void get_ioregs(const struct ctrl_ioregs **regs)
747{
748 u32 omap_rev = omap_revision();
749
750 switch (omap_rev) {
751 case OMAP5430_ES1_0:
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]752 case OMAP5430_ES2_0:
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]753 *regs = &ioregs_omap5430;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]754 break;
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]755 case OMAP5432_ES1_0:
756 *regs = &ioregs_omap5432_es1;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]757 break;
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]758 case OMAP5432_ES2_0:
759 *regs = &ioregs_omap5432_es2;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]760 break;
761 case DRA752_ES1_0:
Nishanth Menon60475ff2014-01-14 10:54:42 -0600[diff] [blame]762 case DRA752_ES1_1:
Nishanth Menon4de16682015-08-13 09:50:58 -0500[diff] [blame]763 case DRA752_ES2_0:
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]764 *regs = &ioregs_dra7xx_es1;
765 break;
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]766 case DRA722_ES1_0:
767 *regs = &ioregs_dra72x_es1;
768 break;
Nishanth Menon32699972016-03-15 18:09:12 -0500[diff] [blame]769 case DRA722_ES2_0:
770 *regs = &ioregs_dra72x_es2;
771 break;
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]772
773 default:
774 printf("\n INVALID OMAP REVISION ");
775 }
776}