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git01.mediatek.com / filogic / uboot / 449a4378467320b7e500cb444c1bc23f04b2e789 / . / arch / arm / cpu / armv7 / omap5 / hw_data.c
blob: 95f16866e6cbd9e043dcdf969a937e648bbd13a8 [file] [log] [blame]
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]1/*
2 *
3 * HW data initialization for OMAP5
4 *
5 * (C) Copyright 2013
6 * Texas Instruments, <www.ti.com>
7 *
8 * Sricharan R <r.sricharan@ti.com>
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]11 */
12#include <common.h>
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]13#include <palmas.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]14#include <asm/arch/omap.h>
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]15#include <asm/arch/sys_proto.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]16#include <asm/omap_common.h>
Lokesh Vutla61c517f2013-05-30 02:54:32 +0000[diff] [blame]17#include <asm/arch/clock.h>
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]18#include <asm/omap_gpio.h>
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]19#include <asm/io.h>
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]20#include <asm/emif.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]21
22struct prcm_regs const **prcm =
23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]24struct dplls const **dplls_data =
25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]26struct vcores_data const **omap_vcores =
27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
Lokesh Vutla834b6b02013-02-04 04:22:04 +0000[diff] [blame]28struct omap_sys_ctrl_regs const **ctrl =
SRICHARAN R4b1b61c2013-04-24 00:41:22 +0000[diff] [blame]29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]30
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]31/* OPP HIGH FREQUENCY for ES2.0 */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]32static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]40};
41
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]42/* OPP NOM FREQUENCY for ES1.0 */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]43static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
46 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
47 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
48 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]51};
52
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]53/* OPP LOW FREQUENCY for ES1.0 */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]54static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]62};
63
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]64/* OPP LOW FREQUENCY for ES2.0 */
65static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]73};
74
Lokesh Vutlac9e70e22013-12-12 15:36:21 +0530[diff] [blame]75/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]76static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
78 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
79 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
80 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
81 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]84};
85
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]86static const struct dpll_params
87 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
90 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
91 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
92 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
94 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]95};
96
97static const struct dpll_params
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]98 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
99 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
101 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
102 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
103 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
105 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
106};
107
108static const struct dpll_params
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]109 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
110 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
111 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
112 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
113 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
114 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]117};
118
119static const struct dpll_params
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]120 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]128};
129
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]130static const struct dpll_params
131 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
139};
140
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]141static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
144 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
145 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
146 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
148 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
149};
150
151static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
152 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
154 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
155 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
156 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
158 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]159};
160
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]161static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]162 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
Poddar, Sourav54243932013-10-07 15:53:00 +0530[diff] [blame]163 {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]164 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
165 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
166 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]169};
170
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]171static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]179};
180
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]181static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
182 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
183 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
184 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
185 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
186 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
189};
190
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]191/* ABE M & N values with sys_clk as source */
192static const struct dpll_params
193 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]194 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
196 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
197 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
198 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]201};
202
203/* ABE M & N values with 32K clock as source */
204static const struct dpll_params abe_dpll_params_32k_196608khz = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]206};
207
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]208/* ABE M & N values with sysclk2(22.5792 MHz) as input */
209static const struct dpll_params
210 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
212 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
216 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
217 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
218};
219
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]220static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]221 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]222 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]223 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
224 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
225 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]227 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]228};
229
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]230static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
231 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
232 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
233 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
234 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
235 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
237 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
238};
239
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]240static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
241 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
242 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
243 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
244 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
245 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]246 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]247 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]248};
249
Lokesh Vutlaadc52df2013-07-08 16:04:39 +0530[diff] [blame]250static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
251 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
252 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
253 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
254 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
255 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
256 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
257 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
258};
259
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]260struct dplls omap5_dplls_es1 = {
261 .mpu = mpu_dpll_params_800mhz,
262 .core = core_dpll_params_2128mhz_ddr532,
263 .per = per_dpll_params_768mhz,
264 .iva = iva_dpll_params_2330mhz,
265#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
266 .abe = abe_dpll_params_sysclk_196608khz,
267#else
268 .abe = &abe_dpll_params_32k_196608khz,
269#endif
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]270 .usb = usb_dpll_params_1920mhz,
271 .ddr = NULL
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]272};
273
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]274struct dplls omap5_dplls_es2 = {
Lokesh Vutlac9e70e22013-12-12 15:36:21 +0530[diff] [blame]275 .mpu = mpu_dpll_params_1ghz,
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]276 .core = core_dpll_params_2128mhz_ddr532_es2,
277 .per = per_dpll_params_768mhz_es2,
278 .iva = iva_dpll_params_2330mhz,
279#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
280 .abe = abe_dpll_params_sysclk_196608khz,
281#else
282 .abe = &abe_dpll_params_32k_196608khz,
283#endif
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]284 .usb = usb_dpll_params_1920mhz,
285 .ddr = NULL
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]286};
287
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]288struct dplls dra7xx_dplls = {
289 .mpu = mpu_dpll_params_1ghz,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]290 .core = core_dpll_params_2128mhz_dra7xx,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]291 .per = per_dpll_params_768mhz_dra7xx,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]292 .abe = abe_dpll_params_sysclk2_361267khz,
293 .iva = iva_dpll_params_2330mhz_dra7xx,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]294 .usb = usb_dpll_params_1920mhz,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]295 .ddr = ddr_dpll_params_2128mhz,
Lokesh Vutlaadc52df2013-07-08 16:04:39 +0530[diff] [blame]296 .gmac = gmac_dpll_params_2000mhz,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]297};
298
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]299struct dplls dra72x_dplls = {
300 .mpu = mpu_dpll_params_1ghz,
301 .core = core_dpll_params_2128mhz_dra7xx,
302 .per = per_dpll_params_768mhz_dra7xx,
303 .abe = abe_dpll_params_sysclk2_361267khz,
304 .iva = iva_dpll_params_2330mhz_dra7xx,
305 .usb = usb_dpll_params_1920mhz,
306 .ddr = ddr_dpll_params_2664mhz,
307 .gmac = gmac_dpll_params_2000mhz,
308};
309
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]310struct pmic_data palmas = {
311 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
312 .step = 10000, /* 10 mV represented in uV */
313 /*
314 * Offset codes 1-6 all give the base voltage in Palmas
315 * Offset code 0 switches OFF the SMPS
316 */
317 .start_code = 6,
Lokesh Vutlaae49f6d2013-05-30 02:54:33 +0000[diff] [blame]318 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
319 .pmic_bus_init = sri2c_init,
320 .pmic_write = omap_vc_bypass_send_value,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]321};
322
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]323struct pmic_data tps659038 = {
324 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
325 .step = 10000, /* 10 mV represented in uV */
326 /*
327 * Offset codes 1-6 all give the base voltage in Palmas
328 * Offset code 0 switches OFF the SMPS
329 */
330 .start_code = 6,
331 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
332 .pmic_bus_init = gpi2c_init,
333 .pmic_write = palmas_i2c_write_u8,
334};
335
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]336struct vcores_data omap5430_volts = {
337 .mpu.value = VDD_MPU,
338 .mpu.addr = SMPS_REG_ADDR_12_MPU,
339 .mpu.pmic = &palmas,
340
341 .core.value = VDD_CORE,
342 .core.addr = SMPS_REG_ADDR_8_CORE,
343 .core.pmic = &palmas,
344
345 .mm.value = VDD_MM,
346 .mm.addr = SMPS_REG_ADDR_45_IVA,
347 .mm.pmic = &palmas,
348};
349
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]350struct vcores_data omap5430_volts_es2 = {
351 .mpu.value = VDD_MPU_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]352 .mpu.addr = SMPS_REG_ADDR_12_MPU,
353 .mpu.pmic = &palmas,
354
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]355 .core.value = VDD_CORE_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]356 .core.addr = SMPS_REG_ADDR_8_CORE,
357 .core.pmic = &palmas,
358
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]359 .mm.value = VDD_MM_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]360 .mm.addr = SMPS_REG_ADDR_45_IVA,
361 .mm.pmic = &palmas,
362};
363
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]364struct vcores_data dra752_volts = {
365 .mpu.value = VDD_MPU_DRA752,
Nishanth Menon93cdb282013-05-30 03:19:31 +0000[diff] [blame]366 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
367 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
Felipe Balbieb446552014-11-06 08:28:43 -0600[diff] [blame]368 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]369 .mpu.pmic = &tps659038,
370
371 .eve.value = VDD_EVE_DRA752,
Nishanth Menon93cdb282013-05-30 03:19:31 +0000[diff] [blame]372 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
373 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
Felipe Balbieb446552014-11-06 08:28:43 -0600[diff] [blame]374 .eve.addr = TPS659038_REG_ADDR_SMPS45,
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]375 .eve.pmic = &tps659038,
376
377 .gpu.value = VDD_GPU_DRA752,
Nishanth Menon93cdb282013-05-30 03:19:31 +0000[diff] [blame]378 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
379 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
Felipe Balbieb446552014-11-06 08:28:43 -0600[diff] [blame]380 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]381 .gpu.pmic = &tps659038,
382
383 .core.value = VDD_CORE_DRA752,
Nishanth Menon93cdb282013-05-30 03:19:31 +0000[diff] [blame]384 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
385 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
Felipe Balbieb446552014-11-06 08:28:43 -0600[diff] [blame]386 .core.addr = TPS659038_REG_ADDR_SMPS7,
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]387 .core.pmic = &tps659038,
388
389 .iva.value = VDD_IVA_DRA752,
Nishanth Menon93cdb282013-05-30 03:19:31 +0000[diff] [blame]390 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
391 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
Felipe Balbieb446552014-11-06 08:28:43 -0600[diff] [blame]392 .iva.addr = TPS659038_REG_ADDR_SMPS8,
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]393 .iva.pmic = &tps659038,
394};
395
Keerthy865242d2014-05-15 11:08:39 +0530[diff] [blame]396struct vcores_data dra722_volts = {
397 .mpu.value = 1000,
398 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
399 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
400 .mpu.addr = 0x23,
401 .mpu.pmic = &tps659038,
402
403 .eve.value = 1000,
404 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
405 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
406 .eve.addr = 0x2f,
407 .eve.pmic = &tps659038,
408
409 .gpu.value = 1000,
410 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
411 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
412 .gpu.addr = 0x2f,
413 .gpu.pmic = &tps659038,
414
415 .core.value = 1000,
416 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
417 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
418 .core.addr = 0x27,
419 .core.pmic = &tps659038,
420
421 .iva.value = 1000,
422 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
423 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
424 .iva.addr = 0x2f,
425 .iva.pmic = &tps659038,
426};
427
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]428/*
429 * Enable essential clock domains, modules and
430 * do some additional special settings needed
431 */
432void enable_basic_clocks(void)
433{
434 u32 const clk_domains_essential[] = {
435 (*prcm)->cm_l4per_clkstctrl,
436 (*prcm)->cm_l3init_clkstctrl,
437 (*prcm)->cm_memif_clkstctrl,
438 (*prcm)->cm_l4cfg_clkstctrl,
Mugunthan V N4a42ff12013-07-08 16:04:40 +0530[diff] [blame]439#ifdef CONFIG_DRIVER_TI_CPSW
440 (*prcm)->cm_gmac_clkstctrl,
441#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]442 0
443 };
444
445 u32 const clk_modules_hw_auto_essential[] = {
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]446 (*prcm)->cm_l3_gpmc_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]447 (*prcm)->cm_memif_emif_1_clkctrl,
448 (*prcm)->cm_memif_emif_2_clkctrl,
449 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
450 (*prcm)->cm_wkup_gpio1_clkctrl,
451 (*prcm)->cm_l4per_gpio2_clkctrl,
452 (*prcm)->cm_l4per_gpio3_clkctrl,
453 (*prcm)->cm_l4per_gpio4_clkctrl,
454 (*prcm)->cm_l4per_gpio5_clkctrl,
455 (*prcm)->cm_l4per_gpio6_clkctrl,
Axel Lin01a461f2013-06-21 18:54:25 +0800[diff] [blame]456 (*prcm)->cm_l4per_gpio7_clkctrl,
457 (*prcm)->cm_l4per_gpio8_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]458 0
459 };
460
461 u32 const clk_modules_explicit_en_essential[] = {
462 (*prcm)->cm_wkup_gptimer1_clkctrl,
463 (*prcm)->cm_l3init_hsmmc1_clkctrl,
464 (*prcm)->cm_l3init_hsmmc2_clkctrl,
465 (*prcm)->cm_l4per_gptimer2_clkctrl,
466 (*prcm)->cm_wkup_wdtimer2_clkctrl,
467 (*prcm)->cm_l4per_uart3_clkctrl,
468 (*prcm)->cm_l4per_i2c1_clkctrl,
Mugunthan V N4a42ff12013-07-08 16:04:40 +0530[diff] [blame]469#ifdef CONFIG_DRIVER_TI_CPSW
470 (*prcm)->cm_gmac_gmac_clkctrl,
471#endif
Matt Porter30746262013-10-07 15:52:59 +0530[diff] [blame]472
473#ifdef CONFIG_TI_QSPI
474 (*prcm)->cm_l4per_qspi_clkctrl,
475#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]476 0
477 };
478
479 /* Enable optional additional functional clock for GPIO4 */
480 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
481 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
482
483 /* Enable 96 MHz clock for MMC1 & MMC2 */
484 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
485 HSMMC_CLKCTRL_CLKSEL_MASK);
486 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
487 HSMMC_CLKCTRL_CLKSEL_MASK);
488
489 /* Set the correct clock dividers for mmc */
490 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
491 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
492 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
493 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
494
495 /* Select 32KHz clock as the source of GPTIMER1 */
496 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
497 GPTIMER1_CLKCTRL_CLKSEL_MASK);
498
499 do_enable_clocks(clk_domains_essential,
500 clk_modules_hw_auto_essential,
501 clk_modules_explicit_en_essential,
502 1);
503
Matt Porter30746262013-10-07 15:52:59 +0530[diff] [blame]504#ifdef CONFIG_TI_QSPI
505 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
506#endif
507
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]508 /* Enable SCRM OPT clocks for PER and CORE dpll */
509 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
510 OPTFCLKEN_SCRM_PER_MASK);
511 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
512 OPTFCLKEN_SCRM_CORE_MASK);
513}
514
515void enable_basic_uboot_clocks(void)
516{
517 u32 const clk_domains_essential[] = {
518 0
519 };
520
521 u32 const clk_modules_hw_auto_essential[] = {
Lubomir Popov65354032013-04-11 00:08:51 +0000[diff] [blame]522 (*prcm)->cm_l3init_hsusbtll_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]523 0
524 };
525
526 u32 const clk_modules_explicit_en_essential[] = {
527 (*prcm)->cm_l4per_mcspi1_clkctrl,
528 (*prcm)->cm_l4per_i2c2_clkctrl,
529 (*prcm)->cm_l4per_i2c3_clkctrl,
530 (*prcm)->cm_l4per_i2c4_clkctrl,
Lubomir Popovb36e6092013-04-08 21:49:37 +0000[diff] [blame]531 (*prcm)->cm_l4per_i2c5_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]532 (*prcm)->cm_l3init_hsusbhost_clkctrl,
533 (*prcm)->cm_l3init_fsusb_clkctrl,
534 0
535 };
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]536 do_enable_clocks(clk_domains_essential,
537 clk_modules_hw_auto_essential,
538 clk_modules_explicit_en_essential,
539 1);
540}
541
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]542const struct ctrl_ioregs ioregs_omap5430 = {
543 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
544 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
545 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
546 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
547 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
548};
549
550const struct ctrl_ioregs ioregs_omap5432_es1 = {
551 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
552 .ctrl_lpddr2ch = 0x0,
553 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
554 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
555 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
556 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
557 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
SRICHARAN Re02f5f82013-11-08 17:40:37 +0530[diff] [blame]558 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]559};
560
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]561const struct ctrl_ioregs ioregs_omap5432_es2 = {
562 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
563 .ctrl_lpddr2ch = 0x0,
564 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
565 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
566 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
567 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
568 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
SRICHARAN Re02f5f82013-11-08 17:40:37 +0530[diff] [blame]569 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]570};
571
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]572const struct ctrl_ioregs ioregs_dra7xx_es1 = {
573 .ctrl_ddrch = 0x40404040,
574 .ctrl_lpddr2ch = 0x40404040,
575 .ctrl_ddr3ch = 0x80808080,
SRICHARAN Re02f5f82013-11-08 17:40:37 +0530[diff] [blame]576 .ctrl_ddrio_0 = 0xA2084210,
577 .ctrl_ddrio_1 = 0x84210840,
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]578 .ctrl_ddrio_2 = 0x84210000,
SRICHARAN Re02f5f82013-11-08 17:40:37 +0530[diff] [blame]579 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
Sricharan R6ff822d2014-07-31 12:05:50 +0530[diff] [blame]580 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]581 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
582};
583
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]584const struct ctrl_ioregs ioregs_dra72x_es1 = {
585 .ctrl_ddrch = 0x40404040,
586 .ctrl_lpddr2ch = 0x40404040,
587 .ctrl_ddr3ch = 0x60606080,
588 .ctrl_ddrio_0 = 0xA2084210,
589 .ctrl_ddrio_1 = 0x84210840,
590 .ctrl_ddrio_2 = 0x84210000,
591 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
592 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
593 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
594};
595
Felipe Balbi449a4372014-11-06 08:28:48 -0600[diff] [blame^]596void __weak hw_data_init(void)
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]597{
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]598 u32 omap_rev = omap_revision();
599
600 switch (omap_rev) {
601
602 case OMAP5430_ES1_0:
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]603 case OMAP5432_ES1_0:
604 *prcm = &omap5_es1_prcm;
605 *dplls_data = &omap5_dplls_es1;
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]606 *omap_vcores = &omap5430_volts;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]607 *ctrl = &omap5_ctrl;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]608 break;
609
SRICHARAN R06ebff42013-02-12 01:33:42 +0000[diff] [blame]610 case OMAP5430_ES2_0:
611 case OMAP5432_ES2_0:
612 *prcm = &omap5_es2_prcm;
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]613 *dplls_data = &omap5_dplls_es2;
614 *omap_vcores = &omap5430_volts_es2;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]615 *ctrl = &omap5_ctrl;
SRICHARAN R06ebff42013-02-12 01:33:42 +0000[diff] [blame]616 break;
617
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]618 case DRA752_ES1_0:
Nishanth Menon60475ff2014-01-14 10:54:42 -0600[diff] [blame]619 case DRA752_ES1_1:
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]620 *prcm = &dra7xx_prcm;
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]621 *dplls_data = &dra7xx_dplls;
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]622 *omap_vcores = &dra752_volts;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]623 *ctrl = &dra7xx_ctrl;
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]624 break;
625
Lokesh Vutla95d11162014-05-15 11:08:40 +0530[diff] [blame]626 case DRA722_ES1_0:
627 *prcm = &dra7xx_prcm;
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]628 *dplls_data = &dra72x_dplls;
Lokesh Vutla95d11162014-05-15 11:08:40 +0530[diff] [blame]629 *omap_vcores = &dra722_volts;
630 *ctrl = &dra7xx_ctrl;
631 break;
632
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]633 default:
634 printf("\n INVALID OMAP REVISION ");
635 }
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]636}
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]637
638void get_ioregs(const struct ctrl_ioregs **regs)
639{
640 u32 omap_rev = omap_revision();
641
642 switch (omap_rev) {
643 case OMAP5430_ES1_0:
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]644 case OMAP5430_ES2_0:
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]645 *regs = &ioregs_omap5430;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]646 break;
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]647 case OMAP5432_ES1_0:
648 *regs = &ioregs_omap5432_es1;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]649 break;
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]650 case OMAP5432_ES2_0:
651 *regs = &ioregs_omap5432_es2;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]652 break;
653 case DRA752_ES1_0:
Nishanth Menon60475ff2014-01-14 10:54:42 -0600[diff] [blame]654 case DRA752_ES1_1:
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]655 *regs = &ioregs_dra7xx_es1;
656 break;
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]657 case DRA722_ES1_0:
658 *regs = &ioregs_dra72x_es1;
659 break;
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]660
661 default:
662 printf("\n INVALID OMAP REVISION ");
663 }
664}