| commit | 5424393723f38a22637f8c4248e897751c72106d | [log] [tgz] |
|---|---|---|
| author | Poddar, Sourav <sourav.poddar@ti.com> | Mon Oct 07 15:53:00 2013 +0530 |
| committer | Jagannadha Sutradharudu Teki <jaganna@xilinx.com> | Mon Oct 07 17:55:51 2013 +0530 |
| tree | 509be84dae9d26378f38db6adc4bf11719ba9d1e | |
| parent | 3074626df2d785276be647f95658dc1f0dbef3f4 [diff] |
armv7: hw_data: change clock divider setting. Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>