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git01.mediatek.com / filogic / uboot / 159a21f5c4073248ba2516f4ec8e04c535bc9696 / . / arch / arm / mach-omap2 / omap5 / hw_data.c
blob: 4ad6b530d29cb7b5ba4073dd9495e7fe8450a401 [file] [log] [blame]
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]1/*
2 *
3 * HW data initialization for OMAP5
4 *
5 * (C) Copyright 2013
6 * Texas Instruments, <www.ti.com>
7 *
8 * Sricharan R <r.sricharan@ti.com>
9 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]11 */
12#include <common.h>
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]13#include <palmas.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]14#include <asm/arch/omap.h>
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]15#include <asm/arch/sys_proto.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]16#include <asm/omap_common.h>
Lokesh Vutla61c517f2013-05-30 02:54:32 +0000[diff] [blame]17#include <asm/arch/clock.h>
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]18#include <asm/omap_gpio.h>
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]19#include <asm/io.h>
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]20#include <asm/emif.h>
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]21
22struct prcm_regs const **prcm =
23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]24struct dplls const **dplls_data =
25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]26struct vcores_data const **omap_vcores =
27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
Lokesh Vutla834b6b02013-02-04 04:22:04 +0000[diff] [blame]28struct omap_sys_ctrl_regs const **ctrl =
SRICHARAN R4b1b61c2013-04-24 00:41:22 +0000[diff] [blame]29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]30
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]31/* OPP NOM FREQUENCY for ES1.0 */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]32static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]33 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
35 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
36 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
37 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
39 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]40};
41
Lokesh Vutlac9e70e22013-12-12 15:36:21 +0530[diff] [blame]42/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]43static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]44 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
45 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
46 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
47 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
48 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]50 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]51};
52
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]53static const struct dpll_params
54 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]55 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
57 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
58 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
59 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
61 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]62};
63
64static const struct dpll_params
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]65 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
66 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
68 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
69 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
70 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
72 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
73};
74
75static const struct dpll_params
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]76 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
77 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
78 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
79 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
80 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
81 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]83 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]84};
85
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]86static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]87 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
88 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
89 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
90 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
91 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
92 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
93 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
94};
95
96static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
97 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
98 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
99 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
100 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
101 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
102 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
103 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]104};
105
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]106static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]107 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
Lokesh Vutla087cdb32016-07-25 15:45:44 +0530[diff] [blame]108 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]109 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
110 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
111 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]112 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutlaff212052013-12-12 15:34:56 +0530[diff] [blame]113 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]114};
115
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]116static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]117 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
118 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
119 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
120 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
121 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
123 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]124};
125
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]126static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
127 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
128 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
129 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
130 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
131 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
132 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
133 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
134};
135
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]136/* ABE M & N values with sys_clk as source */
Lokesh Vutla47ea1682017-01-17 08:52:59 +0530[diff] [blame]137#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]138static const struct dpll_params
139 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]140 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
142 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
143 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
144 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
145 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
146 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]147};
Lokesh Vutla47ea1682017-01-17 08:52:59 +0530[diff] [blame]148#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]149
150/* ABE M & N values with 32K clock as source */
Lokesh Vutla47ea1682017-01-17 08:52:59 +0530[diff] [blame]151#ifndef CONFIG_SYS_OMAP_ABE_SYSCK
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]152static const struct dpll_params abe_dpll_params_32k_196608khz = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]153 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]154};
Lokesh Vutla47ea1682017-01-17 08:52:59 +0530[diff] [blame]155#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]156
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]157/* ABE M & N values with sysclk2(22.5792 MHz) as input */
158static const struct dpll_params
159 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
160 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
161 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
162 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
163 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
164 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
165 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
166 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
167};
168
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]169static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]170 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]171 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]172 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
173 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
174 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
175 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]176 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]177};
178
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]179static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
180 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
181 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
182 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
183 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
184 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
185 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
186 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
187};
188
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]189static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
190 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
191 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
192 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
193 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
194 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]196 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]197};
198
Lokesh Vutlaadc52df2013-07-08 16:04:39 +0530[diff] [blame]199static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
200 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
201 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
202 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
203 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
204 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
205 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
206 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
207};
208
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]209struct dplls omap5_dplls_es1 = {
210 .mpu = mpu_dpll_params_800mhz,
211 .core = core_dpll_params_2128mhz_ddr532,
212 .per = per_dpll_params_768mhz,
213 .iva = iva_dpll_params_2330mhz,
214#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
215 .abe = abe_dpll_params_sysclk_196608khz,
216#else
217 .abe = &abe_dpll_params_32k_196608khz,
218#endif
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]219 .usb = usb_dpll_params_1920mhz,
220 .ddr = NULL
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]221};
222
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]223struct dplls omap5_dplls_es2 = {
Lokesh Vutlac9e70e22013-12-12 15:36:21 +0530[diff] [blame]224 .mpu = mpu_dpll_params_1ghz,
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]225 .core = core_dpll_params_2128mhz_ddr532_es2,
226 .per = per_dpll_params_768mhz_es2,
227 .iva = iva_dpll_params_2330mhz,
228#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
229 .abe = abe_dpll_params_sysclk_196608khz,
230#else
231 .abe = &abe_dpll_params_32k_196608khz,
232#endif
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]233 .usb = usb_dpll_params_1920mhz,
234 .ddr = NULL
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]235};
236
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]237struct dplls dra7xx_dplls = {
238 .mpu = mpu_dpll_params_1ghz,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]239 .core = core_dpll_params_2128mhz_dra7xx,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]240 .per = per_dpll_params_768mhz_dra7xx,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]241 .abe = abe_dpll_params_sysclk2_361267khz,
242 .iva = iva_dpll_params_2330mhz_dra7xx,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]243 .usb = usb_dpll_params_1920mhz,
Lokesh Vutla16523262013-05-30 03:19:38 +0000[diff] [blame]244 .ddr = ddr_dpll_params_2128mhz,
Lokesh Vutlaadc52df2013-07-08 16:04:39 +0530[diff] [blame]245 .gmac = gmac_dpll_params_2000mhz,
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]246};
247
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]248struct dplls dra72x_dplls = {
249 .mpu = mpu_dpll_params_1ghz,
250 .core = core_dpll_params_2128mhz_dra7xx,
251 .per = per_dpll_params_768mhz_dra7xx,
252 .abe = abe_dpll_params_sysclk2_361267khz,
253 .iva = iva_dpll_params_2330mhz_dra7xx,
254 .usb = usb_dpll_params_1920mhz,
255 .ddr = ddr_dpll_params_2664mhz,
256 .gmac = gmac_dpll_params_2000mhz,
257};
258
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]259struct pmic_data palmas = {
260 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
261 .step = 10000, /* 10 mV represented in uV */
262 /*
263 * Offset codes 1-6 all give the base voltage in Palmas
264 * Offset code 0 switches OFF the SMPS
265 */
266 .start_code = 6,
Lokesh Vutlaae49f6d2013-05-30 02:54:33 +0000[diff] [blame]267 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
268 .pmic_bus_init = sri2c_init,
269 .pmic_write = omap_vc_bypass_send_value,
Lokesh Vutla266b23a2016-08-17 16:25:35 +0530[diff] [blame]270 .gpio_en = 0,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]271};
272
Lubomir Popov21f34062014-12-19 17:34:31 +0200[diff] [blame]273/* The TPS659038 and TPS65917 are software-compatible, use common struct */
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]274struct pmic_data tps659038 = {
275 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
276 .step = 10000, /* 10 mV represented in uV */
277 /*
278 * Offset codes 1-6 all give the base voltage in Palmas
279 * Offset code 0 switches OFF the SMPS
280 */
281 .start_code = 6,
282 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
283 .pmic_bus_init = gpi2c_init,
284 .pmic_write = palmas_i2c_write_u8,
Lokesh Vutla266b23a2016-08-17 16:25:35 +0530[diff] [blame]285 .gpio_en = 0,
Lokesh Vutla36852972013-05-30 03:19:29 +0000[diff] [blame]286};
287
Keerthy4d4e34b2016-11-23 13:25:27 +0530[diff] [blame]288/* The LP8732 and LP8733 are software-compatible, use common struct */
289struct pmic_data lp8733 = {
290 .base_offset = LP873X_BUCK_BASE_VOLT_UV,
291 .step = 5000, /* 5 mV represented in uV */
292 /*
293 * Offset codes 0 - 0x13 Invalid.
294 * Offset codes 0x14 0x17 give 10mV steps
295 * Offset codes 0x17 through 0x9D give 5mV steps
296 * So let us start with our operating range from .73V
297 */
298 .start_code = 0x17,
299 .i2c_slave_addr = 0x60,
300 .pmic_bus_init = gpi2c_init,
301 .pmic_write = palmas_i2c_write_u8,
302};
303
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]304struct vcores_data omap5430_volts = {
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530[diff] [blame]305 .mpu.value[OPP_NOM] = VDD_MPU,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]306 .mpu.addr = SMPS_REG_ADDR_12_MPU,
307 .mpu.pmic = &palmas,
308
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530[diff] [blame]309 .core.value[OPP_NOM] = VDD_CORE,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]310 .core.addr = SMPS_REG_ADDR_8_CORE,
311 .core.pmic = &palmas,
312
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530[diff] [blame]313 .mm.value[OPP_NOM] = VDD_MM,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]314 .mm.addr = SMPS_REG_ADDR_45_IVA,
315 .mm.pmic = &palmas,
316};
317
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]318struct vcores_data omap5430_volts_es2 = {
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530[diff] [blame]319 .mpu.value[OPP_NOM] = VDD_MPU_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]320 .mpu.addr = SMPS_REG_ADDR_12_MPU,
321 .mpu.pmic = &palmas,
Nishanth Menon1eb62b42016-04-21 14:34:23 -0500[diff] [blame]322 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]323
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530[diff] [blame]324 .core.value[OPP_NOM] = VDD_CORE_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]325 .core.addr = SMPS_REG_ADDR_8_CORE,
326 .core.pmic = &palmas,
327
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530[diff] [blame]328 .mm.value[OPP_NOM] = VDD_MM_ES2,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]329 .mm.addr = SMPS_REG_ADDR_45_IVA,
330 .mm.pmic = &palmas,
Nishanth Menon07be7572016-04-21 14:34:24 -0500[diff] [blame]331 .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
Nishanth Menon159a21f2017-08-04 21:42:09 -0500[diff] [blame^]332
333 .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN,
334 .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
335
336 .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN,
337 .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
338
339 .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN,
340 .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
SRICHARAN R00d328c2013-02-04 04:22:02 +0000[diff] [blame]341};
342
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]343/*
344 * Enable essential clock domains, modules and
345 * do some additional special settings needed
346 */
347void enable_basic_clocks(void)
348{
349 u32 const clk_domains_essential[] = {
350 (*prcm)->cm_l4per_clkstctrl,
351 (*prcm)->cm_l3init_clkstctrl,
352 (*prcm)->cm_memif_clkstctrl,
353 (*prcm)->cm_l4cfg_clkstctrl,
Mugunthan V N4a42ff12013-07-08 16:04:40 +0530[diff] [blame]354#ifdef CONFIG_DRIVER_TI_CPSW
355 (*prcm)->cm_gmac_clkstctrl,
356#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]357 0
358 };
359
360 u32 const clk_modules_hw_auto_essential[] = {
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]361 (*prcm)->cm_l3_gpmc_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]362 (*prcm)->cm_memif_emif_1_clkctrl,
363 (*prcm)->cm_memif_emif_2_clkctrl,
364 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
365 (*prcm)->cm_wkup_gpio1_clkctrl,
366 (*prcm)->cm_l4per_gpio2_clkctrl,
367 (*prcm)->cm_l4per_gpio3_clkctrl,
368 (*prcm)->cm_l4per_gpio4_clkctrl,
369 (*prcm)->cm_l4per_gpio5_clkctrl,
370 (*prcm)->cm_l4per_gpio6_clkctrl,
Axel Lin01a461f2013-06-21 18:54:25 +0800[diff] [blame]371 (*prcm)->cm_l4per_gpio7_clkctrl,
372 (*prcm)->cm_l4per_gpio8_clkctrl,
Mugunthan V Nd7ced252017-04-07 13:42:00 +0200[diff] [blame]373#ifdef CONFIG_SCSI_AHCI_PLAT
374 (*prcm)->cm_l3init_ocp2scp3_clkctrl,
375#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]376 0
377 };
378
379 u32 const clk_modules_explicit_en_essential[] = {
380 (*prcm)->cm_wkup_gptimer1_clkctrl,
381 (*prcm)->cm_l3init_hsmmc1_clkctrl,
382 (*prcm)->cm_l3init_hsmmc2_clkctrl,
383 (*prcm)->cm_l4per_gptimer2_clkctrl,
384 (*prcm)->cm_wkup_wdtimer2_clkctrl,
385 (*prcm)->cm_l4per_uart3_clkctrl,
386 (*prcm)->cm_l4per_i2c1_clkctrl,
Mugunthan V N4a42ff12013-07-08 16:04:40 +0530[diff] [blame]387#ifdef CONFIG_DRIVER_TI_CPSW
388 (*prcm)->cm_gmac_gmac_clkctrl,
389#endif
Matt Porter30746262013-10-07 15:52:59 +0530[diff] [blame]390
391#ifdef CONFIG_TI_QSPI
392 (*prcm)->cm_l4per_qspi_clkctrl,
393#endif
Mugunthan V Nd7ced252017-04-07 13:42:00 +0200[diff] [blame]394#ifdef CONFIG_SCSI_AHCI_PLAT
395 (*prcm)->cm_l3init_sata_clkctrl,
396#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]397 0
398 };
399
400 /* Enable optional additional functional clock for GPIO4 */
401 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
402 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
403
404 /* Enable 96 MHz clock for MMC1 & MMC2 */
405 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
406 HSMMC_CLKCTRL_CLKSEL_MASK);
407 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
408 HSMMC_CLKCTRL_CLKSEL_MASK);
409
410 /* Set the correct clock dividers for mmc */
411 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
412 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
413 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
414 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
415
416 /* Select 32KHz clock as the source of GPTIMER1 */
417 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
418 GPTIMER1_CLKCTRL_CLKSEL_MASK);
419
420 do_enable_clocks(clk_domains_essential,
421 clk_modules_hw_auto_essential,
422 clk_modules_explicit_en_essential,
423 1);
424
Matt Porter30746262013-10-07 15:52:59 +0530[diff] [blame]425#ifdef CONFIG_TI_QSPI
426 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
427#endif
428
Mugunthan V Nd7ced252017-04-07 13:42:00 +0200[diff] [blame]429#ifdef CONFIG_SCSI_AHCI_PLAT
430 /* Enable optional functional clock for SATA */
431 setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
432 SATA_CLKCTRL_OPTFCLKEN_MASK);
433#endif
434
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]435 /* Enable SCRM OPT clocks for PER and CORE dpll */
436 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
437 OPTFCLKEN_SCRM_PER_MASK);
438 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
439 OPTFCLKEN_SCRM_CORE_MASK);
440}
441
442void enable_basic_uboot_clocks(void)
443{
444 u32 const clk_domains_essential[] = {
Nishanth Menon813fe9d2016-11-29 15:22:00 +0530[diff] [blame]445#if defined(CONFIG_DRA7XX)
Lokesh Vutlab04038f2015-06-05 15:19:21 +0530[diff] [blame]446 (*prcm)->cm_ipu_clkstctrl,
447#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]448 0
449 };
450
451 u32 const clk_modules_hw_auto_essential[] = {
Lubomir Popov65354032013-04-11 00:08:51 +0000[diff] [blame]452 (*prcm)->cm_l3init_hsusbtll_clkctrl,
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]453 0
454 };
455
456 u32 const clk_modules_explicit_en_essential[] = {
457 (*prcm)->cm_l4per_mcspi1_clkctrl,
458 (*prcm)->cm_l4per_i2c2_clkctrl,
459 (*prcm)->cm_l4per_i2c3_clkctrl,
460 (*prcm)->cm_l4per_i2c4_clkctrl,
Nishanth Menon813fe9d2016-11-29 15:22:00 +0530[diff] [blame]461#if defined(CONFIG_DRA7XX)
Lokesh Vutlab04038f2015-06-05 15:19:21 +0530[diff] [blame]462 (*prcm)->cm_ipu_i2c5_clkctrl,
463#else
Lubomir Popovb36e6092013-04-08 21:49:37 +0000[diff] [blame]464 (*prcm)->cm_l4per_i2c5_clkctrl,
Lokesh Vutlab04038f2015-06-05 15:19:21 +0530[diff] [blame]465#endif
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]466 (*prcm)->cm_l3init_hsusbhost_clkctrl,
467 (*prcm)->cm_l3init_fsusb_clkctrl,
468 0
469 };
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]470 do_enable_clocks(clk_domains_essential,
471 clk_modules_hw_auto_essential,
472 clk_modules_explicit_en_essential,
473 1);
474}
475
Vignesh R92dc6a02015-08-17 13:29:52 +0530[diff] [blame]476#ifdef CONFIG_TI_EDMA3
477void enable_edma3_clocks(void)
478{
479 u32 const clk_domains_edma3[] = {
480 0
481 };
482
483 u32 const clk_modules_hw_auto_edma3[] = {
484 (*prcm)->cm_l3main1_tptc1_clkctrl,
485 (*prcm)->cm_l3main1_tptc2_clkctrl,
486 0
487 };
488
489 u32 const clk_modules_explicit_en_edma3[] = {
490 0
491 };
492
493 do_enable_clocks(clk_domains_edma3,
494 clk_modules_hw_auto_edma3,
495 clk_modules_explicit_en_edma3,
496 1);
497}
498
499void disable_edma3_clocks(void)
500{
501 u32 const clk_domains_edma3[] = {
502 0
503 };
504
505 u32 const clk_modules_disable_edma3[] = {
506 (*prcm)->cm_l3main1_tptc1_clkctrl,
507 (*prcm)->cm_l3main1_tptc2_clkctrl,
508 0
509 };
510
511 do_disable_clocks(clk_domains_edma3,
512 clk_modules_disable_edma3,
513 1);
514}
515#endif
516
Roger Quadros16c97102016-05-23 17:37:47 +0300[diff] [blame]517#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]518void enable_usb_clocks(int index)
519{
520 u32 cm_l3init_usb_otg_ss_clkctrl = 0;
521
522 if (index == 0) {
523 cm_l3init_usb_otg_ss_clkctrl =
524 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
525 /* Enable 960 MHz clock for dwc3 */
526 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
527 OPTFCLKEN_REFCLK960M);
528
Roger Quadrosf1258942016-05-23 17:37:49 +0300[diff] [blame]529 /* Enable 32 KHz clock for USB_PHY1 */
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]530 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
531 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
Roger Quadrosf1258942016-05-23 17:37:49 +0300[diff] [blame]532
533 /* Enable 32 KHz clock for USB_PHY3 */
534 if (is_dra7xx())
535 setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
536 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]537 } else if (index == 1) {
538 cm_l3init_usb_otg_ss_clkctrl =
539 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
540 /* Enable 960 MHz clock for dwc3 */
541 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
542 OPTFCLKEN_REFCLK960M);
543
544 /* Enable 32 KHz clock for dwc3 */
545 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
546 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
547
548 /* Enable 60 MHz clock for USB2PHY2 */
549 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
550 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
551 }
552
553 u32 const clk_domains_usb[] = {
554 0
555 };
556
557 u32 const clk_modules_hw_auto_usb[] = {
558 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
559 cm_l3init_usb_otg_ss_clkctrl,
560 0
561 };
562
563 u32 const clk_modules_explicit_en_usb[] = {
564 0
565 };
566
567 do_enable_clocks(clk_domains_usb,
568 clk_modules_hw_auto_usb,
569 clk_modules_explicit_en_usb,
570 1);
571}
572
573void disable_usb_clocks(int index)
574{
575 u32 cm_l3init_usb_otg_ss_clkctrl = 0;
576
577 if (index == 0) {
578 cm_l3init_usb_otg_ss_clkctrl =
579 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
580 /* Disable 960 MHz clock for dwc3 */
581 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
582 OPTFCLKEN_REFCLK960M);
583
Roger Quadrosf1258942016-05-23 17:37:49 +0300[diff] [blame]584 /* Disable 32 KHz clock for USB_PHY1 */
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]585 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
586 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
Roger Quadrosf1258942016-05-23 17:37:49 +0300[diff] [blame]587
588 /* Disable 32 KHz clock for USB_PHY3 */
589 if (is_dra7xx())
590 clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
591 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
Kishon Vijay Abraham If54117d2015-08-19 16:16:25 +0530[diff] [blame]592 } else if (index == 1) {
593 cm_l3init_usb_otg_ss_clkctrl =
594 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
595 /* Disable 960 MHz clock for dwc3 */
596 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
597 OPTFCLKEN_REFCLK960M);
598
599 /* Disable 32 KHz clock for dwc3 */
600 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
601 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
602
603 /* Disable 60 MHz clock for USB2PHY2 */
604 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
605 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
606 }
607
608 u32 const clk_domains_usb[] = {
609 0
610 };
611
612 u32 const clk_modules_disable[] = {
613 (*prcm)->cm_l3init_ocp2scp1_clkctrl,
614 cm_l3init_usb_otg_ss_clkctrl,
615 0
616 };
617
618 do_disable_clocks(clk_domains_usb,
619 clk_modules_disable,
620 1);
621}
622#endif
623
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]624const struct ctrl_ioregs ioregs_omap5430 = {
625 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
626 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
627 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
628 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
629 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
630};
631
632const struct ctrl_ioregs ioregs_omap5432_es1 = {
633 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
634 .ctrl_lpddr2ch = 0x0,
635 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
636 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
637 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
638 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
639 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
SRICHARAN Re02f5f82013-11-08 17:40:37 +0530[diff] [blame]640 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]641};
642
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]643const struct ctrl_ioregs ioregs_omap5432_es2 = {
644 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
645 .ctrl_lpddr2ch = 0x0,
646 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
647 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
648 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
649 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
650 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
SRICHARAN Re02f5f82013-11-08 17:40:37 +0530[diff] [blame]651 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]652};
653
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]654const struct ctrl_ioregs ioregs_dra7xx_es1 = {
655 .ctrl_ddrch = 0x40404040,
656 .ctrl_lpddr2ch = 0x40404040,
657 .ctrl_ddr3ch = 0x80808080,
Lokesh Vutla07fbc332015-06-03 14:43:27 +0530[diff] [blame]658 .ctrl_ddrio_0 = 0x00094A40,
659 .ctrl_ddrio_1 = 0x04A52000,
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]660 .ctrl_ddrio_2 = 0x84210000,
Nishanth Menonf013a3a2015-06-16 08:29:01 -0500[diff] [blame]661 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
662 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]663 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
664};
665
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]666const struct ctrl_ioregs ioregs_dra72x_es1 = {
667 .ctrl_ddrch = 0x40404040,
668 .ctrl_lpddr2ch = 0x40404040,
669 .ctrl_ddr3ch = 0x60606080,
Lokesh Vutla07fbc332015-06-03 14:43:27 +0530[diff] [blame]670 .ctrl_ddrio_0 = 0x00094A40,
671 .ctrl_ddrio_1 = 0x04A52000,
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]672 .ctrl_ddrio_2 = 0x84210000,
Nishanth Menonf013a3a2015-06-16 08:29:01 -0500[diff] [blame]673 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
674 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]675 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
676};
677
Nishanth Menon32699972016-03-15 18:09:12 -0500[diff] [blame]678const struct ctrl_ioregs ioregs_dra72x_es2 = {
679 .ctrl_ddrch = 0x40404040,
680 .ctrl_lpddr2ch = 0x40404040,
681 .ctrl_ddr3ch = 0x60606060,
682 .ctrl_ddrio_0 = 0x00094A40,
683 .ctrl_ddrio_1 = 0x00000000,
684 .ctrl_ddrio_2 = 0x00000000,
685 .ctrl_emif_sdram_config_ext = 0x0001C1A7,
686 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
687 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
688};
689
Felipe Balbi449a4372014-11-06 08:28:48 -0600[diff] [blame]690void __weak hw_data_init(void)
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]691{
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]692 u32 omap_rev = omap_revision();
693
694 switch (omap_rev) {
695
696 case OMAP5430_ES1_0:
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]697 case OMAP5432_ES1_0:
698 *prcm = &omap5_es1_prcm;
699 *dplls_data = &omap5_dplls_es1;
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]700 *omap_vcores = &omap5430_volts;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]701 *ctrl = &omap5_ctrl;
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]702 break;
703
SRICHARAN R06ebff42013-02-12 01:33:42 +0000[diff] [blame]704 case OMAP5430_ES2_0:
705 case OMAP5432_ES2_0:
706 *prcm = &omap5_es2_prcm;
SRICHARAN Ra04ed142013-02-12 01:33:43 +0000[diff] [blame]707 *dplls_data = &omap5_dplls_es2;
708 *omap_vcores = &omap5430_volts_es2;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]709 *ctrl = &omap5_ctrl;
SRICHARAN R06ebff42013-02-12 01:33:42 +0000[diff] [blame]710 break;
711
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]712 case DRA752_ES1_0:
Nishanth Menon60475ff2014-01-14 10:54:42 -0600[diff] [blame]713 case DRA752_ES1_1:
Nishanth Menon4de16682015-08-13 09:50:58 -0500[diff] [blame]714 case DRA752_ES2_0:
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]715 *prcm = &dra7xx_prcm;
Lokesh Vutla5e70e292013-02-12 21:29:05 +0000[diff] [blame]716 *dplls_data = &dra7xx_dplls;
Lokesh Vutlaf120cef2013-02-12 21:29:06 +0000[diff] [blame]717 *ctrl = &dra7xx_ctrl;
Lokesh Vutla15c2c702013-02-17 23:33:37 +0000[diff] [blame]718 break;
719
Lokesh Vutla95d11162014-05-15 11:08:40 +0530[diff] [blame]720 case DRA722_ES1_0:
Ravi Babuaf9af442016-03-15 18:09:11 -0500[diff] [blame]721 case DRA722_ES2_0:
Lokesh Vutla95d11162014-05-15 11:08:40 +0530[diff] [blame]722 *prcm = &dra7xx_prcm;
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]723 *dplls_data = &dra72x_dplls;
Lokesh Vutla95d11162014-05-15 11:08:40 +0530[diff] [blame]724 *ctrl = &dra7xx_ctrl;
725 break;
726
SRICHARAN R1a79cab2013-02-04 04:22:01 +0000[diff] [blame]727 default:
728 printf("\n INVALID OMAP REVISION ");
729 }
SRICHARAN Rfb6aa1f2013-02-04 04:22:00 +0000[diff] [blame]730}
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]731
732void get_ioregs(const struct ctrl_ioregs **regs)
733{
734 u32 omap_rev = omap_revision();
735
736 switch (omap_rev) {
737 case OMAP5430_ES1_0:
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]738 case OMAP5430_ES2_0:
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]739 *regs = &ioregs_omap5430;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]740 break;
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]741 case OMAP5432_ES1_0:
742 *regs = &ioregs_omap5432_es1;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]743 break;
Lokesh Vutla79a9ec72013-02-12 01:33:44 +0000[diff] [blame]744 case OMAP5432_ES2_0:
745 *regs = &ioregs_omap5432_es2;
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]746 break;
747 case DRA752_ES1_0:
Nishanth Menon60475ff2014-01-14 10:54:42 -0600[diff] [blame]748 case DRA752_ES1_1:
Nishanth Menon4de16682015-08-13 09:50:58 -0500[diff] [blame]749 case DRA752_ES2_0:
Sricharan Rffa98182013-05-30 03:19:39 +0000[diff] [blame]750 *regs = &ioregs_dra7xx_es1;
751 break;
R Sricharan5a9d4d12014-08-28 12:01:04 +0530[diff] [blame]752 case DRA722_ES1_0:
753 *regs = &ioregs_dra72x_es1;
754 break;
Nishanth Menon32699972016-03-15 18:09:12 -0500[diff] [blame]755 case DRA722_ES2_0:
756 *regs = &ioregs_dra72x_es2;
757 break;
Lokesh Vutlad8ac0502013-02-04 04:22:05 +0000[diff] [blame]758
759 default:
760 printf("\n INVALID OMAP REVISION ");
761 }
762}