commit d7ced256dd4c982bc10d7e3c832e8347d4f6cc1b
author Mugunthan V N <mugunthanvnm@ti.com> Fri Apr 07 13:42:00 2017 +0200
committer Simon Glass <sjg@chromium.org> Fri Apr 14 19:38:57 2017 -0600
tree f0eba8cdb29569344f03edf18156c26e0969b3a3
parent f399f6e62830e78dc3616c2cdf38eee590f9c1bb

arm: omap: sata: move enable sata clocks to enable_basic_clocks()

All the clocks which has to be enabled has to be done in
enable_basic_clocks(), so moving enable sata clock to common
clocks enable function.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

arch/arm/mach-omap2/omap5/hw_data.c

diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index 5d956b5..a8a6b8a 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -361,6 +361,9 @@
 		(*prcm)->cm_l4per_gpio6_clkctrl,
 		(*prcm)->cm_l4per_gpio7_clkctrl,
 		(*prcm)->cm_l4per_gpio8_clkctrl,
+#ifdef CONFIG_SCSI_AHCI_PLAT
+		(*prcm)->cm_l3init_ocp2scp3_clkctrl,
+#endif
 		0
 	};
 
@@ -379,6 +382,9 @@
 #ifdef CONFIG_TI_QSPI
 		(*prcm)->cm_l4per_qspi_clkctrl,
 #endif
+#ifdef CONFIG_SCSI_AHCI_PLAT
+		(*prcm)->cm_l3init_sata_clkctrl,
+#endif
 		0
 	};
 
@@ -411,6 +417,12 @@
 	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
 #endif
 
+#ifdef CONFIG_SCSI_AHCI_PLAT
+	/* Enable optional functional clock for SATA */
+	setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+		     SATA_CLKCTRL_OPTFCLKEN_MASK);
+#endif
+
 	/* Enable SCRM OPT clocks for PER and CORE dpll */
 	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
 			OPTFCLKEN_SCRM_PER_MASK);