SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * HW data initialization for OMAP5 |
| 4 | * |
| 5 | * (C) Copyright 2013 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Sricharan R <r.sricharan@ti.com> |
| 9 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 11 | */ |
| 12 | #include <common.h> |
Lokesh Vutla | 3685297 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 13 | #include <palmas.h> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 14 | #include <asm/arch/omap.h> |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 15 | #include <asm/arch/sys_proto.h> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 16 | #include <asm/omap_common.h> |
Lokesh Vutla | 61c517f | 2013-05-30 02:54:32 +0000 | [diff] [blame] | 17 | #include <asm/arch/clock.h> |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 18 | #include <asm/omap_gpio.h> |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 19 | #include <asm/io.h> |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 20 | #include <asm/emif.h> |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 21 | |
| 22 | struct prcm_regs const **prcm = |
| 23 | (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 24 | struct dplls const **dplls_data = |
| 25 | (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 26 | struct vcores_data const **omap_vcores = |
| 27 | (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; |
Lokesh Vutla | 834b6b0 | 2013-02-04 04:22:04 +0000 | [diff] [blame] | 28 | struct omap_sys_ctrl_regs const **ctrl = |
SRICHARAN R | 4b1b61c | 2013-04-24 00:41:22 +0000 | [diff] [blame] | 29 | (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 30 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 31 | /* OPP NOM FREQUENCY for ES1.0 */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 32 | static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 33 | {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 34 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 35 | {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 36 | {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 37 | {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 38 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 39 | {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 40 | }; |
| 41 | |
Lokesh Vutla | c9e70e2 | 2013-12-12 15:36:21 +0530 | [diff] [blame] | 42 | /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 43 | static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 44 | {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 45 | {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 46 | {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 47 | {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 48 | {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 49 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 50 | {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 51 | }; |
| 52 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 53 | static const struct dpll_params |
| 54 | core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 55 | {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ |
| 56 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 57 | {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ |
| 58 | {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ |
| 59 | {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ |
| 60 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 61 | {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 62 | }; |
| 63 | |
| 64 | static const struct dpll_params |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 65 | core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { |
| 66 | {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ |
| 67 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 68 | {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ |
| 69 | {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ |
| 70 | {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ |
| 71 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 72 | {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ |
| 73 | }; |
| 74 | |
| 75 | static const struct dpll_params |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 76 | core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { |
| 77 | {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ |
| 78 | {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ |
| 79 | {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ |
| 80 | {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ |
| 81 | {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 82 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 83 | {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 84 | }; |
| 85 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 86 | static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 87 | {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ |
| 88 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 89 | {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 90 | {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 91 | {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ |
| 92 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 93 | {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ |
| 94 | }; |
| 95 | |
| 96 | static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { |
| 97 | {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ |
| 98 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 99 | {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 100 | {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 101 | {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ |
| 102 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 103 | {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 104 | }; |
| 105 | |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 106 | static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { |
Lokesh Vutla | ff21205 | 2013-12-12 15:34:56 +0530 | [diff] [blame] | 107 | {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ |
Lokesh Vutla | 087cdb3 | 2016-07-25 15:45:44 +0530 | [diff] [blame] | 108 | {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ |
Lokesh Vutla | ff21205 | 2013-12-12 15:34:56 +0530 | [diff] [blame] | 109 | {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 110 | {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 111 | {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 112 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | ff21205 | 2013-12-12 15:34:56 +0530 | [diff] [blame] | 113 | {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 114 | }; |
| 115 | |
Praneeth Bajjuri | 9b21ff4 | 2017-08-21 12:50:52 +0530 | [diff] [blame^] | 116 | static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = { |
| 117 | {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */ |
| 118 | {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */ |
| 119 | {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 120 | {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 121 | {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */ |
| 122 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 123 | {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 124 | }; |
| 125 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 126 | static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 127 | {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 128 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 129 | {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 130 | {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 131 | {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 132 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 133 | {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 134 | }; |
| 135 | |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 136 | static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { |
| 137 | {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 138 | {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 139 | {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 140 | {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 141 | {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 142 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 143 | {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 144 | }; |
| 145 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 146 | /* ABE M & N values with sys_clk as source */ |
Lokesh Vutla | 47ea168 | 2017-01-17 08:52:59 +0530 | [diff] [blame] | 147 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 148 | static const struct dpll_params |
| 149 | abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 150 | {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 151 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ |
| 152 | {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 153 | {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 154 | {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 155 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 156 | {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 157 | }; |
Lokesh Vutla | 47ea168 | 2017-01-17 08:52:59 +0530 | [diff] [blame] | 158 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 159 | |
| 160 | /* ABE M & N values with 32K clock as source */ |
Lokesh Vutla | 47ea168 | 2017-01-17 08:52:59 +0530 | [diff] [blame] | 161 | #ifndef CONFIG_SYS_OMAP_ABE_SYSCK |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 162 | static const struct dpll_params abe_dpll_params_32k_196608khz = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 163 | 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 164 | }; |
Lokesh Vutla | 47ea168 | 2017-01-17 08:52:59 +0530 | [diff] [blame] | 165 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 166 | |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 167 | /* ABE M & N values with sysclk2(22.5792 MHz) as input */ |
| 168 | static const struct dpll_params |
| 169 | abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { |
| 170 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 171 | {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 172 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 173 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 174 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 175 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 176 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 177 | }; |
| 178 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 179 | static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 180 | {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 181 | {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 182 | {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 183 | {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 184 | {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 185 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 186 | {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 187 | }; |
| 188 | |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 189 | static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { |
| 190 | {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 191 | {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 192 | {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 193 | {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 194 | {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 195 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 196 | {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 197 | }; |
| 198 | |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 199 | static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { |
| 200 | {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 201 | {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 202 | {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 203 | {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 204 | {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 205 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 206 | {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 207 | }; |
| 208 | |
Lokesh Vutla | adc52df | 2013-07-08 16:04:39 +0530 | [diff] [blame] | 209 | static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { |
| 210 | {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ |
| 211 | {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ |
| 212 | {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ |
| 213 | {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 214 | {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ |
| 215 | {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ |
| 216 | {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ |
| 217 | }; |
| 218 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 219 | struct dplls omap5_dplls_es1 = { |
| 220 | .mpu = mpu_dpll_params_800mhz, |
| 221 | .core = core_dpll_params_2128mhz_ddr532, |
| 222 | .per = per_dpll_params_768mhz, |
| 223 | .iva = iva_dpll_params_2330mhz, |
| 224 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 225 | .abe = abe_dpll_params_sysclk_196608khz, |
| 226 | #else |
| 227 | .abe = &abe_dpll_params_32k_196608khz, |
| 228 | #endif |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 229 | .usb = usb_dpll_params_1920mhz, |
| 230 | .ddr = NULL |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 231 | }; |
| 232 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 233 | struct dplls omap5_dplls_es2 = { |
Lokesh Vutla | c9e70e2 | 2013-12-12 15:36:21 +0530 | [diff] [blame] | 234 | .mpu = mpu_dpll_params_1ghz, |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 235 | .core = core_dpll_params_2128mhz_ddr532_es2, |
| 236 | .per = per_dpll_params_768mhz_es2, |
| 237 | .iva = iva_dpll_params_2330mhz, |
| 238 | #ifdef CONFIG_SYS_OMAP_ABE_SYSCK |
| 239 | .abe = abe_dpll_params_sysclk_196608khz, |
| 240 | #else |
| 241 | .abe = &abe_dpll_params_32k_196608khz, |
| 242 | #endif |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 243 | .usb = usb_dpll_params_1920mhz, |
| 244 | .ddr = NULL |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 245 | }; |
| 246 | |
Praneeth Bajjuri | 9b21ff4 | 2017-08-21 12:50:52 +0530 | [diff] [blame^] | 247 | struct dplls dra76x_dplls = { |
| 248 | .mpu = mpu_dpll_params_1ghz, |
| 249 | .core = core_dpll_params_2128mhz_dra7xx, |
| 250 | .per = per_dpll_params_768mhz_dra76x, |
| 251 | .abe = abe_dpll_params_sysclk2_361267khz, |
| 252 | .iva = iva_dpll_params_2330mhz_dra7xx, |
| 253 | .usb = usb_dpll_params_1920mhz, |
| 254 | .ddr = ddr_dpll_params_2664mhz, |
| 255 | .gmac = gmac_dpll_params_2000mhz, |
| 256 | }; |
| 257 | |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 258 | struct dplls dra7xx_dplls = { |
| 259 | .mpu = mpu_dpll_params_1ghz, |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 260 | .core = core_dpll_params_2128mhz_dra7xx, |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 261 | .per = per_dpll_params_768mhz_dra7xx, |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 262 | .abe = abe_dpll_params_sysclk2_361267khz, |
| 263 | .iva = iva_dpll_params_2330mhz_dra7xx, |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 264 | .usb = usb_dpll_params_1920mhz, |
Lokesh Vutla | 1652326 | 2013-05-30 03:19:38 +0000 | [diff] [blame] | 265 | .ddr = ddr_dpll_params_2128mhz, |
Lokesh Vutla | adc52df | 2013-07-08 16:04:39 +0530 | [diff] [blame] | 266 | .gmac = gmac_dpll_params_2000mhz, |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 267 | }; |
| 268 | |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 269 | struct dplls dra72x_dplls = { |
| 270 | .mpu = mpu_dpll_params_1ghz, |
| 271 | .core = core_dpll_params_2128mhz_dra7xx, |
| 272 | .per = per_dpll_params_768mhz_dra7xx, |
| 273 | .abe = abe_dpll_params_sysclk2_361267khz, |
| 274 | .iva = iva_dpll_params_2330mhz_dra7xx, |
| 275 | .usb = usb_dpll_params_1920mhz, |
| 276 | .ddr = ddr_dpll_params_2664mhz, |
| 277 | .gmac = gmac_dpll_params_2000mhz, |
| 278 | }; |
| 279 | |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 280 | struct pmic_data palmas = { |
| 281 | .base_offset = PALMAS_SMPS_BASE_VOLT_UV, |
| 282 | .step = 10000, /* 10 mV represented in uV */ |
| 283 | /* |
| 284 | * Offset codes 1-6 all give the base voltage in Palmas |
| 285 | * Offset code 0 switches OFF the SMPS |
| 286 | */ |
| 287 | .start_code = 6, |
Lokesh Vutla | ae49f6d | 2013-05-30 02:54:33 +0000 | [diff] [blame] | 288 | .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, |
| 289 | .pmic_bus_init = sri2c_init, |
| 290 | .pmic_write = omap_vc_bypass_send_value, |
Lokesh Vutla | 266b23a | 2016-08-17 16:25:35 +0530 | [diff] [blame] | 291 | .gpio_en = 0, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 292 | }; |
| 293 | |
Lubomir Popov | 21f3406 | 2014-12-19 17:34:31 +0200 | [diff] [blame] | 294 | /* The TPS659038 and TPS65917 are software-compatible, use common struct */ |
Lokesh Vutla | 3685297 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 295 | struct pmic_data tps659038 = { |
| 296 | .base_offset = PALMAS_SMPS_BASE_VOLT_UV, |
| 297 | .step = 10000, /* 10 mV represented in uV */ |
| 298 | /* |
| 299 | * Offset codes 1-6 all give the base voltage in Palmas |
| 300 | * Offset code 0 switches OFF the SMPS |
| 301 | */ |
| 302 | .start_code = 6, |
| 303 | .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, |
| 304 | .pmic_bus_init = gpi2c_init, |
| 305 | .pmic_write = palmas_i2c_write_u8, |
Lokesh Vutla | 266b23a | 2016-08-17 16:25:35 +0530 | [diff] [blame] | 306 | .gpio_en = 0, |
Lokesh Vutla | 3685297 | 2013-05-30 03:19:29 +0000 | [diff] [blame] | 307 | }; |
| 308 | |
Keerthy | 4d4e34b | 2016-11-23 13:25:27 +0530 | [diff] [blame] | 309 | /* The LP8732 and LP8733 are software-compatible, use common struct */ |
| 310 | struct pmic_data lp8733 = { |
| 311 | .base_offset = LP873X_BUCK_BASE_VOLT_UV, |
| 312 | .step = 5000, /* 5 mV represented in uV */ |
| 313 | /* |
| 314 | * Offset codes 0 - 0x13 Invalid. |
| 315 | * Offset codes 0x14 0x17 give 10mV steps |
| 316 | * Offset codes 0x17 through 0x9D give 5mV steps |
| 317 | * So let us start with our operating range from .73V |
| 318 | */ |
| 319 | .start_code = 0x17, |
| 320 | .i2c_slave_addr = 0x60, |
| 321 | .pmic_bus_init = gpi2c_init, |
| 322 | .pmic_write = palmas_i2c_write_u8, |
| 323 | }; |
| 324 | |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 325 | struct vcores_data omap5430_volts = { |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 326 | .mpu.value[OPP_NOM] = VDD_MPU, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 327 | .mpu.addr = SMPS_REG_ADDR_12_MPU, |
| 328 | .mpu.pmic = &palmas, |
| 329 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 330 | .core.value[OPP_NOM] = VDD_CORE, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 331 | .core.addr = SMPS_REG_ADDR_8_CORE, |
| 332 | .core.pmic = &palmas, |
| 333 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 334 | .mm.value[OPP_NOM] = VDD_MM, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 335 | .mm.addr = SMPS_REG_ADDR_45_IVA, |
| 336 | .mm.pmic = &palmas, |
| 337 | }; |
| 338 | |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 339 | struct vcores_data omap5430_volts_es2 = { |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 340 | .mpu.value[OPP_NOM] = VDD_MPU_ES2, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 341 | .mpu.addr = SMPS_REG_ADDR_12_MPU, |
| 342 | .mpu.pmic = &palmas, |
Nishanth Menon | 1eb62b4 | 2016-04-21 14:34:23 -0500 | [diff] [blame] | 343 | .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 344 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 345 | .core.value[OPP_NOM] = VDD_CORE_ES2, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 346 | .core.addr = SMPS_REG_ADDR_8_CORE, |
| 347 | .core.pmic = &palmas, |
| 348 | |
Lokesh Vutla | 6ede0fd | 2016-11-23 12:54:39 +0530 | [diff] [blame] | 349 | .mm.value[OPP_NOM] = VDD_MM_ES2, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 350 | .mm.addr = SMPS_REG_ADDR_45_IVA, |
| 351 | .mm.pmic = &palmas, |
Nishanth Menon | 07be757 | 2016-04-21 14:34:24 -0500 | [diff] [blame] | 352 | .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, |
Nishanth Menon | 159a21f | 2017-08-04 21:42:09 -0500 | [diff] [blame] | 353 | |
| 354 | .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN, |
| 355 | .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, |
| 356 | |
| 357 | .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN, |
| 358 | .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, |
| 359 | |
| 360 | .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN, |
| 361 | .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, |
SRICHARAN R | 00d328c | 2013-02-04 04:22:02 +0000 | [diff] [blame] | 362 | }; |
| 363 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 364 | /* |
| 365 | * Enable essential clock domains, modules and |
| 366 | * do some additional special settings needed |
| 367 | */ |
| 368 | void enable_basic_clocks(void) |
| 369 | { |
| 370 | u32 const clk_domains_essential[] = { |
| 371 | (*prcm)->cm_l4per_clkstctrl, |
| 372 | (*prcm)->cm_l3init_clkstctrl, |
| 373 | (*prcm)->cm_memif_clkstctrl, |
| 374 | (*prcm)->cm_l4cfg_clkstctrl, |
Mugunthan V N | 4a42ff1 | 2013-07-08 16:04:40 +0530 | [diff] [blame] | 375 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 376 | (*prcm)->cm_gmac_clkstctrl, |
| 377 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 378 | 0 |
| 379 | }; |
| 380 | |
| 381 | u32 const clk_modules_hw_auto_essential[] = { |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 382 | (*prcm)->cm_l3_gpmc_clkctrl, |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 383 | (*prcm)->cm_memif_emif_1_clkctrl, |
| 384 | (*prcm)->cm_memif_emif_2_clkctrl, |
| 385 | (*prcm)->cm_l4cfg_l4_cfg_clkctrl, |
| 386 | (*prcm)->cm_wkup_gpio1_clkctrl, |
| 387 | (*prcm)->cm_l4per_gpio2_clkctrl, |
| 388 | (*prcm)->cm_l4per_gpio3_clkctrl, |
| 389 | (*prcm)->cm_l4per_gpio4_clkctrl, |
| 390 | (*prcm)->cm_l4per_gpio5_clkctrl, |
| 391 | (*prcm)->cm_l4per_gpio6_clkctrl, |
Axel Lin | 01a461f | 2013-06-21 18:54:25 +0800 | [diff] [blame] | 392 | (*prcm)->cm_l4per_gpio7_clkctrl, |
| 393 | (*prcm)->cm_l4per_gpio8_clkctrl, |
Mugunthan V N | d7ced25 | 2017-04-07 13:42:00 +0200 | [diff] [blame] | 394 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 395 | (*prcm)->cm_l3init_ocp2scp3_clkctrl, |
| 396 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 397 | 0 |
| 398 | }; |
| 399 | |
| 400 | u32 const clk_modules_explicit_en_essential[] = { |
| 401 | (*prcm)->cm_wkup_gptimer1_clkctrl, |
| 402 | (*prcm)->cm_l3init_hsmmc1_clkctrl, |
| 403 | (*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 404 | (*prcm)->cm_l4per_gptimer2_clkctrl, |
| 405 | (*prcm)->cm_wkup_wdtimer2_clkctrl, |
| 406 | (*prcm)->cm_l4per_uart3_clkctrl, |
| 407 | (*prcm)->cm_l4per_i2c1_clkctrl, |
Mugunthan V N | 4a42ff1 | 2013-07-08 16:04:40 +0530 | [diff] [blame] | 408 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 409 | (*prcm)->cm_gmac_gmac_clkctrl, |
| 410 | #endif |
Matt Porter | 3074626 | 2013-10-07 15:52:59 +0530 | [diff] [blame] | 411 | |
| 412 | #ifdef CONFIG_TI_QSPI |
| 413 | (*prcm)->cm_l4per_qspi_clkctrl, |
| 414 | #endif |
Mugunthan V N | d7ced25 | 2017-04-07 13:42:00 +0200 | [diff] [blame] | 415 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 416 | (*prcm)->cm_l3init_sata_clkctrl, |
| 417 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 418 | 0 |
| 419 | }; |
| 420 | |
| 421 | /* Enable optional additional functional clock for GPIO4 */ |
| 422 | setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, |
| 423 | GPIO4_CLKCTRL_OPTFCLKEN_MASK); |
| 424 | |
| 425 | /* Enable 96 MHz clock for MMC1 & MMC2 */ |
| 426 | setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, |
| 427 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 428 | setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 429 | HSMMC_CLKCTRL_CLKSEL_MASK); |
| 430 | |
| 431 | /* Set the correct clock dividers for mmc */ |
| 432 | setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, |
| 433 | HSMMC_CLKCTRL_CLKSEL_DIV_MASK); |
| 434 | setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, |
| 435 | HSMMC_CLKCTRL_CLKSEL_DIV_MASK); |
| 436 | |
| 437 | /* Select 32KHz clock as the source of GPTIMER1 */ |
| 438 | setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, |
| 439 | GPTIMER1_CLKCTRL_CLKSEL_MASK); |
| 440 | |
| 441 | do_enable_clocks(clk_domains_essential, |
| 442 | clk_modules_hw_auto_essential, |
| 443 | clk_modules_explicit_en_essential, |
| 444 | 1); |
| 445 | |
Matt Porter | 3074626 | 2013-10-07 15:52:59 +0530 | [diff] [blame] | 446 | #ifdef CONFIG_TI_QSPI |
| 447 | setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); |
| 448 | #endif |
| 449 | |
Mugunthan V N | d7ced25 | 2017-04-07 13:42:00 +0200 | [diff] [blame] | 450 | #ifdef CONFIG_SCSI_AHCI_PLAT |
| 451 | /* Enable optional functional clock for SATA */ |
| 452 | setbits_le32((*prcm)->cm_l3init_sata_clkctrl, |
| 453 | SATA_CLKCTRL_OPTFCLKEN_MASK); |
| 454 | #endif |
| 455 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 456 | /* Enable SCRM OPT clocks for PER and CORE dpll */ |
| 457 | setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, |
| 458 | OPTFCLKEN_SCRM_PER_MASK); |
| 459 | setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, |
| 460 | OPTFCLKEN_SCRM_CORE_MASK); |
| 461 | } |
| 462 | |
| 463 | void enable_basic_uboot_clocks(void) |
| 464 | { |
| 465 | u32 const clk_domains_essential[] = { |
Nishanth Menon | 813fe9d | 2016-11-29 15:22:00 +0530 | [diff] [blame] | 466 | #if defined(CONFIG_DRA7XX) |
Lokesh Vutla | b04038f | 2015-06-05 15:19:21 +0530 | [diff] [blame] | 467 | (*prcm)->cm_ipu_clkstctrl, |
| 468 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 469 | 0 |
| 470 | }; |
| 471 | |
| 472 | u32 const clk_modules_hw_auto_essential[] = { |
Lubomir Popov | 6535403 | 2013-04-11 00:08:51 +0000 | [diff] [blame] | 473 | (*prcm)->cm_l3init_hsusbtll_clkctrl, |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 474 | 0 |
| 475 | }; |
| 476 | |
| 477 | u32 const clk_modules_explicit_en_essential[] = { |
| 478 | (*prcm)->cm_l4per_mcspi1_clkctrl, |
| 479 | (*prcm)->cm_l4per_i2c2_clkctrl, |
| 480 | (*prcm)->cm_l4per_i2c3_clkctrl, |
| 481 | (*prcm)->cm_l4per_i2c4_clkctrl, |
Nishanth Menon | 813fe9d | 2016-11-29 15:22:00 +0530 | [diff] [blame] | 482 | #if defined(CONFIG_DRA7XX) |
Lokesh Vutla | b04038f | 2015-06-05 15:19:21 +0530 | [diff] [blame] | 483 | (*prcm)->cm_ipu_i2c5_clkctrl, |
| 484 | #else |
Lubomir Popov | b36e609 | 2013-04-08 21:49:37 +0000 | [diff] [blame] | 485 | (*prcm)->cm_l4per_i2c5_clkctrl, |
Lokesh Vutla | b04038f | 2015-06-05 15:19:21 +0530 | [diff] [blame] | 486 | #endif |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 487 | (*prcm)->cm_l3init_hsusbhost_clkctrl, |
| 488 | (*prcm)->cm_l3init_fsusb_clkctrl, |
| 489 | 0 |
| 490 | }; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 491 | do_enable_clocks(clk_domains_essential, |
| 492 | clk_modules_hw_auto_essential, |
| 493 | clk_modules_explicit_en_essential, |
| 494 | 1); |
| 495 | } |
| 496 | |
Vignesh R | 92dc6a0 | 2015-08-17 13:29:52 +0530 | [diff] [blame] | 497 | #ifdef CONFIG_TI_EDMA3 |
| 498 | void enable_edma3_clocks(void) |
| 499 | { |
| 500 | u32 const clk_domains_edma3[] = { |
| 501 | 0 |
| 502 | }; |
| 503 | |
| 504 | u32 const clk_modules_hw_auto_edma3[] = { |
| 505 | (*prcm)->cm_l3main1_tptc1_clkctrl, |
| 506 | (*prcm)->cm_l3main1_tptc2_clkctrl, |
| 507 | 0 |
| 508 | }; |
| 509 | |
| 510 | u32 const clk_modules_explicit_en_edma3[] = { |
| 511 | 0 |
| 512 | }; |
| 513 | |
| 514 | do_enable_clocks(clk_domains_edma3, |
| 515 | clk_modules_hw_auto_edma3, |
| 516 | clk_modules_explicit_en_edma3, |
| 517 | 1); |
| 518 | } |
| 519 | |
| 520 | void disable_edma3_clocks(void) |
| 521 | { |
| 522 | u32 const clk_domains_edma3[] = { |
| 523 | 0 |
| 524 | }; |
| 525 | |
| 526 | u32 const clk_modules_disable_edma3[] = { |
| 527 | (*prcm)->cm_l3main1_tptc1_clkctrl, |
| 528 | (*prcm)->cm_l3main1_tptc2_clkctrl, |
| 529 | 0 |
| 530 | }; |
| 531 | |
| 532 | do_disable_clocks(clk_domains_edma3, |
| 533 | clk_modules_disable_edma3, |
| 534 | 1); |
| 535 | } |
| 536 | #endif |
| 537 | |
Roger Quadros | 16c9710 | 2016-05-23 17:37:47 +0300 | [diff] [blame] | 538 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 539 | void enable_usb_clocks(int index) |
| 540 | { |
| 541 | u32 cm_l3init_usb_otg_ss_clkctrl = 0; |
| 542 | |
| 543 | if (index == 0) { |
| 544 | cm_l3init_usb_otg_ss_clkctrl = |
| 545 | (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; |
| 546 | /* Enable 960 MHz clock for dwc3 */ |
| 547 | setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, |
| 548 | OPTFCLKEN_REFCLK960M); |
| 549 | |
Roger Quadros | f125894 | 2016-05-23 17:37:49 +0300 | [diff] [blame] | 550 | /* Enable 32 KHz clock for USB_PHY1 */ |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 551 | setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, |
| 552 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
Roger Quadros | f125894 | 2016-05-23 17:37:49 +0300 | [diff] [blame] | 553 | |
| 554 | /* Enable 32 KHz clock for USB_PHY3 */ |
| 555 | if (is_dra7xx()) |
| 556 | setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, |
| 557 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 558 | } else if (index == 1) { |
| 559 | cm_l3init_usb_otg_ss_clkctrl = |
| 560 | (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; |
| 561 | /* Enable 960 MHz clock for dwc3 */ |
| 562 | setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, |
| 563 | OPTFCLKEN_REFCLK960M); |
| 564 | |
| 565 | /* Enable 32 KHz clock for dwc3 */ |
| 566 | setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, |
| 567 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
| 568 | |
| 569 | /* Enable 60 MHz clock for USB2PHY2 */ |
| 570 | setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, |
| 571 | L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); |
| 572 | } |
| 573 | |
| 574 | u32 const clk_domains_usb[] = { |
| 575 | 0 |
| 576 | }; |
| 577 | |
| 578 | u32 const clk_modules_hw_auto_usb[] = { |
| 579 | (*prcm)->cm_l3init_ocp2scp1_clkctrl, |
| 580 | cm_l3init_usb_otg_ss_clkctrl, |
| 581 | 0 |
| 582 | }; |
| 583 | |
| 584 | u32 const clk_modules_explicit_en_usb[] = { |
| 585 | 0 |
| 586 | }; |
| 587 | |
| 588 | do_enable_clocks(clk_domains_usb, |
| 589 | clk_modules_hw_auto_usb, |
| 590 | clk_modules_explicit_en_usb, |
| 591 | 1); |
| 592 | } |
| 593 | |
| 594 | void disable_usb_clocks(int index) |
| 595 | { |
| 596 | u32 cm_l3init_usb_otg_ss_clkctrl = 0; |
| 597 | |
| 598 | if (index == 0) { |
| 599 | cm_l3init_usb_otg_ss_clkctrl = |
| 600 | (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; |
| 601 | /* Disable 960 MHz clock for dwc3 */ |
| 602 | clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, |
| 603 | OPTFCLKEN_REFCLK960M); |
| 604 | |
Roger Quadros | f125894 | 2016-05-23 17:37:49 +0300 | [diff] [blame] | 605 | /* Disable 32 KHz clock for USB_PHY1 */ |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 606 | clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, |
| 607 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
Roger Quadros | f125894 | 2016-05-23 17:37:49 +0300 | [diff] [blame] | 608 | |
| 609 | /* Disable 32 KHz clock for USB_PHY3 */ |
| 610 | if (is_dra7xx()) |
| 611 | clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, |
| 612 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
Kishon Vijay Abraham I | f54117d | 2015-08-19 16:16:25 +0530 | [diff] [blame] | 613 | } else if (index == 1) { |
| 614 | cm_l3init_usb_otg_ss_clkctrl = |
| 615 | (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; |
| 616 | /* Disable 960 MHz clock for dwc3 */ |
| 617 | clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, |
| 618 | OPTFCLKEN_REFCLK960M); |
| 619 | |
| 620 | /* Disable 32 KHz clock for dwc3 */ |
| 621 | clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, |
| 622 | USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); |
| 623 | |
| 624 | /* Disable 60 MHz clock for USB2PHY2 */ |
| 625 | clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, |
| 626 | L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); |
| 627 | } |
| 628 | |
| 629 | u32 const clk_domains_usb[] = { |
| 630 | 0 |
| 631 | }; |
| 632 | |
| 633 | u32 const clk_modules_disable[] = { |
| 634 | (*prcm)->cm_l3init_ocp2scp1_clkctrl, |
| 635 | cm_l3init_usb_otg_ss_clkctrl, |
| 636 | 0 |
| 637 | }; |
| 638 | |
| 639 | do_disable_clocks(clk_domains_usb, |
| 640 | clk_modules_disable, |
| 641 | 1); |
| 642 | } |
| 643 | #endif |
| 644 | |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 645 | const struct ctrl_ioregs ioregs_omap5430 = { |
| 646 | .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, |
| 647 | .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, |
| 648 | .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, |
| 649 | .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, |
| 650 | .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, |
| 651 | }; |
| 652 | |
| 653 | const struct ctrl_ioregs ioregs_omap5432_es1 = { |
| 654 | .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, |
| 655 | .ctrl_lpddr2ch = 0x0, |
| 656 | .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, |
| 657 | .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, |
| 658 | .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, |
| 659 | .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, |
| 660 | .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, |
SRICHARAN R | e02f5f8 | 2013-11-08 17:40:37 +0530 | [diff] [blame] | 661 | .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 662 | }; |
| 663 | |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 664 | const struct ctrl_ioregs ioregs_omap5432_es2 = { |
| 665 | .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, |
| 666 | .ctrl_lpddr2ch = 0x0, |
| 667 | .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, |
| 668 | .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, |
| 669 | .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, |
| 670 | .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, |
| 671 | .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, |
SRICHARAN R | e02f5f8 | 2013-11-08 17:40:37 +0530 | [diff] [blame] | 672 | .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 673 | }; |
| 674 | |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 675 | const struct ctrl_ioregs ioregs_dra7xx_es1 = { |
| 676 | .ctrl_ddrch = 0x40404040, |
| 677 | .ctrl_lpddr2ch = 0x40404040, |
| 678 | .ctrl_ddr3ch = 0x80808080, |
Lokesh Vutla | 07fbc33 | 2015-06-03 14:43:27 +0530 | [diff] [blame] | 679 | .ctrl_ddrio_0 = 0x00094A40, |
| 680 | .ctrl_ddrio_1 = 0x04A52000, |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 681 | .ctrl_ddrio_2 = 0x84210000, |
Nishanth Menon | f013a3a | 2015-06-16 08:29:01 -0500 | [diff] [blame] | 682 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, |
| 683 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 684 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, |
| 685 | }; |
| 686 | |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 687 | const struct ctrl_ioregs ioregs_dra72x_es1 = { |
| 688 | .ctrl_ddrch = 0x40404040, |
| 689 | .ctrl_lpddr2ch = 0x40404040, |
| 690 | .ctrl_ddr3ch = 0x60606080, |
Lokesh Vutla | 07fbc33 | 2015-06-03 14:43:27 +0530 | [diff] [blame] | 691 | .ctrl_ddrio_0 = 0x00094A40, |
| 692 | .ctrl_ddrio_1 = 0x04A52000, |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 693 | .ctrl_ddrio_2 = 0x84210000, |
Nishanth Menon | f013a3a | 2015-06-16 08:29:01 -0500 | [diff] [blame] | 694 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, |
| 695 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 696 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, |
| 697 | }; |
| 698 | |
Nishanth Menon | 3269997 | 2016-03-15 18:09:12 -0500 | [diff] [blame] | 699 | const struct ctrl_ioregs ioregs_dra72x_es2 = { |
| 700 | .ctrl_ddrch = 0x40404040, |
| 701 | .ctrl_lpddr2ch = 0x40404040, |
| 702 | .ctrl_ddr3ch = 0x60606060, |
| 703 | .ctrl_ddrio_0 = 0x00094A40, |
| 704 | .ctrl_ddrio_1 = 0x00000000, |
| 705 | .ctrl_ddrio_2 = 0x00000000, |
| 706 | .ctrl_emif_sdram_config_ext = 0x0001C1A7, |
| 707 | .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, |
| 708 | .ctrl_ddr_ctrl_ext_0 = 0xA2000000, |
| 709 | }; |
| 710 | |
Felipe Balbi | 449a437 | 2014-11-06 08:28:48 -0600 | [diff] [blame] | 711 | void __weak hw_data_init(void) |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 712 | { |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 713 | u32 omap_rev = omap_revision(); |
| 714 | |
| 715 | switch (omap_rev) { |
| 716 | |
| 717 | case OMAP5430_ES1_0: |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 718 | case OMAP5432_ES1_0: |
| 719 | *prcm = &omap5_es1_prcm; |
| 720 | *dplls_data = &omap5_dplls_es1; |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 721 | *omap_vcores = &omap5430_volts; |
Lokesh Vutla | f120cef | 2013-02-12 21:29:06 +0000 | [diff] [blame] | 722 | *ctrl = &omap5_ctrl; |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 723 | break; |
| 724 | |
SRICHARAN R | 06ebff4 | 2013-02-12 01:33:42 +0000 | [diff] [blame] | 725 | case OMAP5430_ES2_0: |
| 726 | case OMAP5432_ES2_0: |
| 727 | *prcm = &omap5_es2_prcm; |
SRICHARAN R | a04ed14 | 2013-02-12 01:33:43 +0000 | [diff] [blame] | 728 | *dplls_data = &omap5_dplls_es2; |
| 729 | *omap_vcores = &omap5430_volts_es2; |
Lokesh Vutla | f120cef | 2013-02-12 21:29:06 +0000 | [diff] [blame] | 730 | *ctrl = &omap5_ctrl; |
SRICHARAN R | 06ebff4 | 2013-02-12 01:33:42 +0000 | [diff] [blame] | 731 | break; |
| 732 | |
Praneeth Bajjuri | 9b21ff4 | 2017-08-21 12:50:52 +0530 | [diff] [blame^] | 733 | case DRA762_ES1_0: |
| 734 | *prcm = &dra7xx_prcm; |
| 735 | *dplls_data = &dra76x_dplls; |
| 736 | *ctrl = &dra7xx_ctrl; |
| 737 | break; |
| 738 | |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 739 | case DRA752_ES1_0: |
Nishanth Menon | 60475ff | 2014-01-14 10:54:42 -0600 | [diff] [blame] | 740 | case DRA752_ES1_1: |
Nishanth Menon | 4de1668 | 2015-08-13 09:50:58 -0500 | [diff] [blame] | 741 | case DRA752_ES2_0: |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 742 | *prcm = &dra7xx_prcm; |
Lokesh Vutla | 5e70e29 | 2013-02-12 21:29:05 +0000 | [diff] [blame] | 743 | *dplls_data = &dra7xx_dplls; |
Lokesh Vutla | f120cef | 2013-02-12 21:29:06 +0000 | [diff] [blame] | 744 | *ctrl = &dra7xx_ctrl; |
Lokesh Vutla | 15c2c70 | 2013-02-17 23:33:37 +0000 | [diff] [blame] | 745 | break; |
| 746 | |
Lokesh Vutla | 95d1116 | 2014-05-15 11:08:40 +0530 | [diff] [blame] | 747 | case DRA722_ES1_0: |
Ravi Babu | af9af44 | 2016-03-15 18:09:11 -0500 | [diff] [blame] | 748 | case DRA722_ES2_0: |
Lokesh Vutla | 95d1116 | 2014-05-15 11:08:40 +0530 | [diff] [blame] | 749 | *prcm = &dra7xx_prcm; |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 750 | *dplls_data = &dra72x_dplls; |
Lokesh Vutla | 95d1116 | 2014-05-15 11:08:40 +0530 | [diff] [blame] | 751 | *ctrl = &dra7xx_ctrl; |
| 752 | break; |
| 753 | |
SRICHARAN R | 1a79cab | 2013-02-04 04:22:01 +0000 | [diff] [blame] | 754 | default: |
| 755 | printf("\n INVALID OMAP REVISION "); |
| 756 | } |
SRICHARAN R | fb6aa1f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 757 | } |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 758 | |
| 759 | void get_ioregs(const struct ctrl_ioregs **regs) |
| 760 | { |
| 761 | u32 omap_rev = omap_revision(); |
| 762 | |
| 763 | switch (omap_rev) { |
| 764 | case OMAP5430_ES1_0: |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 765 | case OMAP5430_ES2_0: |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 766 | *regs = &ioregs_omap5430; |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 767 | break; |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 768 | case OMAP5432_ES1_0: |
| 769 | *regs = &ioregs_omap5432_es1; |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 770 | break; |
Lokesh Vutla | 79a9ec7 | 2013-02-12 01:33:44 +0000 | [diff] [blame] | 771 | case OMAP5432_ES2_0: |
| 772 | *regs = &ioregs_omap5432_es2; |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 773 | break; |
| 774 | case DRA752_ES1_0: |
Nishanth Menon | 60475ff | 2014-01-14 10:54:42 -0600 | [diff] [blame] | 775 | case DRA752_ES1_1: |
Nishanth Menon | 4de1668 | 2015-08-13 09:50:58 -0500 | [diff] [blame] | 776 | case DRA752_ES2_0: |
Sricharan R | ffa9818 | 2013-05-30 03:19:39 +0000 | [diff] [blame] | 777 | *regs = &ioregs_dra7xx_es1; |
| 778 | break; |
R Sricharan | 5a9d4d1 | 2014-08-28 12:01:04 +0530 | [diff] [blame] | 779 | case DRA722_ES1_0: |
| 780 | *regs = &ioregs_dra72x_es1; |
| 781 | break; |
Nishanth Menon | 3269997 | 2016-03-15 18:09:12 -0500 | [diff] [blame] | 782 | case DRA722_ES2_0: |
| 783 | *regs = &ioregs_dra72x_es2; |
| 784 | break; |
Lokesh Vutla | d8ac050 | 2013-02-04 04:22:05 +0000 | [diff] [blame] | 785 | |
| 786 | default: |
| 787 | printf("\n INVALID OMAP REVISION "); |
| 788 | } |
| 789 | } |