arm: dra76: Add support for ES1.0 detection
dra76 family is a high-performance, infotainment application
device, based on OMAP architecture on a 28-nm technology.
This contains most of the subsystems, peripherals that are
available on dra74, dra72 family. This SoC mainly features
Subsystems:
- 2 x Cortex-A15 with max speed of 1.8GHz
- 2 X DSP
- 2 X Cortex-M4 IPU
- ISS
- CAL
- DSS
- VPE
- VIP
Connectivity peripherals:
- 1 USB3.0 and 3 USB2.0 subsystems
- 1 x SATA
- 2 x PCI Express Gen2
- 3-port Gigabit ethernet switch
- 2 x CAN
- MCAN
Adding CPU detection support for the dra76 ES1.0 soc
and update prcm, control module, dplls data.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index 4ad6b53..19a8d10 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -113,6 +113,16 @@
{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
+static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
+ {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */
+ {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
@@ -234,6 +244,17 @@
.ddr = NULL
};
+struct dplls dra76x_dplls = {
+ .mpu = mpu_dpll_params_1ghz,
+ .core = core_dpll_params_2128mhz_dra7xx,
+ .per = per_dpll_params_768mhz_dra76x,
+ .abe = abe_dpll_params_sysclk2_361267khz,
+ .iva = iva_dpll_params_2330mhz_dra7xx,
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = ddr_dpll_params_2664mhz,
+ .gmac = gmac_dpll_params_2000mhz,
+};
+
struct dplls dra7xx_dplls = {
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_dra7xx,
@@ -709,6 +730,12 @@
*ctrl = &omap5_ctrl;
break;
+ case DRA762_ES1_0:
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra76x_dplls;
+ *ctrl = &dra7xx_ctrl;
+ break;
+
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0: