blob: 77ee897ddc5f2111eabb95a0926025c2df997b81 [file] [log] [blame]
Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
Paul Beesleyf8640672019-04-12 14:19:42 +010016``include/plat/common/platform.h``. The firmware provides a default
17implementation of variables and functions to fulfill the optional requirements.
18These implementations are all weakly defined; they are provided to ease the
19porting effort. Each platform port can override them with its own implementation
20if the default implementation is inadequate.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022Some modifications are common to all Boot Loader (BL) stages. Section 2
23discusses these in detail. The subsequent sections discuss the remaining
24modifications for each BL stage in detail.
25
Paul Beesleyf8640672019-04-12 14:19:42 +010026Please refer to the :ref:`Platform Compatibility Policy` for the policy
27regarding compatibility and deprecation of these porting interfaces.
Soby Mathew02bdbb92018-09-26 11:17:23 +010028
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000029Only Arm development platforms (such as FVP and Juno) may use the
30functions/definitions in ``include/plat/arm/common/`` and the corresponding
31source files in ``plat/arm/common/``. This is done so that there are no
32dependencies between platforms maintained by different people/companies. If you
33want to use any of the functionality present in ``plat/arm`` files, please
34create a pull request that moves the code to ``plat/common`` so that it can be
35discussed.
36
Douglas Raillardd7c21b72017-06-28 15:23:03 +010037Common modifications
38--------------------
39
40This section covers the modifications that should be made by the platform for
41each BL stage to correctly port the firmware stack. They are categorized as
42either mandatory or optional.
43
44Common mandatory modifications
45------------------------------
46
47A platform port must enable the Memory Management Unit (MMU) as well as the
48instruction and data caches for each BL stage. Setting up the translation
49tables is the responsibility of the platform port because memory maps differ
50across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010051provided to help in this setup.
52
53Note that although this library supports non-identity mappings, this is intended
54only for re-mapping peripheral physical addresses and allows platforms with high
55I/O addresses to reduce their virtual address space. All other addresses
56corresponding to code and data must currently use an identity mapping.
57
Dan Handley610e7e12018-03-01 18:44:00 +000058Also, the only translation granule size supported in TF-A is 4KB, as various
59parts of the code assume that is the case. It is not possible to switch to
6016 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010061
Dan Handley610e7e12018-03-01 18:44:00 +000062In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
64an identity mapping for all addresses.
65
66If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
67block of identity mapped secure memory with Device-nGnRE attributes aligned to
68page boundary (4K) for each BL stage. All sections which allocate coherent
69memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
70section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
71possible for the firmware to place variables in it using the following C code
72directive:
73
74::
75
76 __section("bakery_lock")
77
78Or alternatively the following assembler code directive:
79
80::
81
82 .section bakery_lock
83
84The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
85used to allocate any data structures that are accessed both when a CPU is
86executing with its MMU and caches enabled, and when it's running with its MMU
87and caches disabled. Examples are given below.
88
89The following variables, functions and constants must be defined by the platform
90for the firmware to work correctly.
91
Javier Almansa Sobrino37bf69c2022-04-07 18:26:49 +010092.. _platform_def_mandatory:
93
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +010094File : platform_def.h [mandatory]
95~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +010096
97Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000098include path with the following constants defined. This will require updating
99the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100
Paul Beesleyf8640672019-04-12 14:19:42 +0100101Platform ports may optionally use the file ``include/plat/common/common_def.h``,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100102which provides typical values for some of the constants below. These values are
103likely to be suitable for all platform ports.
104
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100105- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100106
107 Defines the linker format used by the platform, for example
108 ``elf64-littleaarch64``.
109
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100110- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100111
112 Defines the processor architecture for the linker by the platform, for
113 example ``aarch64``.
114
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100115- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100116
117 Defines the normal stack memory available to each CPU. This constant is used
Paul Beesleyf8640672019-04-12 14:19:42 +0100118 by ``plat/common/aarch64/platform_mp_stack.S`` and
119 ``plat/common/aarch64/platform_up_stack.S``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
David Horstmann051fd6d2020-11-12 15:19:04 +0000121- **#define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100122
123 Defines the size in bits of the largest cache line across all the cache
124 levels in the platform.
125
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100126- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127
128 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
129 function.
130
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100131- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132
133 Defines the total number of CPUs implemented by the platform across all
134 clusters in the system.
135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100136- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137
138 Defines the total number of nodes in the power domain topology
139 tree at all the power domain levels used by the platform.
140 This macro is used by the PSCI implementation to allocate
141 data structures to represent power domain topology.
142
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100143- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100144
145 Defines the maximum power domain level that the power management operations
146 should apply to. More often, but not always, the power domain level
147 corresponds to affinity level. This macro allows the PSCI implementation
148 to know the highest power domain level that it should consider for power
149 management operations in the system that the platform implements. For
150 example, the Base AEM FVP implements two clusters with a configurable
151 number of CPUs and it reports the maximum power domain level as 1.
152
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100153- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100154
155 Defines the local power state corresponding to the deepest power down
156 possible at every power domain level in the platform. The local power
157 states for each level may be sparsely allocated between 0 and this value
158 with 0 being reserved for the RUN state. The PSCI implementation uses this
159 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100162- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100163
164 Defines the local power state corresponding to the deepest retention state
165 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100166 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100168 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100170- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100171
172 Defines the maximum number of local power states per power domain level
173 that the platform supports. The default value of this macro is 2 since
174 most platforms just support a maximum of two local power states at each
175 power domain level (power-down and retention). If the platform needs to
176 account for more local power states, then it must redefine this macro.
177
178 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100179 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100181- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100182
183 Defines the base address in secure ROM where BL1 originally lives. Must be
184 aligned on a page-size boundary.
185
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100186- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100187
188 Defines the maximum address in secure ROM that BL1's actual content (i.e.
189 excluding any data section allocated at runtime) can occupy.
190
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100191- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100192
193 Defines the base address in secure RAM where BL1's read-write data will live
194 at runtime. Must be aligned on a page-size boundary.
195
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100196- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100197
198 Defines the maximum address in secure RAM that BL1's read-write data can
199 occupy at runtime.
200
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100201- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100202
203 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000204 Must be aligned on a page-size boundary. This constant is not applicable
205 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100207- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100208
209 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000210 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
211
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100212- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000213
214 Defines the base address in secure XIP memory where BL2 RO section originally
215 lives. Must be aligned on a page-size boundary. This constant is only needed
216 when BL2_IN_XIP_MEM is set to '1'.
217
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100218- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000219
220 Defines the maximum address in secure XIP memory that BL2's actual content
221 (i.e. excluding any data section allocated at runtime) can occupy. This
222 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
223
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100224- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000225
226 Defines the base address in secure RAM where BL2's read-write data will live
227 at runtime. Must be aligned on a page-size boundary. This constant is only
228 needed when BL2_IN_XIP_MEM is set to '1'.
229
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100230- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000231
232 Defines the maximum address in secure RAM that BL2's read-write data can
233 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
234 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100236- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100237
238 Defines the base address in secure RAM where BL2 loads the BL31 binary
239 image. Must be aligned on a page-size boundary.
240
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100241- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243 Defines the maximum address in secure RAM that the BL31 image can occupy.
244
245For every image, the platform must define individual identifiers that will be
246used by BL1 or BL2 to load the corresponding image into memory from non-volatile
247storage. For the sake of performance, integer numbers will be used as
248identifiers. The platform will use those identifiers to return the relevant
249information about the image to be loaded (file handler, load address,
250authentication information, etc.). The following image identifiers are
251mandatory:
252
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100253- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100254
255 BL2 image identifier, used by BL1 to load BL2.
256
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100257- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100258
259 BL31 image identifier, used by BL2 to load BL31.
260
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100261- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100262
263 BL33 image identifier, used by BL2 to load BL33.
264
265If Trusted Board Boot is enabled, the following certificate identifiers must
266also be defined:
267
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100268- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100269
270 BL2 content certificate identifier, used by BL1 to load the BL2 content
271 certificate.
272
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100273- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100274
275 Trusted key certificate identifier, used by BL2 to load the trusted key
276 certificate.
277
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100278- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
280 BL31 key certificate identifier, used by BL2 to load the BL31 key
281 certificate.
282
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100283- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100284
285 BL31 content certificate identifier, used by BL2 to load the BL31 content
286 certificate.
287
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100288- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100289
290 BL33 key certificate identifier, used by BL2 to load the BL33 key
291 certificate.
292
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100293- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100294
295 BL33 content certificate identifier, used by BL2 to load the BL33 content
296 certificate.
297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100298- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100300 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100301 FWU content certificate.
302
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100303- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304
Dan Handley610e7e12018-03-01 18:44:00 +0000305 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000307 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100308 set.
309
310If the AP Firmware Updater Configuration image, BL2U is used, the following
311must also be defined:
312
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100313- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100314
315 Defines the base address in secure memory where BL1 copies the BL2U binary
316 image. Must be aligned on a page-size boundary.
317
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100318- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100319
320 Defines the maximum address in secure memory that the BL2U image can occupy.
321
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100322- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100323
324 BL2U image identifier, used by BL1 to fetch an image descriptor
325 corresponding to BL2U.
326
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100327If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100328must also be defined:
329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100331
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100332 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
333 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000334
335 .. note::
336 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100337
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100338If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100339also be defined:
340
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100341- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100342
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100343 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100344 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000345
346 .. note::
347 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100349- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100350
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100351 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
352 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100354If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100355be defined:
356
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100357- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100358
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100359 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000361
362 .. note::
363 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100364
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100365- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100366
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100367 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
368 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100369
370For the the Firmware update capability of TRUSTED BOARD BOOT, the following
371macros may also be defined:
372
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100373- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374
375 Total number of images that can be loaded simultaneously. If the platform
376 doesn't specify any value, it defaults to 10.
377
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100378If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100379also be defined:
380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100381- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100382
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100383 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000384 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100386- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100388 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100389 certificate (mandatory when Trusted Board Boot is enabled).
390
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100391- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100393 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394 content certificate (mandatory when Trusted Board Boot is enabled).
395
396If a BL32 image is supported by the platform, the following constants must
397also be defined:
398
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100399- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100400
401 BL32 image identifier, used by BL2 to load BL32.
402
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100403- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100404
405 BL32 key certificate identifier, used by BL2 to load the BL32 key
406 certificate (mandatory when Trusted Board Boot is enabled).
407
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100408- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100409
410 BL32 content certificate identifier, used by BL2 to load the BL32 content
411 certificate (mandatory when Trusted Board Boot is enabled).
412
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100413- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100414
415 Defines the base address in secure memory where BL2 loads the BL32 binary
416 image. Must be aligned on a page-size boundary.
417
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100418- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100419
420 Defines the maximum address that the BL32 image can occupy.
421
422If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
423platform, the following constants must also be defined:
424
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100425- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100426
427 Defines the base address of the secure memory used by the TSP image on the
428 platform. This must be at the same address or below ``BL32_BASE``.
429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100430- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100431
432 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000433 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
434 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
435 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100437- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100438
439 Defines the ID of the secure physical generic timer interrupt used by the
440 TSP's interrupt handling code.
441
442If the platform port uses the translation table library code, the following
443constants must also be defined:
444
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100445- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100446
447 Optional flag that can be set per-image to enable the dynamic allocation of
448 regions even when the MMU is enabled. If not defined, only static
449 functionality will be available, if defined and set to 1 it will also
450 include the dynamic functionality.
451
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100452- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100453
454 Defines the maximum number of translation tables that are allocated by the
455 translation table library code. To minimize the amount of runtime memory
456 used, choose the smallest value needed to map the required virtual addresses
457 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
458 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
459 as well.
460
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100461- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100462
463 Defines the maximum number of regions that are allocated by the translation
464 table library code. A region consists of physical base address, virtual base
465 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
466 defined in the ``mmap_region_t`` structure. The platform defines the regions
467 that should be mapped. Then, the translation table library will create the
468 corresponding tables and descriptors at runtime. To minimize the amount of
469 runtime memory used, choose the smallest value needed to register the
470 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
471 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
472 the dynamic regions as well.
473
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100474- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100475
476 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000477 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100478
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100479- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100480
481 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000482 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100483
484If the platform port uses the IO storage framework, the following constants
485must also be defined:
486
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100487- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100488
489 Defines the maximum number of registered IO devices. Attempting to register
490 more devices than this value using ``io_register_device()`` will fail with
491 -ENOMEM.
492
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100493- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100494
495 Defines the maximum number of open IO handles. Attempting to open more IO
496 entities than this value using ``io_open()`` will fail with -ENOMEM.
497
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100498- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100499
500 Defines the maximum number of registered IO block devices. Attempting to
501 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100502 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100503 With this macro, multiple block devices could be supported at the same
504 time.
505
506If the platform needs to allocate data within the per-cpu data framework in
507BL31, it should define the following macro. Currently this is only required if
508the platform decides not to use the coherent memory section by undefining the
509``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
510required memory within the the per-cpu data to minimize wastage.
511
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100512- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100513
514 Defines the memory (in bytes) to be reserved within the per-cpu data
515 structure for use by the platform layer.
516
517The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000518memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100519
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100520- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100521
522 Defines the maximum address in secure RAM that the BL31's progbits sections
523 can occupy.
524
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100525- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100526
527 Defines the maximum address that the TSP's progbits sections can occupy.
528
529If the platform port uses the PL061 GPIO driver, the following constant may
530optionally be defined:
531
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100532- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100533 Maximum number of GPIOs required by the platform. This allows control how
534 much memory is allocated for PL061 GPIO controllers. The default value is
535
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100536 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100537
538If the platform port uses the partition driver, the following constant may
539optionally be defined:
540
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100541- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100542 Maximum number of partition entries required by the platform. This allows
543 control how much memory is allocated for partition entries. The default
544 value is 128.
Paul Beesleyf8640672019-04-12 14:19:42 +0100545 For example, define the build flag in ``platform.mk``:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100546 PLAT_PARTITION_MAX_ENTRIES := 12
547 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100548
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800549- **PLAT_PARTITION_BLOCK_SIZE**
550 The size of partition block. It could be either 512 bytes or 4096 bytes.
551 The default value is 512.
Paul Beesleyf2ec7142019-10-04 16:17:46 +0000552 For example, define the build flag in ``platform.mk``:
Haojian Zhuang42a746d2019-09-14 18:01:16 +0800553 PLAT_PARTITION_BLOCK_SIZE := 4096
554 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
555
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100556The following constant is optional. It should be defined to override the default
557behaviour of the ``assert()`` function (for example, to save memory).
558
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100559- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100560 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
561 ``assert()`` prints the name of the file, the line number and the asserted
562 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
563 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
564 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
565 defined, it defaults to ``LOG_LEVEL``.
566
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100567File : plat_macros.S [mandatory]
568~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100569
570Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000571the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100572found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
573
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100574- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100575
576 This macro allows the crash reporting routine to print relevant platform
577 registers in case of an unhandled exception in BL31. This aids in debugging
578 and this macro can be defined to be empty in case register reporting is not
579 desired.
580
581 For instance, GIC or interconnect registers may be helpful for
582 troubleshooting.
583
584Handling Reset
585--------------
586
587BL1 by default implements the reset vector where execution starts from a cold
588or warm boot. BL31 can be optionally set as a reset vector using the
589``RESET_TO_BL31`` make variable.
590
591For each CPU, the reset vector code is responsible for the following tasks:
592
593#. Distinguishing between a cold boot and a warm boot.
594
595#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
596 the CPU is placed in a platform-specific state until the primary CPU
597 performs the necessary steps to remove it from this state.
598
599#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
600 specific address in the BL31 image in the same processor mode as it was
601 when released from reset.
602
603The following functions need to be implemented by the platform port to enable
604reset vector code to perform the above tasks.
605
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100606Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
607~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100608
609::
610
611 Argument : void
612 Return : uintptr_t
613
614This function is called with the MMU and caches disabled
615(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
616distinguishing between a warm and cold reset for the current CPU using
617platform-specific means. If it's a warm reset, then it returns the warm
618reset entrypoint point provided to ``plat_setup_psci_ops()`` during
619BL31 initialization. If it's a cold reset then this function must return zero.
620
621This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000622Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100623not assume that callee saved registers are preserved across a call to this
624function.
625
626This function fulfills requirement 1 and 3 listed above.
627
628Note that for platforms that support programming the reset address, it is
629expected that a CPU will start executing code directly at the right address,
630both on a cold and warm reset. In this case, there is no need to identify the
631type of reset nor to query the warm reset entrypoint. Therefore, implementing
632this function is not required on such platforms.
633
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100634Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
635~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100636
637::
638
639 Argument : void
640
641This function is called with the MMU and data caches disabled. It is responsible
642for placing the executing secondary CPU in a platform-specific state until the
643primary CPU performs the necessary actions to bring it out of that state and
644allow entry into the OS. This function must not return.
645
Dan Handley610e7e12018-03-01 18:44:00 +0000646In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100647itself off. The primary CPU is responsible for powering up the secondary CPUs
648when normal world software requires them. When booting an EL3 payload instead,
649they stay powered on and are put in a holding pen until their mailbox gets
650populated.
651
652This function fulfills requirement 2 above.
653
654Note that for platforms that can't release secondary CPUs out of reset, only the
655primary CPU will execute the cold boot code. Therefore, implementing this
656function is not required on such platforms.
657
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100658Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
659~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100660
661::
662
663 Argument : void
664 Return : unsigned int
665
666This function identifies whether the current CPU is the primary CPU or a
667secondary CPU. A return value of zero indicates that the CPU is not the
668primary CPU, while a non-zero return value indicates that the CPU is the
669primary CPU.
670
671Note that for platforms that can't release secondary CPUs out of reset, only the
672primary CPU will execute the cold boot code. Therefore, there is no need to
673distinguish between primary and secondary CPUs and implementing this function is
674not required.
675
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100676Function : platform_mem_init() [mandatory]
677~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100678
679::
680
681 Argument : void
682 Return : void
683
684This function is called before any access to data is made by the firmware, in
685order to carry out any essential memory initialization.
686
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100687Function: plat_get_rotpk_info()
688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100689
690::
691
692 Argument : void *, void **, unsigned int *, unsigned int *
693 Return : int
694
695This function is mandatory when Trusted Board Boot is enabled. It returns a
696pointer to the ROTPK stored in the platform (or a hash of it) and its length.
697The ROTPK must be encoded in DER format according to the following ASN.1
698structure:
699
700::
701
702 AlgorithmIdentifier ::= SEQUENCE {
703 algorithm OBJECT IDENTIFIER,
704 parameters ANY DEFINED BY algorithm OPTIONAL
705 }
706
707 SubjectPublicKeyInfo ::= SEQUENCE {
708 algorithm AlgorithmIdentifier,
709 subjectPublicKey BIT STRING
710 }
711
712In case the function returns a hash of the key:
713
714::
715
716 DigestInfo ::= SEQUENCE {
717 digestAlgorithm AlgorithmIdentifier,
718 digest OCTET STRING
719 }
720
721The function returns 0 on success. Any other value is treated as error by the
722Trusted Board Boot. The function also reports extra information related
723to the ROTPK in the flags parameter:
724
725::
726
727 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
728 hash.
729 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
730 verification while the platform ROTPK is not deployed.
731 When this flag is set, the function does not need to
732 return a platform ROTPK, and the authentication
733 framework uses the ROTPK in the certificate without
734 verifying it against the platform value. This flag
735 must not be used in a deployed production environment.
736
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100737Function: plat_get_nv_ctr()
738~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100739
740::
741
742 Argument : void *, unsigned int *
743 Return : int
744
745This function is mandatory when Trusted Board Boot is enabled. It returns the
746non-volatile counter value stored in the platform in the second argument. The
747cookie in the first argument may be used to select the counter in case the
748platform provides more than one (for example, on platforms that use the default
749TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100750TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100751
752The function returns 0 on success. Any other value means the counter value could
753not be retrieved from the platform.
754
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100755Function: plat_set_nv_ctr()
756~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100757
758::
759
760 Argument : void *, unsigned int
761 Return : int
762
763This function is mandatory when Trusted Board Boot is enabled. It sets a new
764counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100765select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100766the updated counter value to be written to the NV counter.
767
768The function returns 0 on success. Any other value means the counter value could
769not be updated.
770
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100771Function: plat_set_nv_ctr2()
772~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100773
774::
775
776 Argument : void *, const auth_img_desc_t *, unsigned int
777 Return : int
778
779This function is optional when Trusted Board Boot is enabled. If this
780interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
781first argument passed is a cookie and is typically used to
782differentiate between a Non Trusted NV Counter and a Trusted NV
783Counter. The second argument is a pointer to an authentication image
784descriptor and may be used to decide if the counter is allowed to be
785updated or not. The third argument is the updated counter value to
786be written to the NV counter.
787
788The function returns 0 on success. Any other value means the counter value
789either could not be updated or the authentication image descriptor indicates
790that it is not allowed to be updated.
791
792Common mandatory function modifications
793---------------------------------------
794
795The following functions are mandatory functions which need to be implemented
796by the platform port.
797
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100798Function : plat_my_core_pos()
799~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100800
801::
802
803 Argument : void
804 Return : unsigned int
805
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000806This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100807CPU-specific linear index into blocks of memory (for example while allocating
808per-CPU stacks). This function will be invoked very early in the
809initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000810implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100811runtime environment. This function can clobber x0 - x8 and must preserve
812x9 - x29.
813
814This function plays a crucial role in the power domain topology framework in
Paul Beesleyf8640672019-04-12 14:19:42 +0100815PSCI and details of this can be found in
816:ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100817
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100818Function : plat_core_pos_by_mpidr()
819~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100820
821::
822
823 Argument : u_register_t
824 Return : int
825
826This function validates the ``MPIDR`` of a CPU and converts it to an index,
827which can be used as a CPU-specific linear index into blocks of memory. In
828case the ``MPIDR`` is invalid, this function returns -1. This function will only
829be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +0000830utilize the C runtime environment. For further details about how TF-A
831represents the power domain topology and how this relates to the linear CPU
Paul Beesleyf8640672019-04-12 14:19:42 +0100832index, please refer :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100833
Ambroise Vincentd207f562019-04-10 12:50:27 +0100834Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
835~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
836
837::
838
839 Arguments : void **heap_addr, size_t *heap_size
840 Return : int
841
842This function is invoked during Mbed TLS library initialisation to get a heap,
843by means of a starting address and a size. This heap will then be used
844internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
845must be able to provide a heap to it.
846
847A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
848which a heap is statically reserved during compile time inside every image
849(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
850the function simply returns the address and size of this "pre-allocated" heap.
851For a platform to use this default implementation, only a call to the helper
852from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
853
854However, by writting their own implementation, platforms have the potential to
855optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
856shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
857twice.
858
859On success the function should return 0 and a negative error code otherwise.
860
Sumit Gargc0c369c2019-11-15 18:47:53 +0530861Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]
862~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
863
864::
865
866 Arguments : enum fw_enc_status_t fw_enc_status, uint8_t *key,
867 size_t *key_len, unsigned int *flags, const uint8_t *img_id,
868 size_t img_id_len
869 Return : int
870
871This function provides a symmetric key (either SSK or BSSK depending on
872fw_enc_status) which is invoked during runtime decryption of encrypted
873firmware images. `plat/common/plat_bl_common.c` provides a dummy weak
874implementation for testing purposes which must be overridden by the platform
875trying to implement a real world firmware encryption use-case.
876
877It also allows the platform to pass symmetric key identifier rather than
878actual symmetric key which is useful in cases where the crypto backend provides
879secure storage for the symmetric key. So in this case ``ENC_KEY_IS_IDENTIFIER``
880flag must be set in ``flags``.
881
882In addition to above a platform may also choose to provide an image specific
883symmetric key/identifier using img_id.
884
885On success the function should return 0 and a negative error code otherwise.
886
Manish Pandey34a305e2021-10-21 21:53:49 +0100887Note that this API depends on ``DECRYPTION_SUPPORT`` build flag.
Sumit Gargc0c369c2019-11-15 18:47:53 +0530888
Manish V Badarkheda87af12021-06-20 21:14:46 +0100889Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
890~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
891
892::
893
Sughosh Ganuf40154f2021-11-17 17:08:10 +0530894 Argument : const struct fwu_metadata *metadata
Manish V Badarkheda87af12021-06-20 21:14:46 +0100895 Return : void
896
897This function is mandatory when PSA_FWU_SUPPORT is enabled.
898It provides a means to retrieve image specification (offset in
899non-volatile storage and length) of active/updated images using the passed
900FWU metadata, and update I/O policies of active/updated images using retrieved
901image specification information.
902Further I/O layer operations such as I/O open, I/O read, etc. on these
903images rely on this function call.
904
905In Arm platforms, this function is used to set an I/O policy of the FIP image,
906container of all active/updated secure and non-secure images.
907
908Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
909~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
910
911::
912
913 Argument : unsigned int image_id, uintptr_t *dev_handle,
914 uintptr_t *image_spec
915 Return : int
916
917This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
918responsible for setting up the platform I/O policy of the requested metadata
919image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
920be used to load this image from the platform's non-volatile storage.
921
922FWU metadata can not be always stored as a raw image in non-volatile storage
923to define its image specification (offset in non-volatile storage and length)
924statically in I/O policy.
925For example, the FWU metadata image is stored as a partition inside the GUID
926partition table image. Its specification is defined in the partition table
927that needs to be parsed dynamically.
928This function provides a means to retrieve such dynamic information to set
929the I/O policy of the FWU metadata image.
930Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
931image relies on this function call.
932
933It returns '0' on success, otherwise a negative error value on error.
934Alongside, returns device handle and image specification from the I/O policy
935of the requested FWU metadata image.
936
Sughosh Ganu4e336a62021-12-01 15:53:32 +0530937Function : plat_fwu_get_boot_idx() [when PSA_FWU_SUPPORT == 1]
938~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
939
940::
941
942 Argument : void
943 Return : uint32_t
944
945This function is mandatory when PSA_FWU_SUPPORT is enabled. It provides the
946means to retrieve the boot index value from the platform. The boot index is the
947bank from which the platform has booted the firmware images.
948
949By default, the platform will read the metadata structure and try to boot from
950the active bank. If the platform fails to boot from the active bank due to
951reasons like an Authentication failure, or on crossing a set number of watchdog
952resets while booting from the active bank, the platform can then switch to boot
953from a different bank. This function then returns the bank that the platform
954should boot its images from.
955
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100956Common optional modifications
957-----------------------------
958
959The following are helper functions implemented by the firmware that perform
960common platform-specific tasks. A platform may choose to override these
961definitions.
962
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100963Function : plat_set_my_stack()
964~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100965
966::
967
968 Argument : void
969 Return : void
970
971This function sets the current stack pointer to the normal memory stack that
972has been allocated for the current CPU. For BL images that only require a
973stack for the primary CPU, the UP version of the function is used. The size
974of the stack allocated to each CPU is specified by the platform defined
975constant ``PLATFORM_STACK_SIZE``.
976
977Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +0100978provided in ``plat/common/aarch64/platform_up_stack.S`` and
979``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100980
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100981Function : plat_get_my_stack()
982~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100983
984::
985
986 Argument : void
987 Return : uintptr_t
988
989This function returns the base address of the normal memory stack that
990has been allocated for the current CPU. For BL images that only require a
991stack for the primary CPU, the UP version of the function is used. The size
992of the stack allocated to each CPU is specified by the platform defined
993constant ``PLATFORM_STACK_SIZE``.
994
995Common implementations of this function for the UP and MP BL images are
Paul Beesleyf8640672019-04-12 14:19:42 +0100996provided in ``plat/common/aarch64/platform_up_stack.S`` and
997``plat/common/aarch64/platform_mp_stack.S``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100998
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100999Function : plat_report_exception()
1000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001001
1002::
1003
1004 Argument : unsigned int
1005 Return : void
1006
1007A platform may need to report various information about its status when an
1008exception is taken, for example the current exception level, the CPU security
1009state (secure/non-secure), the exception type, and so on. This function is
1010called in the following circumstances:
1011
1012- In BL1, whenever an exception is taken.
1013- In BL2, whenever an exception is taken.
1014
1015The default implementation doesn't do anything, to avoid making assumptions
1016about the way the platform displays its status information.
1017
1018For AArch64, this function receives the exception type as its argument.
1019Possible values for exceptions types are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001020``include/common/bl_common.h`` header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +00001021related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001022
1023For AArch32, this function receives the exception mode as its argument.
1024Possible values for exception modes are listed in the
Paul Beesleyf8640672019-04-12 14:19:42 +01001025``include/lib/aarch32/arch.h`` header file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001026
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001027Function : plat_reset_handler()
1028~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001029
1030::
1031
1032 Argument : void
1033 Return : void
1034
1035A platform may need to do additional initialization after reset. This function
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001036allows the platform to do the platform specific initializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001037specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001038preserve the values of callee saved registers x19 to x29.
1039
1040The default implementation doesn't do anything. If a platform needs to override
Paul Beesleyf8640672019-04-12 14:19:42 +01001041the default implementation, refer to the :ref:`Firmware Design` for general
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001042guidelines.
1043
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001044Function : plat_disable_acp()
1045~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001046
1047::
1048
1049 Argument : void
1050 Return : void
1051
John Tsichritzis6dda9762018-07-23 09:18:04 +01001052This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001053present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +01001054doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001055it has restrictions for stack usage and it can use the registers x0 - x17 as
1056scratch registers. It should preserve the value in x18 register as it is used
1057by the caller to store the return address.
1058
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001059Function : plat_error_handler()
1060~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001061
1062::
1063
1064 Argument : int
1065 Return : void
1066
1067This API is called when the generic code encounters an error situation from
1068which it cannot continue. It allows the platform to perform error reporting or
1069recovery actions (for example, reset the system). This function must not return.
1070
1071The parameter indicates the type of error using standard codes from ``errno.h``.
1072Possible errors reported by the generic code are:
1073
1074- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
1075 Board Boot is enabled)
1076- ``-ENOENT``: the requested image or certificate could not be found or an IO
1077 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +00001078- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
1079 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001080
1081The default implementation simply spins.
1082
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001083Function : plat_panic_handler()
1084~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001085
1086::
1087
1088 Argument : void
1089 Return : void
1090
1091This API is called when the generic code encounters an unexpected error
1092situation from which it cannot recover. This function must not return,
1093and must be implemented in assembly because it may be called before the C
1094environment is initialized.
1095
Paul Beesleyba3ed402019-03-13 16:20:44 +00001096.. note::
1097 The address from where it was called is stored in x30 (Link Register).
1098 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001099
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001100Function : plat_get_bl_image_load_info()
1101~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001102
1103::
1104
1105 Argument : void
1106 Return : bl_load_info_t *
1107
1108This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001109populated to load. This function is invoked in BL2 to load the
1110BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001111
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001112Function : plat_get_next_bl_params()
1113~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001114
1115::
1116
1117 Argument : void
1118 Return : bl_params_t *
1119
1120This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001121kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001122function is invoked in BL2 to pass this information to the next BL
1123image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001124
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001125Function : plat_get_stack_protector_canary()
1126~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001127
1128::
1129
1130 Argument : void
1131 Return : u_register_t
1132
1133This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001134when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001135value will weaken the protection as the attacker could easily write the right
1136value as part of the attack most of the time. Therefore, it should return a
1137true random number.
1138
Paul Beesleyba3ed402019-03-13 16:20:44 +00001139.. warning::
1140 For the protection to be effective, the global data need to be placed at
1141 a lower address than the stack bases. Failure to do so would allow an
1142 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001143
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001144Function : plat_flush_next_bl_params()
1145~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001146
1147::
1148
1149 Argument : void
1150 Return : void
1151
1152This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001153next image. This function is invoked in BL2 to flush this information
1154to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001155
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001156Function : plat_log_get_prefix()
1157~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001158
1159::
1160
1161 Argument : unsigned int
1162 Return : const char *
1163
1164This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001165prepended to all the log output from TF-A. The `log_level` (argument) will
1166correspond to one of the standard log levels defined in debug.h. The platform
1167can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001168the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001169increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001170
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001171Function : plat_get_soc_version()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001172~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001173
1174::
1175
1176 Argument : void
1177 Return : int32_t
1178
1179This function returns soc version which mainly consist of below fields
1180
1181::
1182
1183 soc_version[30:24] = JEP-106 continuation code for the SiP
1184 soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001185 soc_version[15:0] = Implementation defined SoC ID
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001186
1187Function : plat_get_soc_revision()
Manish V Badarkhe904f93a2020-03-26 14:20:27 +00001188~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Manish V Badarkhef809c6e2020-02-22 08:43:00 +00001189
1190::
1191
1192 Argument : void
1193 Return : int32_t
1194
1195This function returns soc revision in below format
1196
1197::
1198
1199 soc_revision[0:30] = SOC revision of specific SOC
1200
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +01001201Function : plat_is_smccc_feature_available()
1202~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1203
1204::
1205
1206 Argument : u_register_t
1207 Return : int32_t
1208
1209This function returns SMC_ARCH_CALL_SUCCESS if the platform supports
1210the SMCCC function specified in the argument; otherwise returns
1211SMC_ARCH_CALL_NOT_SUPPORTED.
1212
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001213Function : plat_mboot_measure_image()
1214~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1215
1216::
1217
1218 Argument : unsigned int, image_info_t *
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001219 Return : int
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001220
1221When the MEASURED_BOOT flag is enabled:
1222
1223- This function measures the given image and records its measurement using
1224 the measured boot backend driver.
1225- On the Arm FVP port, this function measures the given image using its
1226 passed id and information and then records that measurement in the
1227 Event Log buffer.
Manish V Badarkhe931c6ef2021-10-21 09:06:18 +01001228- This function must return 0 on success, a signed integer error code
1229 otherwise.
1230
1231When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1232
1233Function : plat_mboot_measure_critical_data()
1234~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1235
1236::
1237
1238 Argument : unsigned int, const void *, size_t
1239 Return : int
1240
1241When the MEASURED_BOOT flag is enabled:
1242
1243- This function measures the given critical data structure and records its
1244 measurement using the measured boot backend driver.
1245- This function must return 0 on success, a signed integer error code
1246 otherwise.
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001247
1248When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1249
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001250Modifications specific to a Boot Loader stage
1251---------------------------------------------
1252
1253Boot Loader Stage 1 (BL1)
1254-------------------------
1255
1256BL1 implements the reset vector where execution starts from after a cold or
1257warm boot. For each CPU, BL1 is responsible for the following tasks:
1258
1259#. Handling the reset as described in section 2.2
1260
1261#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1262 only this CPU executes the remaining BL1 code, including loading and passing
1263 control to the BL2 stage.
1264
1265#. Identifying and starting the Firmware Update process (if required).
1266
1267#. Loading the BL2 image from non-volatile storage into secure memory at the
1268 address specified by the platform defined constant ``BL2_BASE``.
1269
1270#. Populating a ``meminfo`` structure with the following information in memory,
1271 accessible by BL2 immediately upon entry.
1272
1273 ::
1274
1275 meminfo.total_base = Base address of secure RAM visible to BL2
1276 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001277
Soby Mathew97b1bff2018-09-27 16:46:41 +01001278 By default, BL1 places this ``meminfo`` structure at the end of secure
1279 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001280
Soby Mathewb1bf0442018-02-16 14:52:52 +00001281 It is possible for the platform to decide where it wants to place the
1282 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1283 BL2 by overriding the weak default implementation of
1284 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001285
1286The following functions need to be implemented by the platform port to enable
1287BL1 to perform the above tasks.
1288
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001289Function : bl1_early_platform_setup() [mandatory]
1290~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001291
1292::
1293
1294 Argument : void
1295 Return : void
1296
1297This function executes with the MMU and data caches disabled. It is only called
1298by the primary CPU.
1299
Dan Handley610e7e12018-03-01 18:44:00 +00001300On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001301
1302- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1303
1304- Initializes a UART (PL011 console), which enables access to the ``printf``
1305 family of functions in BL1.
1306
1307- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1308 the CCI slave interface corresponding to the cluster that includes the
1309 primary CPU.
1310
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001311Function : bl1_plat_arch_setup() [mandatory]
1312~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001313
1314::
1315
1316 Argument : void
1317 Return : void
1318
1319This function performs any platform-specific and architectural setup that the
1320platform requires. Platform-specific setup might include configuration of
1321memory controllers and the interconnect.
1322
Dan Handley610e7e12018-03-01 18:44:00 +00001323In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001324
1325This function helps fulfill requirement 2 above.
1326
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001327Function : bl1_platform_setup() [mandatory]
1328~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001329
1330::
1331
1332 Argument : void
1333 Return : void
1334
1335This function executes with the MMU and data caches enabled. It is responsible
1336for performing any remaining platform-specific setup that can occur after the
1337MMU and data cache have been enabled.
1338
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001339if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001340sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001341
Dan Handley610e7e12018-03-01 18:44:00 +00001342In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001343layer used to load the next bootloader image.
1344
1345This function helps fulfill requirement 4 above.
1346
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001347Function : bl1_plat_sec_mem_layout() [mandatory]
1348~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001349
1350::
1351
1352 Argument : void
1353 Return : meminfo *
1354
1355This function should only be called on the cold boot path. It executes with the
1356MMU and data caches enabled. The pointer returned by this function must point to
1357a ``meminfo`` structure containing the extents and availability of secure RAM for
1358the BL1 stage.
1359
1360::
1361
1362 meminfo.total_base = Base address of secure RAM visible to BL1
1363 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001364
1365This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1366populates a similar structure to tell BL2 the extents of memory available for
1367its own use.
1368
1369This function helps fulfill requirements 4 and 5 above.
1370
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001371Function : bl1_plat_prepare_exit() [optional]
1372~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001373
1374::
1375
1376 Argument : entry_point_info_t *
1377 Return : void
1378
1379This function is called prior to exiting BL1 in response to the
1380``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1381platform specific clean up or bookkeeping operations before transferring
1382control to the next image. It receives the address of the ``entry_point_info_t``
1383structure passed from BL2. This function runs with MMU disabled.
1384
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001385Function : bl1_plat_set_ep_info() [optional]
1386~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001387
1388::
1389
1390 Argument : unsigned int image_id, entry_point_info_t *ep_info
1391 Return : void
1392
1393This function allows platforms to override ``ep_info`` for the given ``image_id``.
1394
1395The default implementation just returns.
1396
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001397Function : bl1_plat_get_next_image_id() [optional]
1398~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001399
1400::
1401
1402 Argument : void
1403 Return : unsigned int
1404
1405This and the following function must be overridden to enable the FWU feature.
1406
1407BL1 calls this function after platform setup to identify the next image to be
1408loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1409with the normal boot sequence, which loads and executes BL2. If the platform
1410returns a different image id, BL1 assumes that Firmware Update is required.
1411
Dan Handley610e7e12018-03-01 18:44:00 +00001412The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001413platforms override this function to detect if firmware update is required, and
1414if so, return the first image in the firmware update process.
1415
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001416Function : bl1_plat_get_image_desc() [optional]
1417~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001418
1419::
1420
1421 Argument : unsigned int image_id
1422 Return : image_desc_t *
1423
1424BL1 calls this function to get the image descriptor information ``image_desc_t``
1425for the provided ``image_id`` from the platform.
1426
Dan Handley610e7e12018-03-01 18:44:00 +00001427The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001428standard platforms return an image descriptor corresponding to BL2 or one of
1429the firmware update images defined in the Trusted Board Boot Requirements
1430specification.
1431
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001432Function : bl1_plat_handle_pre_image_load() [optional]
1433~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001434
1435::
1436
Soby Mathew2f38ce32018-02-08 17:45:12 +00001437 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001438 Return : int
1439
1440This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001441corresponding to ``image_id``. This function is invoked in BL1, both in cold
1442boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001443
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001444Function : bl1_plat_handle_post_image_load() [optional]
1445~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001446
1447::
1448
Soby Mathew2f38ce32018-02-08 17:45:12 +00001449 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001450 Return : int
1451
1452This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001453corresponding to ``image_id``. This function is invoked in BL1, both in cold
1454boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001455
Soby Mathewb1bf0442018-02-16 14:52:52 +00001456The default weak implementation of this function calculates the amount of
1457Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1458structure at the beginning of this free memory and populates it. The address
1459of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1460information to BL2.
1461
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001462Function : bl1_plat_fwu_done() [optional]
1463~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001464
1465::
1466
1467 Argument : unsigned int image_id, uintptr_t image_src,
1468 unsigned int image_size
1469 Return : void
1470
1471BL1 calls this function when the FWU process is complete. It must not return.
1472The platform may override this function to take platform specific action, for
1473example to initiate the normal boot flow.
1474
1475The default implementation spins forever.
1476
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001477Function : bl1_plat_mem_check() [mandatory]
1478~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001479
1480::
1481
1482 Argument : uintptr_t mem_base, unsigned int mem_size,
1483 unsigned int flags
1484 Return : int
1485
1486BL1 calls this function while handling FWU related SMCs, more specifically when
1487copying or authenticating an image. Its responsibility is to ensure that the
1488region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1489that this memory corresponds to either a secure or non-secure memory region as
1490indicated by the security state of the ``flags`` argument.
1491
1492This function can safely assume that the value resulting from the addition of
1493``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1494overflow.
1495
1496This function must return 0 on success, a non-null error code otherwise.
1497
1498The default implementation of this function asserts therefore platforms must
1499override it when using the FWU feature.
1500
Manish V Badarkhebd617b92021-09-20 15:19:59 +01001501Function : bl1_plat_mboot_init() [optional]
1502~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1503
1504::
1505
1506 Argument : void
1507 Return : void
1508
1509When the MEASURED_BOOT flag is enabled:
1510
1511- This function is used to initialize the backend driver(s) of measured boot.
1512- On the Arm FVP port, this function is used to initialize the Event Log
1513 backend driver, and also to write header information in the Event Log buffer.
1514
1515When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1516
1517Function : bl1_plat_mboot_finish() [optional]
1518~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1519
1520::
1521
1522 Argument : void
1523 Return : void
1524
1525When the MEASURED_BOOT flag is enabled:
1526
1527- This function is used to finalize the measured boot backend driver(s),
1528 and also, set the information for the next bootloader component to
1529 extend the measurement if needed.
1530- On the Arm FVP port, this function is used to pass the base address of
1531 the Event Log buffer and its size to BL2 via tb_fw_config to extend the
1532 Event Log buffer with the measurement of various images loaded by BL2.
1533 It results in panic on error.
1534
1535When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1536
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001537Boot Loader Stage 2 (BL2)
1538-------------------------
1539
1540The BL2 stage is executed only by the primary CPU, which is determined in BL1
1541using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001542``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1543``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1544non-volatile storage to secure/non-secure RAM. After all the images are loaded
1545then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1546images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001547
1548The following functions must be implemented by the platform port to enable BL2
1549to perform the above tasks.
1550
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001551Function : bl2_early_platform_setup2() [mandatory]
1552~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001553
1554::
1555
Soby Mathew97b1bff2018-09-27 16:46:41 +01001556 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001557 Return : void
1558
1559This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001560by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1561are platform specific.
1562
1563On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001564
Manish V Badarkhe81414512020-06-24 15:58:38 +01001565 arg0 - Points to load address of FW_CONFIG
Soby Mathew97b1bff2018-09-27 16:46:41 +01001566
1567 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1568 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001569
Dan Handley610e7e12018-03-01 18:44:00 +00001570On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001571
1572- Initializes a UART (PL011 console), which enables access to the ``printf``
1573 family of functions in BL2.
1574
1575- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001576 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1577 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001578
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001579Function : bl2_plat_arch_setup() [mandatory]
1580~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001581
1582::
1583
1584 Argument : void
1585 Return : void
1586
1587This function executes with the MMU and data caches disabled. It is only called
1588by the primary CPU.
1589
1590The purpose of this function is to perform any architectural initialization
1591that varies across platforms.
1592
Dan Handley610e7e12018-03-01 18:44:00 +00001593On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001594
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001595Function : bl2_platform_setup() [mandatory]
1596~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001597
1598::
1599
1600 Argument : void
1601 Return : void
1602
1603This function may execute with the MMU and data caches enabled if the platform
1604port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1605called by the primary CPU.
1606
1607The purpose of this function is to perform any platform initialization
1608specific to BL2.
1609
Dan Handley610e7e12018-03-01 18:44:00 +00001610In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001611configuration of the TrustZone controller to allow non-secure masters access
1612to most of DRAM. Part of DRAM is reserved for secure world use.
1613
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001614Function : bl2_plat_handle_pre_image_load() [optional]
1615~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616
1617::
1618
1619 Argument : unsigned int
1620 Return : int
1621
1622This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001623for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001624loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001625
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001626Function : bl2_plat_handle_post_image_load() [optional]
1627~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001628
1629::
1630
1631 Argument : unsigned int
1632 Return : int
1633
1634This function can be used by the platforms to update/use image information
1635for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001636loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001637
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001638Function : bl2_plat_preload_setup [optional]
1639~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001640
1641::
John Tsichritzisee10e792018-06-06 09:38:10 +01001642
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001643 Argument : void
1644 Return : void
1645
1646This optional function performs any BL2 platform initialization
1647required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001648bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001649boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001650plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001651
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001652Function : plat_try_next_boot_source() [optional]
1653~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001654
1655::
John Tsichritzisee10e792018-06-06 09:38:10 +01001656
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001657 Argument : void
1658 Return : int
1659
1660This optional function passes to the next boot source in the redundancy
1661sequence.
1662
1663This function moves the current boot redundancy source to the next
1664element in the boot sequence. If there are no more boot sources then it
1665must return 0, otherwise it must return 1. The default implementation
1666of this always returns 0.
1667
Sandrine Bailleuxeb5fadc2022-07-13 10:07:54 +02001668Function : bl2_plat_mboot_init() [optional]
1669~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1670
1671::
1672
1673 Argument : void
1674 Return : void
1675
1676When the MEASURED_BOOT flag is enabled:
1677
1678- This function is used to initialize the backend driver(s) of measured boot.
1679- On the Arm FVP port, this function is used to initialize the Event Log
1680 backend driver with the Event Log buffer information (base address and
1681 size) received from BL1. It results in panic on error.
1682
1683When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1684
1685Function : bl2_plat_mboot_finish() [optional]
1686~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1687
1688::
1689
1690 Argument : void
1691 Return : void
1692
1693When the MEASURED_BOOT flag is enabled:
1694
1695- This function is used to finalize the measured boot backend driver(s),
1696 and also, set the information for the next bootloader component to extend
1697 the measurement if needed.
1698- On the Arm FVP port, this function is used to pass the Event Log buffer
1699 information (base address and size) to non-secure(BL33) and trusted OS(BL32)
1700 via nt_fw and tos_fw config respectively. It results in panic on error.
1701
1702When the MEASURED_BOOT flag is disabled, this function doesn't do anything.
1703
Roberto Vargasb1584272017-11-20 13:36:10 +00001704Boot Loader Stage 2 (BL2) at EL3
1705--------------------------------
1706
Dan Handley610e7e12018-03-01 18:44:00 +00001707When the platform has a non-TF-A Boot ROM it is desirable to jump
1708directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Paul Beesleyf8640672019-04-12 14:19:42 +01001709execute at EL3 instead of executing at EL1. Refer to the :ref:`Firmware Design`
1710document for more information.
Roberto Vargasb1584272017-11-20 13:36:10 +00001711
1712All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001713bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1714their work is done now by bl2_el3_early_platform_setup and
1715bl2_el3_plat_arch_setup. These functions should generally implement
1716the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001717
1718
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001719Function : bl2_el3_early_platform_setup() [mandatory]
1720~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001721
1722::
John Tsichritzisee10e792018-06-06 09:38:10 +01001723
Roberto Vargasb1584272017-11-20 13:36:10 +00001724 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1725 Return : void
1726
1727This function executes with the MMU and data caches disabled. It is only called
1728by the primary CPU. This function receives four parameters which can be used
1729by the platform to pass any needed information from the Boot ROM to BL2.
1730
Dan Handley610e7e12018-03-01 18:44:00 +00001731On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001732
1733- Initializes a UART (PL011 console), which enables access to the ``printf``
1734 family of functions in BL2.
1735
1736- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001737 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1738 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001739
1740- Initializes the private variables that define the memory layout used.
1741
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001742Function : bl2_el3_plat_arch_setup() [mandatory]
1743~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001744
1745::
John Tsichritzisee10e792018-06-06 09:38:10 +01001746
Roberto Vargasb1584272017-11-20 13:36:10 +00001747 Argument : void
1748 Return : void
1749
1750This function executes with the MMU and data caches disabled. It is only called
1751by the primary CPU.
1752
1753The purpose of this function is to perform any architectural initialization
1754that varies across platforms.
1755
Dan Handley610e7e12018-03-01 18:44:00 +00001756On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00001757
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001758Function : bl2_el3_plat_prepare_exit() [optional]
1759~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001760
1761::
John Tsichritzisee10e792018-06-06 09:38:10 +01001762
Roberto Vargasb1584272017-11-20 13:36:10 +00001763 Argument : void
1764 Return : void
1765
1766This function is called prior to exiting BL2 and run the next image.
1767It should be used to perform platform specific clean up or bookkeeping
1768operations before transferring control to the next image. This function
1769runs with MMU disabled.
1770
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771FWU Boot Loader Stage 2 (BL2U)
1772------------------------------
1773
1774The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1775process and is executed only by the primary CPU. BL1 passes control to BL2U at
1776``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1777
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001778#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1779 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1780 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1781 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001782 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1783 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1784
1785#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00001786 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001787 normal world can access DDR memory.
1788
1789The following functions must be implemented by the platform port to enable
1790BL2U to perform the tasks mentioned above.
1791
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001792Function : bl2u_early_platform_setup() [mandatory]
1793~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001794
1795::
1796
1797 Argument : meminfo *mem_info, void *plat_info
1798 Return : void
1799
1800This function executes with the MMU and data caches disabled. It is only
1801called by the primary CPU. The arguments to this function is the address
1802of the ``meminfo`` structure and platform specific info provided by BL1.
1803
1804The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
1805private storage as the original memory may be subsequently overwritten by BL2U.
1806
Dan Handley610e7e12018-03-01 18:44:00 +00001807On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001808to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001809variable.
1810
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001811Function : bl2u_plat_arch_setup() [mandatory]
1812~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001813
1814::
1815
1816 Argument : void
1817 Return : void
1818
1819This function executes with the MMU and data caches disabled. It is only
1820called by the primary CPU.
1821
1822The purpose of this function is to perform any architectural initialization
1823that varies across platforms, for example enabling the MMU (since the memory
1824map differs across platforms).
1825
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001826Function : bl2u_platform_setup() [mandatory]
1827~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001828
1829::
1830
1831 Argument : void
1832 Return : void
1833
1834This function may execute with the MMU and data caches enabled if the platform
1835port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
1836called by the primary CPU.
1837
1838The purpose of this function is to perform any platform initialization
1839specific to BL2U.
1840
Dan Handley610e7e12018-03-01 18:44:00 +00001841In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001842configuration of the TrustZone controller to allow non-secure masters access
1843to most of DRAM. Part of DRAM is reserved for secure world use.
1844
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001845Function : bl2u_plat_handle_scp_bl2u() [optional]
1846~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001847
1848::
1849
1850 Argument : void
1851 Return : int
1852
1853This function is used to perform any platform-specific actions required to
1854handle the SCP firmware. Typically it transfers the image into SCP memory using
1855a platform-specific protocol and waits until SCP executes it and signals to the
1856Application Processor (AP) for BL2U execution to continue.
1857
1858This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001859This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001860
1861Boot Loader Stage 3-1 (BL31)
1862----------------------------
1863
1864During cold boot, the BL31 stage is executed only by the primary CPU. This is
1865determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
1866control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
1867CPUs. BL31 executes at EL3 and is responsible for:
1868
1869#. Re-initializing all architectural and platform state. Although BL1 performs
1870 some of this initialization, BL31 remains resident in EL3 and must ensure
1871 that EL3 architectural and platform state is completely initialized. It
1872 should make no assumptions about the system state when it receives control.
1873
1874#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01001875 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
1876 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001877
1878#. Providing runtime firmware services. Currently, BL31 only implements a
1879 subset of the Power State Coordination Interface (PSCI) API as a runtime
1880 service. See Section 3.3 below for details of porting the PSCI
1881 implementation.
1882
1883#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001884 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001885 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01001886 executed and run the corresponding image. On ARM platforms, BL31 uses the
1887 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001888
1889If BL31 is a reset vector, It also needs to handle the reset as specified in
1890section 2.2 before the tasks described above.
1891
1892The following functions must be implemented by the platform port to enable BL31
1893to perform the above tasks.
1894
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001895Function : bl31_early_platform_setup2() [mandatory]
1896~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001897
1898::
1899
Soby Mathew97b1bff2018-09-27 16:46:41 +01001900 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001901 Return : void
1902
1903This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001904by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
1905platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001906
Soby Mathew97b1bff2018-09-27 16:46:41 +01001907In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001908
Soby Mathew97b1bff2018-09-27 16:46:41 +01001909 arg0 - The pointer to the head of `bl_params_t` list
1910 which is list of executable images following BL31,
1911
1912 arg1 - Points to load address of SOC_FW_CONFIG if present
Mikael Olsson0232da22021-02-12 17:30:16 +01001913 except in case of Arm FVP and Juno platform.
Manish V Badarkhe81414512020-06-24 15:58:38 +01001914
Mikael Olsson0232da22021-02-12 17:30:16 +01001915 In case of Arm FVP and Juno platform, points to load address
Manish V Badarkhe81414512020-06-24 15:58:38 +01001916 of FW_CONFIG.
Soby Mathew97b1bff2018-09-27 16:46:41 +01001917
1918 arg2 - Points to load address of HW_CONFIG if present
1919
1920 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
1921 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001922
Soby Mathew97b1bff2018-09-27 16:46:41 +01001923The function runs through the `bl_param_t` list and extracts the entry point
1924information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001925
1926- Initialize a UART (PL011 console), which enables access to the ``printf``
1927 family of functions in BL31.
1928
1929- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
1930 CCI slave interface corresponding to the cluster that includes the primary
1931 CPU.
1932
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001933Function : bl31_plat_arch_setup() [mandatory]
1934~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001935
1936::
1937
1938 Argument : void
1939 Return : void
1940
1941This function executes with the MMU and data caches disabled. It is only called
1942by the primary CPU.
1943
1944The purpose of this function is to perform any architectural initialization
1945that varies across platforms.
1946
Dan Handley610e7e12018-03-01 18:44:00 +00001947On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001948
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001949Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001950~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1951
1952::
1953
1954 Argument : void
1955 Return : void
1956
1957This function may execute with the MMU and data caches enabled if the platform
1958port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
1959called by the primary CPU.
1960
1961The purpose of this function is to complete platform initialization so that both
1962BL31 runtime services and normal world software can function correctly.
1963
Dan Handley610e7e12018-03-01 18:44:00 +00001964On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001965
1966- Initialize the generic interrupt controller.
1967
1968 Depending on the GIC driver selected by the platform, the appropriate GICv2
1969 or GICv3 initialization will be done, which mainly consists of:
1970
1971 - Enable secure interrupts in the GIC CPU interface.
1972 - Disable the legacy interrupt bypass mechanism.
1973 - Configure the priority mask register to allow interrupts of all priorities
1974 to be signaled to the CPU interface.
1975 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
1976 - Target all secure SPIs to CPU0.
1977 - Enable these secure interrupts in the GIC distributor.
1978 - Configure all other interrupts as non-secure.
1979 - Enable signaling of secure interrupts in the GIC distributor.
1980
1981- Enable system-level implementation of the generic timer counter through the
1982 memory mapped interface.
1983
1984- Grant access to the system counter timer module
1985
1986- Initialize the power controller device.
1987
1988 In particular, initialise the locks that prevent concurrent accesses to the
1989 power controller device.
1990
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001991Function : bl31_plat_runtime_setup() [optional]
1992~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001993
1994::
1995
1996 Argument : void
1997 Return : void
1998
1999The purpose of this function is allow the platform to perform any BL31 runtime
2000setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07002001implementation of this function will invoke ``console_switch_state()`` to switch
2002console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002003
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002004Function : bl31_plat_get_next_image_ep_info() [mandatory]
2005~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002006
2007::
2008
Sandrine Bailleux842117d2018-05-14 14:25:47 +02002009 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002010 Return : entry_point_info *
2011
2012This function may execute with the MMU and data caches enabled if the platform
2013port does the necessary initializations in ``bl31_plat_arch_setup()``.
2014
2015This function is called by ``bl31_main()`` to retrieve information provided by
2016BL2 for the next image in the security state specified by the argument. BL31
2017uses this information to pass control to that image in the specified security
2018state. This function must return a pointer to the ``entry_point_info`` structure
2019(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
2020should return NULL otherwise.
2021
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002022Function : plat_rmmd_get_cca_attest_token() [mandatory when ENABLE_RME == 1]
Soby Mathew294e1cf2022-03-22 16:19:39 +00002023~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2024
2025::
2026
2027 Argument : uintptr_t, size_t *, uintptr_t, size_t
2028 Return : int
2029
2030This function returns the Platform attestation token.
2031
2032The parameters of the function are:
2033
2034 arg0 - A pointer to the buffer where the Platform token should be copied by
2035 this function. The buffer must be big enough to hold the Platform
2036 token.
2037
2038 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2039 function returns the platform token length in this parameter.
2040
2041 arg2 - A pointer to the buffer where the challenge object is stored.
2042
2043 arg3 - The length of the challenge object in bytes. Possible values are 32,
2044 48 and 64.
2045
2046The function returns 0 on success, -EINVAL on failure.
2047
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002048Function : plat_rmmd_get_cca_realm_attest_key() [mandatory when ENABLE_RME == 1]
2049~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewf05d93a2022-03-22 16:21:19 +00002050
2051::
2052
2053 Argument : uintptr_t, size_t *, unsigned int
2054 Return : int
2055
2056This function returns the delegated realm attestation key which will be used to
2057sign Realm attestation token. The API currently only supports P-384 ECC curve
2058key.
2059
2060The parameters of the function are:
2061
2062 arg0 - A pointer to the buffer where the attestation key should be copied
2063 by this function. The buffer must be big enough to hold the
2064 attestation key.
2065
2066 arg1 - Contains the size (in bytes) of the buffer passed in arg0. The
2067 function returns the attestation key length in this parameter.
2068
2069 arg2 - The type of the elliptic curve to which the requested attestation key
2070 belongs.
2071
2072The function returns 0 on success, -EINVAL on failure.
2073
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +00002074Function : plat_rmmd_get_el3_rmm_shared_mem() [when ENABLE_RME == 1]
2075~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2076
2077::
2078
2079 Argument : uintptr_t *
2080 Return : size_t
2081
2082This function returns the size of the shared area between EL3 and RMM (or 0 on
2083failure). A pointer to the shared area (or a NULL pointer on failure) is stored
2084in the pointer passed as argument.
2085
Javier Almansa Sobrino4165e842022-04-25 17:18:15 +01002086Function : plat_rmmd_load_manifest() [when ENABLE_RME == 1]
2087~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2088
2089::
2090
2091 Arguments : rmm_manifest_t *manifest
2092 Return : int
2093
2094When ENABLE_RME is enabled, this function populates a boot manifest for the
2095RMM image and stores it in the area specified by manifest.
2096
2097When ENABLE_RME is disabled, this function is not used.
2098
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002099Function : bl31_plat_enable_mmu [optional]
2100~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2101
2102::
2103
2104 Argument : uint32_t
2105 Return : void
2106
2107This function enables the MMU. The boot code calls this function with MMU and
2108caches disabled. This function should program necessary registers to enable
2109translation, and upon return, the MMU on the calling PE must be enabled.
2110
2111The function must honor flags passed in the first argument. These flags are
2112defined by the translation library, and can be found in the file
2113``include/lib/xlat_tables/xlat_mmu_helpers.h``.
2114
2115On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002116is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01002117
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002118Function : plat_init_apkey [optional]
2119~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002120
2121::
2122
2123 Argument : void
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002124 Return : uint128_t
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002125
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002126This function returns the 128-bit value which can be used to program ARMv8.3
2127pointer authentication keys.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002128
2129The value should be obtained from a reliable source of randomness.
2130
2131This function is only needed if ARMv8.3 pointer authentication is used in the
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002132Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002133
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002134Function : plat_get_syscnt_freq2() [mandatory]
2135~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002136
2137::
2138
2139 Argument : void
2140 Return : unsigned int
2141
2142This function is used by the architecture setup code to retrieve the counter
2143frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00002144``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002145of the system counter, which is retrieved from the first entry in the frequency
2146modes table.
2147
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002148#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
2149~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002150
2151When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
2152bytes) aligned to the cache line boundary that should be allocated per-cpu to
2153accommodate all the bakery locks.
2154
2155If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
2156calculates the size of the ``bakery_lock`` input section, aligns it to the
2157nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
2158and stores the result in a linker symbol. This constant prevents a platform
2159from relying on the linker and provide a more efficient mechanism for
2160accessing per-cpu bakery lock information.
2161
2162If this constant is defined and its value is not equal to the value
2163calculated by the linker then a link time assertion is raised. A compile time
2164assertion is raised if the value of the constant is not aligned to the cache
2165line boundary.
2166
Paul Beesleyf8640672019-04-12 14:19:42 +01002167.. _porting_guide_sdei_requirements:
2168
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002169SDEI porting requirements
2170~~~~~~~~~~~~~~~~~~~~~~~~~
2171
Paul Beesley606d8072019-03-13 13:58:02 +00002172The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002173and functions, of which some are optional, and some others mandatory.
2174
2175Macros
2176......
2177
2178Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
2179^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2180
2181This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002182Normal |SDEI| events on the platform. This must have a higher value
2183(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002184
2185Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
2186^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2187
2188This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00002189Critical |SDEI| events on the platform. This must have a lower value
2190(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002191
Paul Beesley606d8072019-03-13 13:58:02 +00002192**Note**: |SDEI| exception priorities must be the lowest among Secure
2193priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2194be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002195
2196Functions
2197.........
2198
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002199Function: int plat_sdei_validate_entry_point() [optional]
2200^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002201
2202::
2203
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002204 Argument: uintptr_t ep, unsigned int client_mode
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002205 Return: int
2206
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002207This function validates the entry point address of the event handler provided by
2208the client for both event registration and *Complete and Resume* |SDEI| calls.
2209The function ensures that the address is valid in the client translation regime.
2210
2211The second argument is the exception level that the client is executing in. It
2212can be Non-Secure EL1 or Non-Secure EL2.
2213
2214The function must return ``0`` for successful validation, or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002215
Dan Handley610e7e12018-03-01 18:44:00 +00002216The default implementation always returns ``0``. On Arm platforms, this function
Sandrine Bailleux95db98b2020-05-15 12:05:51 +02002217translates the entry point address within the client translation regime and
2218further ensures that the resulting physical address is located in Non-secure
2219DRAM.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002220
2221Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
2222^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2223
2224::
2225
2226 Argument: uint64_t
2227 Argument: unsigned int
2228 Return: void
2229
Paul Beesley606d8072019-03-13 13:58:02 +00002230|SDEI| specification requires that a PE comes out of reset with the events
2231masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
2232|SDEI| events on the PE. No |SDEI| events can be dispatched until such
2233time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002234
Paul Beesley606d8072019-03-13 13:58:02 +00002235Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01002236events are masked on the PE, the dispatcher implementation invokes the function
2237``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2238interrupt and the interrupt ID are passed as parameters.
2239
2240The default implementation only prints out a warning message.
2241
Jimmy Brisson26c5b5c2020-06-22 14:18:42 -05002242.. _porting_guide_trng_requirements:
2243
2244TRNG porting requirements
2245~~~~~~~~~~~~~~~~~~~~~~~~~
2246
2247The |TRNG| backend requires the platform to provide the following values
2248and mandatory functions.
2249
2250Values
2251......
2252
2253value: uuid_t plat_trng_uuid [mandatory]
2254^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2255
2256This value must be defined to the UUID of the TRNG backend that is specific to
2257the hardware after ``plat_trng_setup`` function is called. This value must
2258conform to the SMCCC calling convention; The most significant 32 bits of the
2259UUID must not equal ``0xffffffff`` or the signed integer ``-1`` as this value in
2260w0 indicates failure to get a TRNG source.
2261
2262Functions
2263.........
2264
2265Function: void plat_entropy_setup(void) [mandatory]
2266^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2267
2268::
2269
2270 Argument: none
2271 Return: none
2272
2273This function is expected to do platform-specific initialization of any TRNG
2274hardware. This may include generating a UUID from a hardware-specific seed.
2275
2276Function: bool plat_get_entropy(uint64_t \*out) [mandatory]
2277^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2278
2279::
2280
2281 Argument: uint64_t *
2282 Return: bool
2283 Out : when the return value is true, the entropy has been written into the
2284 storage pointed to
2285
2286This function writes entropy into storage provided by the caller. If no entropy
2287is available, it must return false and the storage must not be written.
2288
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002289Power State Coordination Interface (in BL31)
2290--------------------------------------------
2291
Dan Handley610e7e12018-03-01 18:44:00 +00002292The TF-A implementation of the PSCI API is based around the concept of a
2293*power domain*. A *power domain* is a CPU or a logical group of CPUs which
2294share some state on which power management operations can be performed as
2295specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
2296a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
2297*power domains* are arranged in a hierarchical tree structure and each
2298*power domain* can be identified in a system by the cpu index of any CPU that
2299is part of that domain and a *power domain level*. A processing element (for
2300example, a CPU) is at level 0. If the *power domain* node above a CPU is a
2301logical grouping of CPUs that share some state, then level 1 is that group of
2302CPUs (for example, a cluster), and level 2 is a group of clusters (for
2303example, the system). More details on the power domain topology and its
Paul Beesleyf8640672019-04-12 14:19:42 +01002304organization can be found in :ref:`PSCI Power Domain Tree Structure`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002305
2306BL31's platform initialization code exports a pointer to the platform-specific
2307power management operations required for the PSCI implementation to function
2308correctly. This information is populated in the ``plat_psci_ops`` structure. The
2309PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
2310power management operations on the power domains. For example, the target
2311CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2312handler (if present) is called for the CPU power domain.
2313
2314The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
2315describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00002316defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002317array of local power states where each index corresponds to a power domain
2318level. Each entry contains the local power state the power domain at that power
2319level could enter. It depends on the ``validate_power_state()`` handler to
2320convert the power-state parameter (possibly encoding a composite power state)
2321passed in a PSCI ``CPU_SUSPEND`` call to this representation.
2322
2323The following functions form part of platform port of PSCI functionality.
2324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002325Function : plat_psci_stat_accounting_start() [optional]
2326~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002327
2328::
2329
2330 Argument : const psci_power_state_t *
2331 Return : void
2332
2333This is an optional hook that platforms can implement for residency statistics
2334accounting before entering a low power state. The ``pwr_domain_state`` field of
2335``state_info`` (first argument) can be inspected if stat accounting is done
2336differently at CPU level versus higher levels. As an example, if the element at
2337index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2338state, special hardware logic may be programmed in order to keep track of the
2339residency statistics. For higher levels (array indices > 0), the residency
2340statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2341default implementation will use PMF to capture timestamps.
2342
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002343Function : plat_psci_stat_accounting_stop() [optional]
2344~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002345
2346::
2347
2348 Argument : const psci_power_state_t *
2349 Return : void
2350
2351This is an optional hook that platforms can implement for residency statistics
2352accounting after exiting from a low power state. The ``pwr_domain_state`` field
2353of ``state_info`` (first argument) can be inspected if stat accounting is done
2354differently at CPU level versus higher levels. As an example, if the element at
2355index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2356state, special hardware logic may be programmed in order to keep track of the
2357residency statistics. For higher levels (array indices > 0), the residency
2358statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
2359default implementation will use PMF to capture timestamps.
2360
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002361Function : plat_psci_stat_get_residency() [optional]
2362~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002363
2364::
2365
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002366 Argument : unsigned int, const psci_power_state_t *, unsigned int
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002367 Return : u_register_t
2368
2369This is an optional interface that is is invoked after resuming from a low power
2370state and provides the time spent resident in that low power state by the power
2371domain at a particular power domain level. When a CPU wakes up from suspend,
2372all its parent power domain levels are also woken up. The generic PSCI code
2373invokes this function for each parent power domain that is resumed and it
2374identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2375argument) describes the low power state that the power domain has resumed from.
2376The current CPU is the first CPU in the power domain to resume from the low
2377power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2378CPU in the power domain to suspend and may be needed to calculate the residency
2379for that power domain.
2380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002381Function : plat_get_target_pwr_state() [optional]
2382~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002383
2384::
2385
2386 Argument : unsigned int, const plat_local_state_t *, unsigned int
2387 Return : plat_local_state_t
2388
2389The PSCI generic code uses this function to let the platform participate in
2390state coordination during a power management operation. The function is passed
2391a pointer to an array of platform specific local power state ``states`` (second
2392argument) which contains the requested power state for each CPU at a particular
2393power domain level ``lvl`` (first argument) within the power domain. The function
2394is expected to traverse this array of upto ``ncpus`` (third argument) and return
2395a coordinated target power state by the comparing all the requested power
2396states. The target power state should not be deeper than any of the requested
2397power states.
2398
2399A weak definition of this API is provided by default wherein it assumes
2400that the platform assigns a local state value in order of increasing depth
2401of the power state i.e. for two power states X & Y, if X < Y
2402then X represents a shallower power state than Y. As a result, the
2403coordinated target local power state for a power domain will be the minimum
2404of the requested local power state values.
2405
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002406Function : plat_get_power_domain_tree_desc() [mandatory]
2407~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002408
2409::
2410
2411 Argument : void
2412 Return : const unsigned char *
2413
2414This function returns a pointer to the byte array containing the power domain
2415topology tree description. The format and method to construct this array are
Paul Beesleyf8640672019-04-12 14:19:42 +01002416described in :ref:`PSCI Power Domain Tree Structure`. The BL31 PSCI
2417initialization code requires this array to be described by the platform, either
2418statically or dynamically, to initialize the power domain topology tree. In case
2419the array is populated dynamically, then plat_core_pos_by_mpidr() and
2420plat_my_core_pos() should also be implemented suitably so that the topology tree
2421description matches the CPU indices returned by these APIs. These APIs together
2422form the platform interface for the PSCI topology framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002423
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002424Function : plat_setup_psci_ops() [mandatory]
2425~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002426
2427::
2428
2429 Argument : uintptr_t, const plat_psci_ops **
2430 Return : int
2431
2432This function may execute with the MMU and data caches enabled if the platform
2433port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2434called by the primary CPU.
2435
2436This function is called by PSCI initialization code. Its purpose is to let
2437the platform layer know about the warm boot entrypoint through the
2438``sec_entrypoint`` (first argument) and to export handler routines for
2439platform-specific psci power management actions by populating the passed
2440pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2441
2442A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002443the Arm FVP specific implementation of these handlers in
Paul Beesleyf8640672019-04-12 14:19:42 +01002444``plat/arm/board/fvp/fvp_pm.c`` as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002445platform wants to support, the associated operation or operations in this
2446structure must be provided and implemented (Refer section 4 of
Paul Beesleyf8640672019-04-12 14:19:42 +01002447:ref:`Firmware Design` for the PSCI API supported in TF-A). To disable a PSCI
Dan Handley610e7e12018-03-01 18:44:00 +00002448function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002449structure instead of providing an empty implementation.
2450
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002451plat_psci_ops.cpu_standby()
2452...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002453
2454Perform the platform-specific actions to enter the standby state for a cpu
2455indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002456wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002457For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2458the suspend state type specified in the ``power-state`` parameter should be
2459STANDBY and the target power domain level specified should be the CPU. The
2460handler should put the CPU into a low power retention state (usually by
2461issuing a wfi instruction) and ensure that it can be woken up from that
2462state by a normal interrupt. The generic code expects the handler to succeed.
2463
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002464plat_psci_ops.pwr_domain_on()
2465.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002466
2467Perform the platform specific actions to power on a CPU, specified
2468by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002469return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002470
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002471plat_psci_ops.pwr_domain_off()
2472..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002473
2474Perform the platform specific actions to prepare to power off the calling CPU
2475and its higher parent power domain levels as indicated by the ``target_state``
2476(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2477
2478The ``target_state`` encodes the platform coordinated target local power states
2479for the CPU power domain and its parent power domain levels. The handler
2480needs to perform power management operation corresponding to the local state
2481at each power level.
2482
2483For this handler, the local power state for the CPU power domain will be a
2484power down state where as it could be either power down, retention or run state
2485for the higher power domain levels depending on the result of state
2486coordination. The generic code expects the handler to succeed.
2487
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002488plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2489...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002490
2491This optional function may be used as a performance optimization to replace
2492or complement pwr_domain_suspend() on some platforms. Its calling semantics
2493are identical to pwr_domain_suspend(), except the PSCI implementation only
2494calls this function when suspending to a power down state, and it guarantees
2495that data caches are enabled.
2496
2497When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2498before calling pwr_domain_suspend(). If the target_state corresponds to a
2499power down state and it is safe to perform some or all of the platform
2500specific actions in that function with data caches enabled, it may be more
2501efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2502= 1, data caches remain enabled throughout, and so there is no advantage to
2503moving platform specific actions to this function.
2504
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002505plat_psci_ops.pwr_domain_suspend()
2506..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002507
2508Perform the platform specific actions to prepare to suspend the calling
2509CPU and its higher parent power domain levels as indicated by the
2510``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2511API implementation.
2512
2513The ``target_state`` has a similar meaning as described in
2514the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2515target local power states for the CPU power domain and its parent
2516power domain levels. The handler needs to perform power management operation
2517corresponding to the local state at each power level. The generic code
2518expects the handler to succeed.
2519
Douglas Raillarda84996b2017-08-02 16:57:32 +01002520The difference between turning a power domain off versus suspending it is that
2521in the former case, the power domain is expected to re-initialize its state
2522when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2523case, the power domain is expected to save enough state so that it can resume
2524execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002525``pwr_domain_suspend_finish()``).
2526
Douglas Raillarda84996b2017-08-02 16:57:32 +01002527When suspending a core, the platform can also choose to power off the GICv3
2528Redistributor and ITS through an implementation-defined sequence. To achieve
2529this safely, the ITS context must be saved first. The architectural part is
2530implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2531sequence is implementation defined and it is therefore the responsibility of
2532the platform code to implement the necessary sequence. Then the GIC
2533Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2534Powering off the Redistributor requires the implementation to support it and it
2535is the responsibility of the platform code to execute the right implementation
2536defined sequence.
2537
2538When a system suspend is requested, the platform can also make use of the
2539``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2540it has saved the context of the Redistributors and ITS of all the cores in the
2541system. The context of the Distributor can be large and may require it to be
2542allocated in a special area if it cannot fit in the platform's global static
2543data, for example in DRAM. The Distributor can then be powered down using an
2544implementation-defined sequence.
2545
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002546plat_psci_ops.pwr_domain_pwr_down_wfi()
2547.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002548
2549This is an optional function and, if implemented, is expected to perform
2550platform specific actions including the ``wfi`` invocation which allows the
2551CPU to powerdown. Since this function is invoked outside the PSCI locks,
2552the actions performed in this hook must be local to the CPU or the platform
2553must ensure that races between multiple CPUs cannot occur.
2554
2555The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2556operation and it encodes the platform coordinated target local power states for
2557the CPU power domain and its parent power domain levels. This function must
2558not return back to the caller.
2559
2560If this function is not implemented by the platform, PSCI generic
2561implementation invokes ``psci_power_down_wfi()`` for power down.
2562
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002563plat_psci_ops.pwr_domain_on_finish()
2564....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002565
2566This function is called by the PSCI implementation after the calling CPU is
2567powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2568It performs the platform-specific setup required to initialize enough state for
2569this CPU to enter the normal world and also provide secure runtime firmware
2570services.
2571
2572The ``target_state`` (first argument) is the prior state of the power domains
2573immediately before the CPU was turned on. It indicates which power domains
2574above the CPU might require initialization due to having previously been in
2575low power states. The generic code expects the handler to succeed.
2576
Madhukar Pappireddy33bd5142019-08-12 18:31:33 -05002577plat_psci_ops.pwr_domain_on_finish_late() [optional]
2578...........................................................
2579
2580This optional function is called by the PSCI implementation after the calling
2581CPU is fully powered on with respective data caches enabled. The calling CPU and
2582the associated cluster are guaranteed to be participating in coherency. This
2583function gives the flexibility to perform any platform-specific actions safely,
2584such as initialization or modification of shared data structures, without the
2585overhead of explicit cache maintainace operations.
2586
2587The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2588operation. The generic code expects the handler to succeed.
2589
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002590plat_psci_ops.pwr_domain_suspend_finish()
2591.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002592
2593This function is called by the PSCI implementation after the calling CPU is
2594powered on and released from reset in response to an asynchronous wakeup
2595event, for example a timer interrupt that was programmed by the CPU during the
2596``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2597setup required to restore the saved state for this CPU to resume execution
2598in the normal world and also provide secure runtime firmware services.
2599
2600The ``target_state`` (first argument) has a similar meaning as described in
2601the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2602to succeed.
2603
Douglas Raillarda84996b2017-08-02 16:57:32 +01002604If the Distributor, Redistributors or ITS have been powered off as part of a
2605suspend, their context must be restored in this function in the reverse order
2606to how they were saved during suspend sequence.
2607
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002608plat_psci_ops.system_off()
2609..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002610
2611This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2612call. It performs the platform-specific system poweroff sequence after
2613notifying the Secure Payload Dispatcher.
2614
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002615plat_psci_ops.system_reset()
2616............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002617
2618This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2619call. It performs the platform-specific system reset sequence after
2620notifying the Secure Payload Dispatcher.
2621
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002622plat_psci_ops.validate_power_state()
2623....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002624
2625This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2626call to validate the ``power_state`` parameter of the PSCI API and if valid,
2627populate it in ``req_state`` (second argument) array as power domain level
2628specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002629return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002630normal world PSCI client.
2631
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002632plat_psci_ops.validate_ns_entrypoint()
2633......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002634
2635This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2636``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2637parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002638the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002639propagated back to the normal world PSCI client.
2640
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002641plat_psci_ops.get_sys_suspend_power_state()
2642...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002643
2644This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2645call to get the ``req_state`` parameter from platform which encodes the power
2646domain level specific local states to suspend to system affinity level. The
2647``req_state`` will be utilized to do the PSCI state coordination and
2648``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2649enter system suspend.
2650
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002651plat_psci_ops.get_pwr_lvl_state_idx()
2652.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002653
2654This is an optional function and, if implemented, is invoked by the PSCI
2655implementation to convert the ``local_state`` (first argument) at a specified
2656``pwr_lvl`` (second argument) to an index between 0 and
2657``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2658supports more than two local power states at each power domain level, that is
2659``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2660local power states.
2661
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002662plat_psci_ops.translate_power_state_by_mpidr()
2663..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002664
2665This is an optional function and, if implemented, verifies the ``power_state``
2666(second argument) parameter of the PSCI API corresponding to a target power
2667domain. The target power domain is identified by using both ``MPIDR`` (first
2668argument) and the power domain level encoded in ``power_state``. The power domain
2669level specific local states are to be extracted from ``power_state`` and be
2670populated in the ``output_state`` (third argument) array. The functionality
2671is similar to the ``validate_power_state`` function described above and is
2672envisaged to be used in case the validity of ``power_state`` depend on the
2673targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002674domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002675function is not implemented, then the generic implementation relies on
2676``validate_power_state`` function to translate the ``power_state``.
2677
2678This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002679power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002680APIs as described in Section 5.18 of `PSCI`_.
2681
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002682plat_psci_ops.get_node_hw_state()
2683.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002684
2685This is an optional function. If implemented this function is intended to return
2686the power state of a node (identified by the first parameter, the ``MPIDR``) in
2687the power domain topology (identified by the second parameter, ``power_level``),
2688as retrieved from a power controller or equivalent component on the platform.
2689Upon successful completion, the implementation must map and return the final
2690status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2691must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2692appropriate.
2693
2694Implementations are not expected to handle ``power_levels`` greater than
2695``PLAT_MAX_PWR_LVL``.
2696
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002697plat_psci_ops.system_reset2()
2698.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002699
2700This is an optional function. If implemented this function is
2701called during the ``SYSTEM_RESET2`` call to perform a reset
2702based on the first parameter ``reset_type`` as specified in
2703`PSCI`_. The parameter ``cookie`` can be used to pass additional
2704reset information. If the ``reset_type`` is not supported, the
2705function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2706resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2707and vendor reset can return other PSCI error codes as defined
2708in `PSCI`_. On success this function will not return.
2709
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002710plat_psci_ops.write_mem_protect()
2711.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002712
2713This is an optional function. If implemented it enables or disables the
2714``MEM_PROTECT`` functionality based on the value of ``val``.
2715A non-zero value enables ``MEM_PROTECT`` and a value of zero
2716disables it. Upon encountering failures it must return a negative value
2717and on success it must return 0.
2718
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002719plat_psci_ops.read_mem_protect()
2720................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002721
2722This is an optional function. If implemented it returns the current
2723state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2724failures it must return a negative value and on success it must
2725return 0.
2726
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002727plat_psci_ops.mem_protect_chk()
2728...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002729
2730This is an optional function. If implemented it checks if a memory
2731region defined by a base address ``base`` and with a size of ``length``
2732bytes is protected by ``MEM_PROTECT``. If the region is protected
2733then it must return 0, otherwise it must return a negative number.
2734
Paul Beesleyf8640672019-04-12 14:19:42 +01002735.. _porting_guide_imf_in_bl31:
2736
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002737Interrupt Management framework (in BL31)
2738----------------------------------------
2739
2740BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2741generated in either security state and targeted to EL1 or EL2 in the non-secure
2742state or EL3/S-EL1 in the secure state. The design of this framework is
Paul Beesleyf8640672019-04-12 14:19:42 +01002743described in the :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002744
2745A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002746text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002747platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00002748present in the platform. Arm standard platform layer supports both
2749`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2750and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2751FVP can be configured to use either GICv2 or GICv3 depending on the build flag
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002752``FVP_USE_GIC_DRIVER`` (See :ref:`build_options_arm_fvp_platform` for more
2753details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002754
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05002755See also: :ref:`Interrupt Controller Abstraction APIs<Platform Interrupt Controller API>`.
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002756
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002757Function : plat_interrupt_type_to_line() [mandatory]
2758~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002759
2760::
2761
2762 Argument : uint32_t, uint32_t
2763 Return : uint32_t
2764
Dan Handley610e7e12018-03-01 18:44:00 +00002765The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002766interrupt line. The specific line that is signaled depends on how the interrupt
2767controller (IC) reports different interrupt types from an execution context in
2768either security state. The IMF uses this API to determine which interrupt line
2769the platform IC uses to signal each type of interrupt supported by the framework
2770from a given security state. This API must be invoked at EL3.
2771
2772The first parameter will be one of the ``INTR_TYPE_*`` values (see
Paul Beesleyf8640672019-04-12 14:19:42 +01002773:ref:`Interrupt Management Framework`) indicating the target type of the
2774interrupt, the second parameter is the security state of the originating
2775execution context. The return result is the bit position in the ``SCR_EL3``
2776register of the respective interrupt trap: IRQ=1, FIQ=2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002777
Dan Handley610e7e12018-03-01 18:44:00 +00002778In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002779configured as FIQs and Non-secure interrupts as IRQs from either security
2780state.
2781
Dan Handley610e7e12018-03-01 18:44:00 +00002782In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002783configured depends on the security state of the execution context when the
2784interrupt is signalled and are as follows:
2785
2786- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
2787 NS-EL0/1/2 context.
2788- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
2789 in the NS-EL0/1/2 context.
2790- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
2791 context.
2792
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002793Function : plat_ic_get_pending_interrupt_type() [mandatory]
2794~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002795
2796::
2797
2798 Argument : void
2799 Return : uint32_t
2800
2801This API returns the type of the highest priority pending interrupt at the
2802platform IC. The IMF uses the interrupt type to retrieve the corresponding
2803handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
2804pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
2805``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
2806
Dan Handley610e7e12018-03-01 18:44:00 +00002807In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002808Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
2809the pending interrupt. The type of interrupt depends upon the id value as
2810follows.
2811
2812#. id < 1022 is reported as a S-EL1 interrupt
2813#. id = 1022 is reported as a Non-secure interrupt.
2814#. id = 1023 is reported as an invalid interrupt type.
2815
Dan Handley610e7e12018-03-01 18:44:00 +00002816In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002817``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2818is read to determine the id of the pending interrupt. The type of interrupt
2819depends upon the id value as follows.
2820
2821#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
2822#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
2823#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
2824#. All other interrupt id's are reported as EL3 interrupt.
2825
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002826Function : plat_ic_get_pending_interrupt_id() [mandatory]
2827~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002828
2829::
2830
2831 Argument : void
2832 Return : uint32_t
2833
2834This API returns the id of the highest priority pending interrupt at the
2835platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
2836pending.
2837
Dan Handley610e7e12018-03-01 18:44:00 +00002838In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002839Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
2840pending interrupt. The id that is returned by API depends upon the value of
2841the id read from the interrupt controller as follows.
2842
2843#. id < 1022. id is returned as is.
2844#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
2845 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
2846 This id is returned by the API.
2847#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
2848
Dan Handley610e7e12018-03-01 18:44:00 +00002849In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002850EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
2851group 0 Register*, is read to determine the id of the pending interrupt. The id
2852that is returned by API depends upon the value of the id read from the
2853interrupt controller as follows.
2854
2855#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
2856#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
2857 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2858 Register* is read to determine the id of the group 1 interrupt. This id
2859 is returned by the API as long as it is a valid interrupt id
2860#. If the id is any of the special interrupt identifiers,
2861 ``INTR_ID_UNAVAILABLE`` is returned.
2862
2863When the API invoked from S-EL1 for GICv3 systems, the id read from system
2864register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002865Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002866``INTR_ID_UNAVAILABLE`` is returned.
2867
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002868Function : plat_ic_acknowledge_interrupt() [mandatory]
2869~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002870
2871::
2872
2873 Argument : void
2874 Return : uint32_t
2875
2876This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002877the highest pending interrupt has begun. It should return the raw, unmodified
2878value obtained from the interrupt controller when acknowledging an interrupt.
2879The actual interrupt number shall be extracted from this raw value using the API
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05002880`plat_ic_get_interrupt_id()<plat_ic_get_interrupt_id>`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002881
Dan Handley610e7e12018-03-01 18:44:00 +00002882This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002883Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
2884priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002885It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002886
Dan Handley610e7e12018-03-01 18:44:00 +00002887In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002888from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
2889Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2890reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
2891group 1*. The read changes the state of the highest pending interrupt from
2892pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002893unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002894
2895The TSP uses this API to start processing of the secure physical timer
2896interrupt.
2897
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002898Function : plat_ic_end_of_interrupt() [mandatory]
2899~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002900
2901::
2902
2903 Argument : uint32_t
2904 Return : void
2905
2906This API is used by the CPU to indicate to the platform IC that processing of
2907the interrupt corresponding to the id (passed as the parameter) has
2908finished. The id should be the same as the id returned by the
2909``plat_ic_acknowledge_interrupt()`` API.
2910
Dan Handley610e7e12018-03-01 18:44:00 +00002911Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002912(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
2913system register in case of GICv3 depending on where the API is invoked from,
2914EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
2915controller.
2916
2917The TSP uses this API to finish processing of the secure physical timer
2918interrupt.
2919
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002920Function : plat_ic_get_interrupt_type() [mandatory]
2921~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002922
2923::
2924
2925 Argument : uint32_t
2926 Return : uint32_t
2927
2928This API returns the type of the interrupt id passed as the parameter.
2929``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
2930interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
2931returned depending upon how the interrupt has been configured by the platform
2932IC. This API must be invoked at EL3.
2933
Dan Handley610e7e12018-03-01 18:44:00 +00002934Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002935and Non-secure interrupts as Group1 interrupts. It reads the group value
2936corresponding to the interrupt id from the relevant *Interrupt Group Register*
2937(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
2938
Dan Handley610e7e12018-03-01 18:44:00 +00002939In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002940Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
2941(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
2942as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
2943
2944Crash Reporting mechanism (in BL31)
2945-----------------------------------
2946
2947BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002948of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002949on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002950``plat_crash_console_putc`` and ``plat_crash_console_flush``.
2951
2952The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
2953implementation of all of them. Platforms may include this file to their
2954makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002955output to be routed over the normal console infrastructure and get printed on
2956consoles configured to output in crash state. ``console_set_scope()`` can be
2957used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00002958
2959.. note::
2960 Platforms are responsible for making sure that they only mark consoles for
2961 use in the crash scope that are able to support this, i.e. that are written
2962 in assembly and conform with the register clobber rules for putc()
2963 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002964
Julius Werneraae9bb12017-09-18 16:49:48 -07002965In some cases (such as debugging very early crashes that happen before the
2966normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08002967more explicitly. These platforms may instead provide custom implementations for
2968these. They are executed outside of a C environment and without a stack. Many
2969console drivers provide functions named ``console_xxx_core_init/putc/flush``
2970that are designed to be used by these functions. See Arm platforms (like juno)
2971for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002972
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002973Function : plat_crash_console_init [mandatory]
2974~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002975
2976::
2977
2978 Argument : void
2979 Return : int
2980
2981This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002982console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002983initialization and returns 1 on success.
2984
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002985Function : plat_crash_console_putc [mandatory]
2986~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002987
2988::
2989
2990 Argument : int
2991 Return : int
2992
2993This API is used by the crash reporting mechanism to print a character on the
2994designated crash console. It must only use general purpose registers x1 and
2995x2 to do its work. The parameter and the return value are in general purpose
2996register x0.
2997
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002998Function : plat_crash_console_flush [mandatory]
2999~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003000
3001::
3002
3003 Argument : void
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003004 Return : void
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003005
3006This API is used by the crash reporting mechanism to force write of all buffered
3007data on the designated crash console. It should only use general purpose
Jimmy Brisson39f9eee2020-08-05 13:44:05 -05003008registers x0 through x5 to do its work.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003009
Manish Pandey9c9f38a2020-06-30 00:46:08 +01003010.. _External Abort handling and RAS Support:
3011
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01003012External Abort handling and RAS Support
3013---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01003014
3015Function : plat_ea_handler
3016~~~~~~~~~~~~~~~~~~~~~~~~~~
3017
3018::
3019
3020 Argument : int
3021 Argument : uint64_t
3022 Argument : void *
3023 Argument : void *
3024 Argument : uint64_t
3025 Return : void
3026
3027This function is invoked by the RAS framework for the platform to handle an
3028External Abort received at EL3. The intention of the function is to attempt to
3029resolve the cause of External Abort and return; if that's not possible, to
3030initiate orderly shutdown of the system.
3031
3032The first parameter (``int ea_reason``) indicates the reason for External Abort.
3033Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
3034
3035The second parameter (``uint64_t syndrome``) is the respective syndrome
3036presented to EL3 after having received the External Abort. Depending on the
3037nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
3038can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
3039
3040The third parameter (``void *cookie``) is unused for now. The fourth parameter
3041(``void *handle``) is a pointer to the preempted context. The fifth parameter
3042(``uint64_t flags``) indicates the preempted security state. These parameters
3043are received from the top-level exception handler.
3044
3045If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
3046function iterates through RAS handlers registered by the platform. If any of the
3047RAS handlers resolve the External Abort, no further action is taken.
3048
3049If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
3050could resolve the External Abort, the default implementation prints an error
3051message, and panics.
3052
3053Function : plat_handle_uncontainable_ea
3054~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3055
3056::
3057
3058 Argument : int
3059 Argument : uint64_t
3060 Return : void
3061
3062This function is invoked by the RAS framework when an External Abort of
3063Uncontainable type is received at EL3. Due to the critical nature of
3064Uncontainable errors, the intention of this function is to initiate orderly
3065shutdown of the system, and is not expected to return.
3066
3067This function must be implemented in assembly.
3068
3069The first and second parameters are the same as that of ``plat_ea_handler``.
3070
3071The default implementation of this function calls
3072``report_unhandled_exception``.
3073
3074Function : plat_handle_double_fault
3075~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3076
3077::
3078
3079 Argument : int
3080 Argument : uint64_t
3081 Return : void
3082
3083This function is invoked by the RAS framework when another External Abort is
3084received at EL3 while one is already being handled. I.e., a call to
3085``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
3086this function is to initiate orderly shutdown of the system, and is not expected
3087recover or return.
3088
3089This function must be implemented in assembly.
3090
3091The first and second parameters are the same as that of ``plat_ea_handler``.
3092
3093The default implementation of this function calls
3094``report_unhandled_exception``.
3095
3096Function : plat_handle_el3_ea
3097~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3098
3099::
3100
3101 Return : void
3102
3103This function is invoked when an External Abort is received while executing in
3104EL3. Due to its critical nature, the intention of this function is to initiate
3105orderly shutdown of the system, and is not expected recover or return.
3106
3107This function must be implemented in assembly.
3108
3109The default implementation of this function calls
3110``report_unhandled_exception``.
3111
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003112Build flags
3113-----------
3114
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003115There are some build flags which can be defined by the platform to control
3116inclusion or exclusion of certain BL stages from the FIP image. These flags
3117need to be defined in the platform makefile which will get included by the
3118build system.
3119
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01003120- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003121 By default, this flag is defined ``yes`` by the build system and ``BL33``
3122 build option should be supplied as a build option. The platform has the
3123 option of excluding the BL33 image in the ``fip`` image by defining this flag
3124 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
3125 are used, this flag will be set to ``no`` automatically.
3126
Paul Beesley07f0a312019-05-16 13:33:18 +01003127Platform include paths
3128----------------------
3129
3130Platforms are allowed to add more include paths to be passed to the compiler.
3131The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
3132particular for the file ``platform_def.h``.
3133
3134Example:
3135
3136.. code:: c
3137
3138 PLAT_INCLUDES += -Iinclude/plat/myplat/include
3139
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003140C Library
3141---------
3142
3143To avoid subtle toolchain behavioral dependencies, the header files provided
3144by the compiler are not used. The software is built with the ``-nostdinc`` flag
3145to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00003146required headers are included in the TF-A source tree. The library only
3147contains those C library definitions required by the local implementation. If
3148more functionality is required, the needed library functions will need to be
3149added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003150
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003151Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
Paul Beesleyf2ec7142019-10-04 16:17:46 +00003152been written specifically for TF-A. Some implementation files have been obtained
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003153from `FreeBSD`_, others have been written specifically for TF-A as well. The
3154files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003155
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01003156SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
3157can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003158
3159Storage abstraction layer
3160-------------------------
3161
Louis Mayencourtb5469002019-07-15 13:56:03 +01003162In order to improve platform independence and portability a storage abstraction
3163layer is used to load data from non-volatile platform storage. Currently
3164storage access is only required by BL1 and BL2 phases and performed inside the
3165``load_image()`` function in ``bl_common.c``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003166
Louis Mayencourtb5469002019-07-15 13:56:03 +01003167.. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003168
Dan Handley610e7e12018-03-01 18:44:00 +00003169It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003170development platforms the Firmware Image Package (FIP) driver is provided as
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01003171the default means to load data from storage (see :ref:`firmware_design_fip`).
3172The storage layer is described in the header file
3173``include/drivers/io/io_storage.h``. The implementation of the common library is
3174in ``drivers/io/io_storage.c`` and the driver files are located in
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003175``drivers/io/``.
3176
Louis Mayencourtb5469002019-07-15 13:56:03 +01003177.. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
3178
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003179Each IO driver must provide ``io_dev_*`` structures, as described in
3180``drivers/io/io_driver.h``. These are returned via a mandatory registration
3181function that is called on platform initialization. The semi-hosting driver
3182implementation in ``io_semihosting.c`` can be used as an example.
3183
Louis Mayencourtb5469002019-07-15 13:56:03 +01003184Each platform should register devices and their drivers via the storage
3185abstraction layer. These drivers then need to be initialized by bootloader
3186phases as required in their respective ``blx_platform_setup()`` functions.
3187
3188.. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
3189
3190The storage abstraction layer provides mechanisms (``io_dev_init()``) to
3191initialize storage devices before IO operations are called.
3192
3193.. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
3194
3195The basic operations supported by the layer
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003196include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
3197Drivers do not have to implement all operations, but each platform must
3198provide at least one driver for a device capable of supporting generic
3199operations such as loading a bootloader image.
3200
3201The current implementation only allows for known images to be loaded by the
3202firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00003203``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003204there). The platform layer (``plat_get_image_source()``) then returns a reference
3205to a device and a driver-specific ``spec`` which will be understood by the driver
3206to allow access to the image data.
3207
3208The layer is designed in such a way that is it possible to chain drivers with
3209other drivers. For example, file-system drivers may be implemented on top of
3210physical block devices, both represented by IO devices with corresponding
3211drivers. In such a case, the file-system "binding" with the block device may
3212be deferred until the file-system device is initialised.
3213
3214The abstraction currently depends on structures being statically allocated
3215by the drivers and callers, as the system does not yet provide a means of
3216dynamically allocating memory. This may also have the affect of limiting the
3217amount of open resources per driver.
3218
3219--------------
3220
Soby Mathewf05d93a2022-03-22 16:21:19 +00003221*Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003222
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003223.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +00003224.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003225.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00003226.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01003227.. _SCC: http://www.simple-cc.org/